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Microelectronics Reliability 47 (2007) 841–852

Negative bias temperature instability: What do we understand?

Dieter K. Schroder

Department of Electrical Engineering and Center for Solid State Electronics Research, Arizona State University, Tempe, AZ 85287-5706, USA

Received 24 May 2006; received in revised form 31 August 2006Available online 1 December 2006

Abstract

We present a brief overview of negative bias temperature instability (NBTI) commonly observed for in p-channel metal–oxide–semi-conductor field-effect transistors (MOSFETs) when stressed with negative gate voltages at elevated temperatures and discuss the resultsof such stress on device and circuit performance and review interface traps and oxide charges, their origin, present understanding, andchanges due to NBTI. Next we discuss some of the models that have been proposed for both NBTI degradation and recovery andp- versus n-MOSFETs. We also address the time and energy dependence effects of NBTI and crystal orientation. Finally we mentionsome aspect of circuit degradation. The general conclusion is that although we understand much about NBTI, several aspects are poorlyunderstood. This may be due to a lack of a basic understanding or due to varying experimental data that are likely the result of samplepreparation and measurement conditions.� 2006 Published by Elsevier Ltd.

1. Introduction

Negative bias temperature instability has been knownsince 1966 [1]. It is only during the last few years, however,that it has become a reliability issue in silicon integratedcircuits, because the gate electric fields have increased asa result of scaling, increased chip operating temperature,surface p-channel MOSFETs have replaced buried channeldevices, and nitrogen is routinely added to thermally grownSiO2. In 2003, we wrote a review paper on NBTI and triedto include most of the published literature up to that time[2]. Although many papers had been published at that time,there was much discrepancy between the various modelsand the experimental data. For example, it was poorlyunderstood that the time between NBTI stress and measur-ing the effect after terminating the stress was important,because the NBTI recovery was just beginning to be under-stood. Now it is understood that the sooner a degradeddevice is measured after stress, i.e., within ms or sooner,the more relevant are the data. Since the publication ofour paper, many more papers have been published andNBTI is beginning to be understood better. Nevertheless,

0026-2714/$ - see front matter � 2006 Published by Elsevier Ltd.

doi:10.1016/j.microrel.2006.10.006

E-mail address: [email protected]

there are still many gaps and experimental data sometimescontradict each other. Several excellent review papers havesince been published. In this paper, I will draw upon theexcellent recent reviews by Stathis and Zafar [3], Huardet al. [4], and Alam and Mahapatra [5] as well as manyother papers published in the last few years. In particular,the careful, detailed measurements of Huard et al. haveconfirmed or debunked some earlier assumptions and Idraw heavily on their results. I have attempted to highlightthose NBTI areas where there is considerable uncertaintyand where experimental results contradict each other. Tohighlight our understanding or misunderstanding I haveended most sections with questions.

2. What is NBTI?

NBTI is an increase in the absolute threshold voltage, adegradation of the mobility, drain current, and transcon-ductance of p-channel MOSFETs. It is almost universallyattributed to the creation of interface traps and oxidecharge by a negative gate bias at elevated temperature.The oxide electric field is usually, but not always, lowerthan that leading to hot carrier degradation. The oxideelectric field and temperature are similar to those typically

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842 D.K. Schroder / Microelectronics Reliability 47 (2007) 841–852

encountered during burn-in and sometimes encounteredduring high-performance chip operation. The details ofhow NBTI occurs are not entirely clear, however. Sincemuch has been written about the origin of NBTI, we willtouch on it only briefly. The mechanism is ascribed tobreaking of SiH bonds at the SiO2/Si substrate interfaceby a combination of electric field, temperature, and holes,resulting in dangling bonds or interface traps at that inter-face, designated as Dit and Nit, and positive oxide charge,Not, that may be due to H+ or trapped holes. Detailed mea-surements by various researchers have shown the activa-tion energy and time dependence to differ for Dit and Not

generation.

3. NBTI models

Various NBTI models have been proposed, of which theReaction–Diffusion (R–D) model is the most prevalent [5–7]. In this model, interface traps are generated at theSiO2/Si interface (reaction) with a linear dependence onstress time. Hydrogen is released during this reactionphase. In the subsequent diffusion phase, the hydrogen dif-fuses from the interface into the oxide (diffusion) with thetime dependence tn, where n for neutral hydrogen speciesis frequently given as 0.25. It may also be possible forhydrogen to diffuse into the substrate. While the diffu-sion-limited regime has been verified many times, the reac-tion-limiting regime has not as frequently been observed,because it occurs during a very short time. Yang et al.extended the stress measurement times from 10�3 to 102 sand show the n = 1 and n = 0.25 dependence, with thebreakpoint between the two regimes occurring att � 0.02–0.03 s, shown in Fig. 1 [8]. A caution about thedata in Ref. [8]. The measurements are affected by thestress-to-measure delay and the n = 1 value is likely to belower if this delay is considered. By measuring NBTI deg-radation as a function of nitrogen density in nitrided oxi-des, they conclude that Dit generation is enhanced bynitrogen and it is mainly due to enhanced hydrogen diffu-

109

1010

1011

1012

10-3 10-2 10-1 100 101 102

ΔNit (

cm-2

)

Stress Time (s)

VG =-2.2 V

T=125oCtox=1.8 nm

Fig. 1. Measured and simulated interface trap density change DNit versusstress time for 15% nitrogen concentration. In Eq. (1): A = 2.67 ·1012 cm�2/s, B = 6.95 · 10�11 cm2/s1/2, DH = 8.28 · 10�16 cm2/s, W/L =20 lm/0.15 lm. After Yang et al. [8].

sion in the nitrided oxide. This enhanced diffusion aidsDit generation.

The generation of interface traps is given by [8]

DN itðtÞ ¼2At

1þffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi1þ 4ABt3=2

p

¼ 2kFN 0t

1þffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi1þ 4kFN 0kRt3=2=ð0:5

ffiffiffiffiffiffiffiDH

pÞ

p ð1Þ

where kF is the forward reaction rate, kR the reverse reac-tion rate, N0 the initial defect density, and DH the hydrogendiffusion coefficient. According to Eq. (1), for small t dur-ing the reaction phase of NBTI degradation

DN itðtÞ � At ¼ kFN 0t ð2aÞ

and during the diffusion phase at later times

DN itðtÞ �ffiffiffiAB

rt1=4 ¼

ffiffiffiffiffiffiffiffiffiffiffikFN 0

2kR

rðDHtÞ1=4 ð2bÞ

Eq. (1) is plotted in Fig. 1 together with experimental data.There is little controversy about the applicability of the

R–D model to NBTI. What is still debated is the time expo-nent n, which is predicted to be 0.25 above, but frequentlyobserved to be lower. The true value is important to be ableto predict NBTI lifetimes. The generation of interface trapsis universally accepted, but, the nature of the positiveoxide charge generated during NBTI stress is not clearyet. It has been attributed to hole traps and also to trappedhydrogen.

Question: Is the R&D model the best model? Does reac-tion dominate at short times and diffusion at longer times?What is the true n value?

4. Interface traps and oxide charges

Silicon is tetrahedrally bonded with each Si atombonded to four Si atoms in the wafer bulk. When the Siis oxidized, the bonding configuration at the surface is asshown in Fig. 2(a) for (111) and (b) for (100) orientationwith most Si atoms bonded to oxygen. Some Si atoms bondto hydrogen. An interface trapped charge, often calledinterface trap, is an interface trivalent Si atom with anunsaturated (unpaired) valence electron at the SiO2/Siinterface, denoted by

Si3 � Si� ð3Þ

Si O Pb

Silicon (111)

HPb0

Silicon (100)

Pb1

Fig. 2. Structural model of the (a): (111)Si surface and (b): (100)Sisurface.

EV

EC

Ei

EF

"0"Acceptors

EV

EC

Ei

EF

Dit

Donors "0"

"-" "0""+"

"0"

Fig. 3. Band diagrams of the Si substrate of a p-channel MOS deviceshowing the occupancy of interface traps and the various charge polaritiesfor a p-substrate with (a) negative interface trap charge at flatband and (b)positive interface trap charge at inversion. Each of the small horizontallines represents an interface trap. It is either occupied by an electron (solidcircle) or occupied by a hole (unoccupied by an electron), shown by thelines.

D.K. Schroder / Microelectronics Reliability 47 (2007) 841–852 843

The ‘‘�’’ represents three complete bonds to other Si atoms(the Si3) and the ‘‘•’’ represents the fourth, unpaired elec-tron in a dangling orbital (dangling bond). Interface trapsare also known as Pb centers [9]. Interface traps are desig-nated as Dit (cm�2 eV�1), Qit (C/cm2), and Nit (cm�2).

On (11 1)-oriented wafers, the Pb center is a Si3 � Si•center, situated at the Si/SiO2 interface with its unbondedcentral-atom orbital perpendicular to the interface andaimed into a vacancy in the oxide immediately above it,as shown in Fig. 2(a). On (100)Si, the four tetrahedralSi–Si directions intersect the interface plane at the sameangle. Two defects, named Pb1 and Pb0, have been detectedby electron spin resonance (ESR), shown in Fig. 2(b). ThePb1 center was originally thought to be a Si atom back-bonded to two substrate Si atoms, with the third saturatedbond attached to an oxygen atom, designated asSi2O � Si•. This identification was found to be incorrect,as the calculated energy levels for this defect do not agreewith experiment [10]. A recent calculation suggests thePb1 center to be an asymmetrically oxidized dimer, withno first neighbor oxygen atoms [11]. By 1999, it was unam-biguously established that both Pb0 and Pb1 are chemicallyidentical to the Pb center [12]. However, there is a chargestate difference between these two centers indicating Pb0

is electrically active, while some authors believe the Pb1

to be electrically inactive [13]. The two different effectsare the result of strain relief in (100) silicon. The defectsresult from the naturally occurring mismatch-inducedstress at the SiO2/Si interface during oxide growth.

Pb0 centers result when strain relaxation occurs with adefect residing at (111) microfacets at the Si/SiO2 inter-face, while Pb1 centers result when strain relaxation occurswith a defect at (100)Si/SiO2 transition regions. Based onthese results and the fact that Pb1 centers are believed tobe electrically inactive, defects resulting from Pb0 centersare considered the key culprits in creating interface trapsin (100) silicon. It is worth mentioning that recent workindicates Pb1 centers to be electrically inactive at low tem-peratures (T = 77 K). However, at room temperature andhigher these defects contribute to the electrical activity oftotal interface traps [14]. Recent ESR measurements showthe Pb1 center to be electrically active with two distinct,narrow peaks close to midgap in the silicon band gap[15]. However, Pb1 centers are typically generated at densi-ties considerably lower than Pb0 centers, making thempotentially less important.

Interface traps are electrically active defects with anenergy distribution throughout the Si band gap. They actas generation/recombination centers and contribute toleakage current, low-frequency noise, and reduced mobil-ity, drain current, and transconductance. Since electronsor holes occupy interface traps, they become charged andcontribute to threshold voltage shifts. The surface potentialdependence of the occupancy of interface traps is illus-trated in Fig. 3.

Interface traps at the SiO2/Si interface are acceptor-likein the upper half and donor-like in the lower half of the

band gap [16]. Hence, as shown in Fig. 3(a), at flatband,with electrons occupying states below the Fermi energy,the states in the lower half of the band gap are neutral(occupied donors designated by ‘‘0’’). Those between mid-gap and the Fermi energy are negatively charged (occupiedacceptors designated by ‘‘�‘‘), and those above EF are neu-tral (unoccupied acceptors). For an inverted p-MOSFET,shown in Fig. 3(b), the fraction of interface traps betweenmid gap and the Fermi level is now unoccupied donors,leading to positively charged interface traps (designatedby ‘‘+’’). Hence interface traps in p-channel devices ininversion are positively charged, leading to negative thresh-old voltage shifts. Negative bias stress generates donorstates in the lower half of the band gap [17,18].

The oxide charge that contributes to NBTI is not wellunderstood. Oxide charge can consist of various entities,including mobile charge, e.g., Na, K, Li, oxide trappedcharge, e.g., electrons and/or holes, and fixed charge. Weexclude mobile charge, because NBTI is observed whenthere is no mobile charge. Oxide charge is located withinthe oxide and may communicate with the Si conductionand valence bands and it is positive. Some believe it isH+ trapped in the oxide near the SiO2/Si interface. How-ever, it is generally believed that hole trapping is the dom-inant mechanism and that the hole traps or their precursorsmay exist in the insulator prior to the stress.

The traps are positively charged when occupied by holesand neutral when unoccupied. It is possible that such posi-tively charged traps can be neutralized by electrons whenthe n-substrate is at flatband and in accumulation. Similartraps have been proposed to be responsible for low-frequency (lf) noise where electrons or holes tunnel intotraps [19]. The trap distance from the SiO2/Si interfacedetermines the tunnel time and hence the lf noise frequencyresponse. Typical trap distances are 1–2 nm. The range 0.9–1.75 nm covers the frequency range 1–104 Hz where 10 Hzcorresponds to �2 nm distance. If carriers can tunnel overthis frequency range that would correspond to tunnel timesof 10�4–1 s and suggests that the positive charge can be dis-charged in very short times, as suggested by NBTI experi-ments. Oxide charge located closer to the oxide/substrate


interface leads to higher threshold voltage shifts than chargenear the gate/oxide interface. It is rarely pointed out thatcharge build-up in the oxide also alters the oxide electricfield. Depending on the charge and their location, the oxideelectric field may increase or decrease locally, e.g., near theSiO2/substrate interface.

The NBTI threshold voltage change does not depend onthe hole density, determined by changing the channel holedensity and measuring the threshold voltage change. Thehole density can be changed by changing VT through fab-rication or substrate bias. When this was done, there wasvery little change in interface trap generation, indicatingthat hole density is a secondary effect [4,20]. However, itappears that holes are required for NBTI degradation.

The p-MOSFET threshold voltage is

V T ¼ /MS �Qox

Cox

� Qitð2/FÞCox

� 2/F �QS

Cox

ð4Þ

where /MS is the work function difference between the gateand substrate, /F the Fermi potential, Qox the positiveoxide charge density, QS the semiconductor charge density,and Cox the oxide capacitance/unit area. Qit, shown to bedependent on the surface potential in Fig. 3, is given by

Qit ¼ qDitDE ¼ qN it ð5Þ

where DE is the energy range over which interface traps areactive. Qit may be positive or negative (Fig. 3).

Since neither gate nor substrate doping density noroxide thickness change during stress, the threshold voltagechange is due to changes in Qox and Qit as

DV T ¼ �DQox þ DQit

Cox

¼ � qðDN ox þ DN itÞKoxe0

tox

¼ �4:6� 10�7ðDNox þ DN itÞtox ð6Þ

In today’s ICs, Nox and Nit are approximately 1010 cm�2 orslightly less before stress. Typical DVT is on the order of�10 mV leading to DNox + DNit � 1011 cm�2 for tox =2 nm, showing the NBTI-generated charges/states are typi-cally higher than the starting values. How many SiH bondsare there to be dissociated? After Si oxidation, Nit = 1012–1013 cm�2 which is reduced to approximately 1010 cm�2

0

0.2

0.4

0.6

0.8

1

0 1000 2000 3000

Rel

ativ

e ΔV

T

Stress Time (s)

T=125oCVG<0 VG>0

Fig. 4. Relative shifts for (a) DVT and (b) DNit versus st

after low-temperature forming gas anneal. This suggeststhat DVT may approach�100 mV or higher after prolongedstress before the 1012–1013 cm�2 SiH bonds are broken.

Question: While it is generally accepted that interfacetraps are one of the NBTI culprits, the oxide charge is lesswell understood. Is the positive charge due to hydrogen ortrapped holes? Are the hole traps induced by NBTI stressor are they pre-existent in the oxide?

5. NBTI recovery

Until recently, most NBTI measurements were made bystressing the device, then measuring the threshold voltage,interface trap density, drain current, transconductance orother device parameter. But, there is usually a time delaybetween stress and characterization and that delay timewas frequently not given in the published papers and itmay have varied widely. More recently, it was found thatthe time delay is very important, because the stress damagerecovers very rapidly. It may take many seconds to generateNBTI damage, but it recovers within a few seconds! Doesthe NBTI damage recover completely? That is not clearand the reported values depend on the authors. Ershovet al. propose that there are two degradation components:a permanent component which remains after stress removaland a reversible component that recovers [21]. Ranganet al., on the other hand, show complete recovery with thedevice being reset to its original state after the stress isremoved [22]. Huard et al. have done extensive measure-ments and find partial recovery [4]. They attribute NBTIdegradation to interface trap generation and hole trapping,Not and claim the recovery to be due to Not recovery withDit remaining largely unchanged during the recovery phase.Fig. 4 shows the threshold voltage and interface trap densitychange during stress and recovery periods. Both DVT andDNit change proportionally during stress, but only DVT

shows a significant drop during the recovery phase withDNit remaining almost constant. In contrast, Yang et al.show the threshold voltage recovery after stress cessationto be primarily due to interface trap passivation, not due

0

0.2

0.4

0.6

0.8

1

0 1000 2000 3000

Rel

ativ

e ΔN

it

Stress Time (s)

VG<0 VG>0T=125oC

ress time for negative and positive gate voltages [4].

-VG

H Si H Si

H-P__


to hole de-trapping [23]. This passivation effect is enhancedby positive gate bias during the recovery phase.

Why does the Not-controlled portion of VT recoveryoccur? If Not is due to trapped holes, then the holes canbe emitted during recovery. For +VG recovery bias, it ispossible that accumulation electrons near the Si surfaceare injected or tunnel into the oxide to neutralize thetrapped holes or that holes are ‘‘pushed’’ out of the traps.How do the hole traps originate? The trap generation ispossibly related to hydrogen released from the SiH bondsat the interface and more traps are generated in nitridedoxides than in SiO2. But what is the mechanism?

Tsujikawa et al. investigated NBTI recovery and foundthat VT recovered more than Dit with zero or positive gatevoltage during recovery [24]. They attributed Not to holetrapping induced by hydrogen and these positive chargesare neutralized by electrons in the accumulation layer whenthe MOSFET is biased to +VG. They correlated NBTI dam-age to stress-induced leakage current (SILC) and time-dependent dielectric breakdown (TDDB) through oxidetraps generated during NBTI stress. Ang, during NBTIrecovery measurements, found that while VT recovers forVG = 0 and VG > 0, Dit hardly recovers at all for VG > 0[25] in agreement with Huard et al., showing that Dit recov-ery is suppressed under +VG recovery bias. However, themechanism is not yet understood. If Dit hardly recovers,does that imply that hydrogen does not diffuse back to theSiO2/Si substrate interface during recovery?

NBTI recovery leads to less severe device/circuit degra-dation under ac operation compared to dc and depends onthe gate voltage duty cycle [21]. Most NBTI degradationmeasurements, however, are made with dc bias. The life-time enhancement can be significant. The accelerated life-time factor for ac operation is

F ¼ t2

t1

� �n

) t2 ¼ t1F 1=n ð7Þ
H Si n -Si
-VG

H Si Si Si

P

n -Si

HH2

H+

_

___

Fig. 6. Possible interface trap creation by hydrogen.

Eq. (7) predicts lifetime enhancements of t2/t1 = 16 forn = 0.25 and 76 for n = 0.16 for 50% ac NBTI degradation,pointing out the importance of an accurate knowledge ofthe n-factor. Since, as we show later, n depends on the time

0.01

0.1

1

10

100 101 102 103 104

-ΔV

T (

mV

)

Stress Time (s)

p-MOS NBTI

|VG |= 2.8 V

T=105oC

n-MOS NBTI

n-MOS PBTIp-MOS PBTI

Fig. 5. Threshold voltage shifts for p- and n-MOSF

lag between stress and recovery, it then also depends on thefrequency or duty cycle of the ac signal.

Question: What fraction of recovery is due to interfacetraps and oxide charge? Are oxide traps generated duringNBTI stress? How does Not recovery work?

6. Why are p-MOSFETs different from n-MOSFETs?

NBTI is observed in both p-MOSFETs and n-MOS-FETs. However, the effect is more extreme in p-MOSFETs.What is the reason for this? Fig. 5 shows the threshold volt-age shift from two different research groups when p- andn-MOSFETs are biased with positive and negative gatevoltages [17,4]. Clearly p-MOSFETs under negative gatebias are the most severely affected. It is commonly assumedthat holes are necessary for NBTI degradation and since n-MOSFETs biased into accumulation also have holes at thesurface, they should show similar VT degradation. But theydo not. We will put forward several explanations for this.

Tsetseris et al. propose the following NBTI model [26].Their first-principles calculations show that positivelycharged hydrogen or protons, H+, react directly with theSiH to form interface traps, according to the reaction

Si3 � SiHþHþ ! Si3 � Si � þH2 ð8Þ

where Si3 � SiH is a hydrogen-terminated interface trapand Si3 � Si• an interface trap with the dot representingthe dangling bond. As shown in Fig. 6, the hydrogen is as-sumed to originate from phosphorus-hydrogen bonds inthe n-Si substrate. The P–H bonds dissociate and thehydrogen on the way to the SiO2/Si interface ‘‘picks up’’a hole to become H+, then reacts with the H from theSiH bond to form H2 leaving behind a positively charged

0.01

0.1

1

10

100 101 102 103 104

-ΔV

T (

au)

Stress Time (s)

p-MOS NBTI

|VG |= V

T=125oC

n-MOS PBTI

n-MOS NBTI

p-MOS PBTI

ETs for positive and negative gate bias [17,4].


Si dangling bond (or trapping center). The H2 diffuses fromthe interface into the oxide or poly-Si gate. It can later pas-sivate a dangling bond by diffusing back to the interfacewhen the stress voltage is interrupted. The reason for thereduced NBTI activity in n-MOSFETs in this model is thatit is more difficult for boron-hydrogen bonds to be brokenin p-Si substrates. So the different behavior of p- versus n-MOSFETs in this model is due to the ease or difficulty ofbreaking P–H and B-H bonds in the Si substrate. Thresh-old voltage shifts in this case are due to interface traps,oxide charge, and a change in the substrate doping densityafter P–H or B-H depassivation.

Another explanation depends on the Nit and Not chargestates. Interface traps, being acceptors in the upper half ofthe band gap and donors in the lower half, affect VT shiftsin n- and p-MOSFETs differently. Fig. 7 shows the banddiagram of n-channel in (a) and p-channel devices in (b).At flatband, the n-channel has positive and the p-channelhas negative interface trap charge. At inversion, /s � j2/Fj,the n-channel has negative and the p-channel has positive

interface trap charge. Since the oxide charge is positivein both cases, we have at inversion: n-channel: Qox � Qit,p-channel: Qox + Qit, hence p-channel MOSFETs are moreseverely affected. This was clearly shown by Sinha andSmith where the threshold voltage of MOS capacitors on(111)n-Si decreases by 1.5 V while VT of (11 1)p-Sidecreases by only about 0.2 V [27].

Let us put this into quantitative terms. For DNox =1011 cm�2 and DDit = 1011 cm�2 eV�1, we have

DV T ðp-MOSFETÞ ¼ �4:6� 10�7ðDNox þ DDitEG=2Þtox

¼ �14:3 mV ð9aÞDV T ðn-MOSFETÞ ¼ �4:6� 10�7ðDNox � DDitEG=2Þtox

¼ �4:3 mV ð9bÞ

assuming that under strong inversion, the Fermi level at thesurface coincides with the valence band in p-MOSFETs

EV

EC

Ei

EF

"0"Acceptors

EV

EC

Ei

EF

Dit

Donors"0"

"+"

"0"

"-"

EV

EC

Ei

EF

"0"Acceptors

EV

EC

Ei

EF

Dit

Donors "0"

"-"

"0""+"

"0"

Fig. 7. Band diagrams of the Si substrate showing the occupancy ofinterface traps and the various charge polarities. (a) p-Substrate withpositive interface trap charge at flat band and negative interface trapcharge at inversion. (b) n-Substrate with negative interface trap charge atflat band and positive interface trap charge at inversion.

and with the conduction band in n-MOSFETs, givingDE � EG/2. So the different behavior of p- versus n-MOS-FETs in this model is due to the opposing sign of the inter-face traps.

Another reason for the n- versus p-channel behavior hasto do with the surface potential–gate voltage behavior, i.e.,the gate voltages on n- and p-channel devices are not thesame for a given oxide electric field [5]. Since this has notbeen treated in detail, I give the relevant equations. Con-sider the band diagrams in Fig. 8, drawn for uniformlydoped substrates without threshold voltage adjust implantsfor simplicity. I use the band diagrams to explain the effectand then use more exact equations for numerical values.The flatband voltages differ by about one band gap, assum-ing a p+ poly-Si gate with EF = EV for the p-channel andEF = EC for the n+ gate of the n-channel devices. ForNBTI, the p-channel device is biased into inversion andthe n-channel device into accumulation, causing the p+ gateto be depleted and the n+ gate to be accumulated. Clearly,the band diagrams for negative NBTI gate bias are notsymmetrical, although they are symmetrical at flatband.

With threshold voltage adjust implant, the gate voltageis given by

V G ¼ V FB þ /s;S þ /s;G þ V ox þ V i ð10Þ

where VFB is the flatband voltage, /s,S and /s,G the sub-strate and gate surface potentials, Vox = QS/Cox the oxidevoltage, and Vi = Qi/Cox (Qi = qNi) the threshold volt-age adjust implant voltage with Ni the implant dose.I will use: NA,D = 1017 cm�3, NG = 5 · 1019 cm�3, ni =1010 cm�3, tox = 2 nm, T = 300 K, and EG/q = 1.12 V.The flatband voltages for the p- and n-channel devices,assumed to be due only to work function differences, are

V FB;p ¼EG

2qþ /F;p ¼

EG

2qþ kT

qln

ND

ni

� �

¼ 0:56þ 0:42 ¼ 0:98 V ð11aÞV FB;n ¼ �

EG

2q� /F;n ¼ �

EG

2q� kT

qln

NA

ni

� �

¼ �0:56� 0:42 ¼ �0:98 V ð11bÞ

VG=VFB φs,S

Vox

φs,G

VG,p

φF,p VG=VFB

Vox

EC

EV

EF

VG,n

φF,n

Fig. 8. Band diagrams for (a) p-channel and (b) n-channel MOSFETs.The poly-Si gate Fermi level is taken to be EV,G in (a) and EC,G in (b). Thelight lines are for VG = VFB and the heavy lines for strong inversion/accumulation for the same Vox.

0

2x1021

4x1021

6x1021

8x1021

1 1022

0 0.5 1 1.5 2 2.5 3

Nit

roge

n (c

m-3

)

Depth (nm)

NO Annealed

Plasma Nitrided Oxide

0.01

0.1

1

10

100 101 102 103 104

ΔID

sat (

%)

Stress Time (s)

NO Annealed

Plasma Nitrided Oxide

tox=3 nm tox=6 nm

T=125oC

VG=-3.6 V

x

Fig. 9. (a) Nitrogen concentration versus depth and (b) drain current change versus stress time for nitrous oxide and plasma nitrided oxides showing thebeneficial effects of plasma nitridation [29].


where /F is the Fermi potential. Assuming for the substrateEV = EF at the surface for both devices for NBTI negativegate voltage bias gives

/s;Sp ðinversionÞ ¼ �0:98 V;

/s;Sn ðaccumulationÞ ¼ �0:14 V ð12Þ

To determine Vi, the two threshold voltages need to be con-sidered. VT is

V T ¼ V FB þ 2/F þ /s;G þ QS=Cox þ V i ð13Þ

Substituting numerical values with QS ¼ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi2qKse0NS2/F

p¼

�0:14 V, /F = ± 0.42 V, and using

V T;p ¼ �0:4 V; V T;n ¼ 0:4 V gives

V T;p ¼ �0:4 ¼ 0:98� 0:84� 0:14þ V i)V i¼ �0:4 V ð14aÞV T;n ¼ 0:4 ¼ �0:98þ 0:84þ 0:14þ V i ) V i ¼ 0:4 V ð14bÞ

assuming the gate surface potential is around zero atthreshold.

For strong inversion

V G;p ¼ V FB þ /s;Sinv þ /s;G þ V ox þ V i

� 0:98� 0:94� 0:56þ V ox � 0:4

¼ V ox � 0:92 V ð15aÞ

assuming /s,Sinv � � (2/F + 0.1) = � 0.94 V and for thedepleted gate /s,G � � EG/2q = � 0.56 V. Similarly forn-channel in accumulation

V G;n ¼ V FB þ /s;Sacc þ /s;G þ V ox þ V i

� �0:98� 0:14þ V ox þ 0:4 ¼ V ox � 0:72 V ð15bÞ

assuming /s,Sacc � � 0.14 V and /s,G � 0. Eqs. (15) showthat for a given oxide voltage or given oxide electric fieldthe gate voltages on the p- and the n-channel devices differby 0.2 V in this fairly realistic example, i.e., the voltage dif-ference for the same oxide electric field does not differ bythe band gap, as sometimes inferred. Hence, measurementson p- and n-channel devices should take into account theseconsiderations for equivalent oxide electric field.

Question: Is the p-channel/n-channel NBTI differencedue to interface trap charge dependence on surface poten-

tial, hydrogen diffusing from the substrate or work func-tion difference?

7. Nitrogen and fluorine

Nitrogen, water and hydrogen in the oxide degradeNBTI. Nitrogen is especially important as it is incorpo-rated into many oxides today and its role in NBTI degra-dation is poorly understood. It has been suggested thatnitrogen creates hole traps [28]. Plasma nitridation leadsto reduced NBTI degradation compared to nitrous oxideillustrated in Fig. 9 [29]. During plasma nitridation thenitrogen diffuses from the top into the oxide with the nitro-gen concentration skewed more heavily toward the gate/oxide part of the oxide. Excess nitrogen near the oxide/sub-strate interface leads not only to enhanced NBTI degrada-tion but also to higher fixed oxide charge density [30].Nitrogen should be located near the gate/oxide interfacerather than the oxide/substrate interface for minimumNBTI degradation. Fluorine, on the other hand generallyhelps. Fluorine atoms release the distortion at the SiO2/Siinterface. Interface-state generation for fluorinated oxidesunder Fowler–Nordheim stress is suppressed and onemight suspect that this also applies to NBTI [31]. NBTIhas also been observed in high-K dielectrics.

8. Activation energy and time dependence

NBTI depends on temperature, oxide electric field, andtime and the threshold voltage shift can be expressed by

DV T ¼ A expðceoxÞ expð�EA=kT Þtn ð16Þ

where A is a constant, c the electric field factor, EA the acti-vation energy and n the time exponent. It is obviouslyimportant to determine the various parameters in this equa-tion to predict NBTI degradation for any time, temperatureand oxide electric field. The degradation mechanism of holetrapping and hydrogen diffusion from the SiO2/Si interfaceinto the oxide is usually described by an activation energyand a time dependence, shown in Eq. (16). Neutral H2

diffusion is described with EA � 0.2–0.3 eV and the time


exponent n � 0.25. Frequently, however, very different val-ues are measured for these parameters and various explana-tions have been forwarded. Recent measurements ofnitrided oxides gave 0.019 eV 6 EA 6 0.24 eV and 0.095 6n 6 0.158 over the 183–513 K temperature range, in contrastto EA � 0.27 eV and n � 0.27 for pure SiO2 [32]. A morecommonly-accepted value for dry SiO2 is 0.1–0.15 eV. Thevalue of 0.27 eV is likely due to partial wet oxide. Ang andWang attribute the non-Arrhenius behavior to the superpo-sition of two defect generation mechanisms with differing n

and EA: hole trapping with n � 0.1 and EA � 0.02 eV andhydrogen diffusion with n � 0.25 and EA � 0.25 eV [32].At low temperatures the VT shift is determined by hole trap-ping at nitrogen defect precursors. At the higher tempera-tures, classical hydrogen diffusion takes over. They suggestthat previously published reports of temperature-dependentn values in thin SiO2 [33] may be due to trace amounts ofnitrogen in those oxides. This mechanism may account forthe VT recovery being due to ‘‘oxide charges’’ and not inter-face traps, observed by Huard et al. [4]. Why is NBTI oxideelectric field dependent? This implies either a charged oxidespecies or the field aids the electrochemical reaction.

The threshold voltage degradation has also been mod-eled by the concept of disorder by [34].

DV Tj j ¼ DV T max 1� exp � ts

� �b� �

ð17Þ

where

s ¼ N i

kT bD0eox exp �DE

kT

� �� 1=b

;

DH ¼ D0t�a ¼ D0t�ð1�bÞ ð18Þ

where Ni is the interstitial site density at the SiO2/Si inter-face, b the dispersion coefficient, DH the dispersive hydro-gen diffusion coefficient, a the dispersion coefficient, eox theoxide electric field, and DE the hydrogen dissociation en-ergy. For short times, jDVTj � DVTmax(t/s)b.

Huard et al. find n to increase with temperature and EA

to vary with stress time [4]. They explain this behavior withthe SiH dispersed dissociation energy having various EA.Each SiH bond follows its own Arrhenius behavior, but

1010

1011

1012

102 103 104

ΔNit (

cm-2

)

tox=7 nm

No delayn=0.19

1 s delayn=0.3

Stress Time (s)

Fig. 10. (a) DNit36 and (b) DVT

37 versus stress tim

the multitude of bonds exhibits a non-Arrhenius behavior.Kaczer et al. use a disorder-controlled kinetics model inwhich the disorder due to energy distribution of deep local-ized hydrogen states in the SiO2 leads to a wide distributionof hydrogen hopping times [35]. This predicts a tempera-ture-dependent n factor. Nitrogen introduces deeper hydro-gen states leading to lower n. The n exponent appears todepend on the measurement conditions. When there is adelay between NBTI stress and its characterization,n � 0.25. However, when the delay is zero, n decreases to�0.15.

Krishnan et al. show the n exponent for interface trapgeneration to be 0.16 under the assumption that neutralH2 diffuses from the SiO2/Si interface into the oxide anddiffusion, not interfacial reaction, is the rate-limiting pro-cess [36]. Their data are shown in Fig. 10(a). They positthat the n = 0.25 value frequently quoted, is due to the timedelay between stress and measurement. In their measure-ments, they obtain n = 0.3 with 1 s delay between stressand Nit measurement. Varghese et al. show n = 0.14 for‘‘no delay’’ measurements and n > 0.14 when there is adelay between stress and measurement, shown inFig. 10(b) [37].

NBTI shows a tendency to saturate for long stresstimes, as shown in Fig. 4. This has been attributed to var-ious causes. A recent paper by Alam and Kufluoglu listsfour possible causes [38]. One suggests that a change ofhydrogen diffusion from H to H2 diffusion changes n from0.25 to 0.16 leading to quasi-saturation of the DVT vs. tcharacteristics. Another cause may be H2 pile up at thegate/oxide interface if hydrogen diffuses slower in thepoly-Si gate than in the oxide, leading to hydrogen backdiffusion and subsequent Dit passivation. On the otherhand, if hydrogen diffuses faster in the poly-Si gate, thenhydrogen ‘‘disappears’’ from the oxide and saturationoccurs when all SiH bonds are broken. The dispersion ofthe bond-breaking dissociation energies leads to low EA

bonds breaking first making it progressively more difficultfor stronger bonds to dissociate. Finally, saturation maybe a measurement artifact. Delays between stress andNBTI damage measurement lead to repassivation of inter-face traps. In the model in which NBTI is due to hydrogen

6789

10

20

30

40

100 101 102 103

ΔVT (

mV

)

Stress Time (s)

T=50oCVG=-3 V No delay

n =0.138

50 ms delayn =0.189

e with and without stress/measurement delay.


diffusion from the substrate, is it possible for the P–Hbonds to deplete thereby leading to saturation?

Question: What is the true time dependence? Is itn � 0.16? What is the activation energy? Is the disorder-controlled diffusion mechanism correct? Which mecha-nism(s) is (are) responsible for the quasi-saturation?

9. Wafer orientation

Most ICs are fabricated on (100) oriented Si wafers.However, it has been known since 1968 that hole mobilityis higher for p-MOSFETs on (110) oriented wafers withthe channel in the h1 10i direction [39,40]. Along with thehigher hole mobility, however, is a higher interface trapdensity. Dit has been reported as Dit(100) = 7.7 · 1010

and Dit(110) = 1.4 · 1011 cm�2 eV�1 [41]. Hence onewould expect more severe NBTI degradation on (110) ori-ented wafers, as indeed has been observed, as shown inFig. 11 [42,43]. This is a potential problem if (110) orientedwafers become important. For certain three-dimensionaldevices, e.g., FinFETs, when fabricated on (100) waferswith the channel in the conventional h1 10i direction, thevertical sidewalls are (110) oriented, leading to NBTIproblems [42]. However, forming FinFETs on (100) waferswith the channel in the h100i direction, leads to (100) ver-tical sidewalls, illustrated in Fig. 12. Three-dimensionalstructures lead to various difficulties, e.g., gate length crit-ical dimension control and the nature of three-dimensional

1

10

100

100 101 102 103 104 105 106

ΔVT (

mV

)

Stress Time (s)

T=125oC

ox =-7.6 MV/cm

(110)

(100)

ε

Fig. 11. DVT versus stress time for SiON (2%) with (110) and (100)orientation. Points: experiment, lines: Eq. (17) with s = 1.3 · 104 s, b =0.3, DVTmax(110) = 91 mV and DVTmax(100) = 53 mV [43].

Fig. 12. Top view of (100) oriented Si wafer with FinFET-like

structures. It is possible, however, to form planar (100)and (110) oriented surfaces on one wafer using SOI layertransfer technology [44].

10. Measurements

Traditionally NBTI has been characterized by stressinga device, then interrupting the stress to measure a deviceparameter, e.g., VT, ID, leff, Dit, Not, stress again, measure,etc. VT, ID, and leff are determined from ID–VD and ID–VG

measurements. The interface trap density Dit is usuallymeasured with charge pumping [45] or log(ID)–VG sub-threshold swing measurements. Usually source, drain andsubstrate are grounded during the stress period. The‘‘dead’’ time between ‘‘stress’’ and ‘‘measure’’ varied fromresearcher to researcher and was frequently not given inpublications. When it was discovered that that time wasquite important, techniques were developed to minimizeand eliminate the ‘‘dead’’ time. Rangan et al. useVD = 50 mV and monitor the drain current during stressand recovery [22]. Drain current depends on effectivemobility and threshold voltage and in this method neitheris measured explicitly, but the drain current degradationis determined.

Huard et al. in their ‘‘on the fly’’ method, apply a lowdrain voltage pulse of �50 mV and record the drain currentat the end of the stress period, without interrupting thestress, illustrated in Fig. 13(a) [4]. This was repeated andin this way drain current degradation was recorded withno ‘‘dead’’ time. Since the current depends on thresholdvoltage, mobility and other device parameters, it is not

transistors with channels in the h110i and h100i directions.

VGVGstress

VD

Stress Time

VDmeas

VGVGstress

VD

Stress Time

VDmeas

ΔVG

Fig. 13. Measurement schematics for (a) drain current and (b) draincurrent and transconductance without interrupting stress.


possible to extract DVT. In a modification of this method,shown in Fig. 13(b), small gate voltage pulses are superim-posed on the dc gate stress voltage. The drain current isalso pulsed and the drain current is measured at three dif-ferent gate voltages, allowing the transconductance to bedetermined.

In yet another method, the ID–VG characteristic of anunstressed device is measured. Then the gate voltage is low-ered briefly from its stress value to a voltage near VT andthe drain current is measured [35]. The gate voltage shiftof the stressed drain current is converted to DVT.

From the linear drain current a number of parameterscan be derived. The linear drain currents IDlin for p-MOS-FETs in the mobility-dominated and velocity saturation-limited regimes are [46]

IDlin � kleffðV GS � V TÞV DS;

IDlin �kleff

1þ leffV DS=vsatLðV GS � V TÞV DS; ð19Þ

leff ¼l0

1þ hðV GS � V TÞ; k ¼ WCox

L

where l0 is the low-field mobility, h the mobility degrada-tion factor, and vsat the saturation velocity. All voltagesare negative for p-channel MOSFETs and given as abso-lute values in Eq. (19). If the change in drain current iscompared to the unstressed, IDlin0, the change in IDlin is [47]

DIDlin

IDlin0

¼ � DV T

V GS � V T0

) DV T ¼ �ðV GS � V T0ÞDIDlin

IDlin0

ð20Þ

where VT0 is the unstressed threshold voltage and anychange in mobility in deriving Eq. (19) is neglected. This,of course, is an approximation since we know that interfacetraps generated during NBTI stress degrade the mobility byintroducing scattering centers. However, the mobilitydependence on gate voltage decreases at higher gatevoltages.

The mobility dependence can be eliminated by measur-ing the transconductance in Fig. 13(b) according to

gm �kl0V DS

1þ hðV GS � V TÞ½ 2;

gm �kl0V DSð1þ l0V DS=vsatLÞ

1þ hðV GS � V TÞ þ l0V DS=vsatL½ 2ð21Þ

and

IDlinffiffiffiffiffiffigm

p ¼ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffikl0V DS

pðV GS � V TÞ;

IDlinffiffiffiffiffiffigm

p ¼ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffikl0V DS

pðV GS � V TÞffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi

1þ l0V DS=vsatLp ð22Þ

Eq. (19) neglects the source/drain parasitic resistance.Including it adds another term, but does not alter Eq.(22) [48]. The mobility degradation factor h has been elim-inated in Eq. (22), but it still contains the low field mobility.

The determination of l0 is discussed in detail by Huardet al. [4].

Question: How much time can be allowed between stressand measurement? Must it be zero?

11. Effect on circuits

The drain or on current is important in analog and dig-ital circuits. In digital circuits, with MOSFETs beingswitches, charging and discharging capacitors, higher draincurrent leads to faster capacitor charging and higher fre-quency operation. The delay time is

td ¼CjV DDj

ID

¼ 2LC

W leff CoxðV DD � V TÞ2ð23Þ

where C is the capacitance and VDD the supply voltage.NBTI stress leads to leff reduction and VT increase, bothgiving delay time increases – clearly undesirable. In analogcircuits the drain current is also important. An interestingeffect that occurs due to NBTI degradation is an increasedgate-to-drain overlap capacitance increase due to generatedinterface traps. Such increased CGD degrades analog cir-cuits due to the Miller effect. For digital circuits VT andCGD degradation contribute about equally to circuit degra-dation while for analog circuits, CGD is the major circuitdegrader, e.g., frequency response of operational amp-lifiers.

The fractional change of drain current due to thresholdvoltage change is

ID �W leffCox

LðV G � V TÞV D )

1

ID

dID

dV T

¼ � DV T

V G � V T

ð24Þ

for MOSFETs in the linear region, and

IDsat �W leff Cox

2LðV G � V TÞ2 )

1

ID

dID

dV T

¼ � 2DV T

V G � V T

ð25Þ

for the saturation region, showing twice the degradation insaturation, as observed experimentally [47]. With scaling,device dimensions and voltages shrink. However, the gatevoltage typically shrinks more than VT, hence the head-room (VG–VT) is smaller for shorter channel devices result-ing in more degradation. For example, with VG = � 1.5 V,VT = � 0.4 V and DVT = � 0.05 V, the fractional draincurrent degradation from Eqs. (24) and (25) becomes4.5% and 9%, respectively. The fractional change due tomobility change is

1

ID

dID

dleff

¼ Dleff

leff

ð26Þ

The mobility degrades due to interface trap generation,since leff depends inversely on Dit.

The one parameter that appears to be positively influ-enced by NBTI is the off current, i.e., the drain currentfor VG = 0. The off current for p-MOSFETs is given by


Ioff ¼ IT expqV T

nkT

� �; n ¼ 1þCb þCit

Cox

¼ 1þKffiffiffiffiffiffiffiN D

pþ qDit

Cox

ð27Þ

where to first order IT and K are constants. As VT becomesmore negative, Ioff decreases. However, Dit increases result-ing in higher n and reduced slope of the log(ID)–VG char-acteristics. This leads to a slight Ioff increase, but the VT

change generally dominates. The n-factor also becomes lessimportant as the oxide capacitance increases for thinneroxides.

For SRAM cells the static noise margin (SNM), which isa measure of the read stability of the 6-T SRAM cell, isdegraded. A simple solution to recover the SNM uses adata flipping technique [49]. Knowing the threshold voltagedegradation of a single transistor due to NBTI, one canpredict the performance degradation of a digital circuitwith a reasonable degree of accuracy.

Digital circuits are less sensitive (approximately 9.2%performance degradation in ten years for 70 nm technol-ogy) to NBTI degradation than previously anticipated [50].

Question: How severe a problem is NBTI for digital andanalog circuits? Which circuits are most severely affected?How much threshold voltage shift can a circuit tolerate?

12. Conclusions

A brief review of NBTI is followed by a summary ofrecent publications elucidating various NBTI mechanisms.I have tried to highlight those aspects of NBTI that are stillnot fully understood – at least not by me. I have used themost relevant equations to bring out particular points. Atthe end of most sections I have posed some questions thatI believe are still unanswered. Although NBTI is much bet-ter understood today than a few years ago, the very mech-anism causing NBTI is not completely understood. Forexample, I do not believe that we really know what causesthe positive oxide charge, although there is little doubtabout what causes interface trap changes. There is a fairamount of discrepancy on the time dependence of NBTIdegradation; is it n = 0.15 or 0.25? While that may appearmarginally important, it becomes very important in pre-dicting long-term NBTI degradation. The reported activa-tion energy also covers a wide range. What exactly doesnitrogen in nitrided oxides do? It appears that the amountand location of nitrogen are important. The further thenitrogen is from the oxide/substrate interface, the less isthe NBTI degradation. Most NBTI measurements aremade at elevated temperatures and some high-performanceICs operate at or near those temperatures. However, manyICs operate at lower temperature. Is the degradation mech-anism the same at various temperatures? This, of course, isalways a problem when devices are stressed during reliabil-ity measurements. The stress (electromigration, gate oxideintegrity, hot carriers) is usually carried out at higher cur-rent, voltage, temperature and the degradation is extrapo-lated to normal operating conditions to very long times,

e.g., 10 years. This relies on the degradation mechanismsduring stress and operation being the same. Several impor-tant NBTI degradation questions remain unanswered.However, I am confident that the world-wide attention ithas garnered will lead to a better understanding. Also, verylittle has been published on NBTI reduction/elimination,perhaps because much of this is proprietary information.

Acknowledgements

I thank the reviewers for constructive and thoughtfulcomments and suggestions, many of which were incorpo-rated into the paper.

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