UART IP VERIFICATION

ByNaveen CBatch-43

ContentsWhat is UART? IntroductionKey Feature of UARTUVM TB Architecture Test Cases verifiedWaveforms

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Introduction

The Universal Asynchronous Receiver Transmitter or simple UART is one of the common peripheral found on microcontrollers (MCU) widely used for communication with the external devices and systems.

Modules, ASIC's , and PC's are among the devices that the microcontroller can communicate to through the UART.

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UART

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Features•WISHBONE interface in 8-bit data bus mode or 32-bit data bus mode.

•FIFO mode is supported.

•An on-chip bit rate (baud rate) generator to control transmit and receive data rate.

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Divisor Latch Byte

Calculating Divisor Latch Byte:

Divisor latch Byte= (input clock speed) / (16 x baud rate)

Two different input clock frequency taken are 50MHz and 25MHz

Baud rate = 1,00,000

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Operationo Upon a write to the data input bus

WB_DAT_I, the core will automatically serialize and emit the byte on the Trx_PAD_O.

o According to the interrupt we have enabled the int_o goes high whenever an interrupt is available.

o Upon reception of a bit stream on Srx_PAD_O, the core will unserialise the information and check for error and it will send the received data to receiver FIFO.

o This announce that the received byte can be read on the data output bus WB_DAT_O. As soon as the fifo trigger level reached and its get enabled the Int_o will get high and can be read at the output port.

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Data framing…

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UVM Architecture

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Modes of OperationThree main modes of operation Half Duplex mode Full Duplex Mode Loop Back Mode

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Half Duplex Mode

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Full Duplex Mode

Transmission is bidirectional.

UART 1 Transmits and UART 2 Receives.meanwhile UART 2 Transmits and UART 1receives.

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Loop Back Mode

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TEST CASESHalf Duplex ModeFull Duplex ModeDual Loop Back ModeParity Error Break interruptOverrun conditionFraming ErrorTimeout IndicationTransmitter holding register emptySetting LCR to Transmitting 5 bits dataSetting LCR to Transmitting 6 bits dataSetting LCR to Transmitting 7 bits data

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Half Duplex Mode INPUT

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Half Duplex Mode OUTPUT

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Full Duplex Mode INPUT

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Full Duplex Mode OUTPUT

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Loop Back Mode INPUT

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Loop Back Mode OUTPUT

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Parity Error INPUT

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Parity Error OUTPUT

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Break interrupt INPUT

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Break Interrupt OUTPUT

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Overrun Error INPUT

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Overrun Error OUTPUT

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Framing Error INPUT

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Framing Error OUTPUT

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Timeout Indication INPUT

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Timeout Indication OUTPUT

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Transmitter Holding Register Empty INPUT

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Transmitter Holding Register Empty OUTPUT

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THANK YOU

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