Navakanta Bhat - Semantic ScholarVLSI-Very Large Scale Integration, ULSI-Ultra Large ScaleIntegration,GSI-GigaScaleIntegration,etc.,are used to describe this. Today, we are able to

Associate Professor,Department of ElectricalCommunicationEngineering, IndianInstitute of Science,[email protected]

Keywords: nanoelectronics,non-classical CMOS, SOI,transport enhanced FETs,Multi-gate transistor, high-kgate dielectric, short channeleffect, gate tunneling,non-CMOS memory andlogic, MEMS, NEMS, SoC,variability, low power.

Moore’s law: Moore’s law isan empirical observation andextrapolation made byGorden Moore in 1965 – thecomponent density on anintegrated circuit doublesevery year. Although therehas been an exponentialgrowth in the componentdensity in the last fourdecades, as predicted byMoore’s law, the growth ratehas decreased with thecomponent density doublingevery two to three years.

REVIEWS

Nanoelectronics Era :NovelDeviceTechnologies Enabling Systems on Chips

Navakanta Bhat

Abstract | The issues in scaling the Complementary Metal Oxide Semiconductor (CMOS)

transistors in sub-100 nm regime are reviewed. The non-classical CMOS device technologies

such as high-k gate dielectrics, strained silicon channel, Silicon On Insulator, multi-gate

transistors, and metal gate electrodes, are discussed in detail. These techniques are expected to

scale the CMOS devices to an ultimate limit of 5 nm physical gate length. The system level

issues of growing power dissipation and increasing device to device variability in the chips

should be overcome for the successful realization of complex systems in nanoelectronics

technologies. A brief overview of the non-CMOS memory and logic device architecture is

provided. The opportunities in building hybrid systems on chips by combining sensors and

actuators along with the compute and storage functions on a single chip are described.

1. IntroductionThe growth in electronics industry since theinvention of the first Integrated Circuit (IC) chipin 1958 [1], is probably unparalleled by any otherindustry sector. The cumulative aggregate growthrate (CAGR) is about 15% in the last 5 decades [2].This has been possible due to the exponentialincrease in the component density integrated on asingle chip, as predicted by Moore’s law [3,4]. Animplicit assumption in the Moore’s law is that wecan shrink the feature size of the transistor – thebasic building block of an IC – at an exponentialrate. The compound annual reduction rate ofthe transistor dimension is more than 10%, overthe last 5 decades. In 1999, the transistor gatelength crossed the 100nm barrier, leading to thevolume production of the nanoelectronics chips.Today, nanoelectronics has been the most successfulcommercial manifestation of the nanotechnology,with the 65 nm CMOS technology in volumeproduction.

The history of silicon technology developmentunderscores several innovations that enabled

continuous progress, overcoming supposedlyinsurmountable barriers. Some of these innovationsinclude dual poly-silicon gates with n+ gatesfor n-channel (NMOS) and p+ gates for p-channel (PMOS) transistors, channel engineeringwith super steep retrograde and pocket haloimplants, source/drain engineering through shallowextensions, shallow trench isolation to shrinkthe active device pitch, silicidation to over comeparasitic resistance, sub-wavelength optical phaseshift lithography to pattern sub-100 nm featuresusing 248 nm/193 nm deep UV source [5–7]. Butto a large extent, the silicon technology has reliedon the traditional scaling of classical CMOS devicearchitecture. However in the nanoelectronics era,the technology scaling has become nontrivial dueto fundamental limits imposed by device physicsand materials technology. Whether and how we cango along the Moore’s law curve will be dictated bythe innovations in novel materials and our abilityto architect the systems using non-classical devicearchitectures. It is expected that non-classical CMOStransistors are essential in the short term and non

Journal of the Indian Institute of Science VOL 87:1 Jan–Mar 2007 journal.library.iisc.ernet.in 61

REVIEW Navakanta Bhat

Figure 1: Hierarchical view of building an electronics Integrated Circuit (IC)chip.

Process Technology

Device Physics

Circuit Design

System Architecture

Application Domain

TechnologyDomain

CAD and Modeling

CMOS transistors coupled with new informationprocessing architectures will be required in thelong term. We discuss some of the potential devicestructures in Section 2.

The success of electronics relies on twoimportant aspects. On the one hand the buildingblocks of the chips, the transistors, have continued toshrink in their size. On the other hand the numberof transistors reliably put together on a chip hasgrown exponentially. Several nomenclatures such asVLSI-Very Large Scale Integration, ULSI-Ultra LargeScale Integration, GSI-Giga Scale Integration, etc., areused to describe this. Today, we are able to integratemore than one billion transistors of sub-100nmsize with very high yield on a silicon chip of 1cm2

area. It is this capability of giga-scale integrationusing nano-scale building blocks that is very uniqueabout the electronics systems. Figure 1 shows thedifferent aspects involved in realizing the chip. It isimportant to recognize that the expertise requiredcuts across different domains, which are broadlydivided into application and technology domains.The scaling of the device in nano regime requires avery good understanding of the physics of the deviceto engineer a high performance transistor. Theprocess technology which can fabricate the devicerequires the expertise in material science, processchemistry and physics. The circuit design and systemarchitecture requires the expertise in electronicsdesign, computer science, communication andvarious other application domains. This complexitycan be managed only through the Computer AidedDesign (CAD) tools which require the expertisein computational science and programming. The

growth of nanoelectronics in the next two decadesis hinged on innovations in all these hierarchicalviews of enabling an IC chip. This requires a highlyinterdisciplinary effort. In section 3 we brieflydiscuss on some of the issues in the applicationdomain.

In the last few years, there has been anotherinteresting development of building Systems onChips (SoC), combining non-electronic energydomain components along with electronicssubsystems of compute and storage elementson a single chip. The motivation for thisphenomenon is illustrated in Fig. 2. The Siliconprocess technology lends itself to define non-electronics structures, such as micro/nano machinedsensors and actuators. These are also referred toas Micro Electro Mechanical Systems (MEMS)and Nano Electro Mechanical Systems (NEMS).However, the SoCs include not only electronics andmechanical components but also optical, chemicaland biological building blocks on the same chip.The nanoelectronics era is well poised for a greaterconfluence of multiple energy domain componentson single chip, leading to penetration of such SoCsinto newer application domains. We will discusssome of these developments and possibilities inSection 4.

2. Device TechnologyFigure 3 shows a typical cross-section of classicalNMOS transistor. The PMOS transistor is acomplement of this structure with N type substratedoping and p+ source and drain regions. TheCMOS technology utilizes both NMOS and PMOStransistors to build the circuits and systems. BothNMOS and PMOS transistors are created on bulkSilicon substrate with SiO2 gate insulator andpoly-crystalline silicon gate electrode. The MOStransistor is essentially a gate controlled switch,with the vertical electrical field controlling thechannel conductivity (field effect transistor – FET).The gate length, Lg , of the transistor determinesthe switching speed of the transistor. The typicaltransistor dimensions on a 65 nm CMOS technologyare illustrated in Fig. 3. The typical gate lengthis actually less than 65 nm, however the gatepitch (combination of gate length and the distancebetween neighboring gates) is of the order of 130nm (2×65), and hence the label “65 nm CMOStechnology”.

One of the important implications of scalingthe MOS transistor in the sub-micron regime isthe significant manifestation of the 2-dimensionalnature of the MOS transistor. The conductivity ofthe MOS transistor channel, below the SiO2 gateinsulator, should be ideally controlled by the vertical

62 Journal of the Indian Institute of Science VOL 87:1 Jan–Mar 2007 journal.library.iisc.ernet.in

Fermi level: The Fermi level isthe top of the collection ofelectron energy levels at zerodegree kelvin. In asemiconductor, the positionof the Fermi level in theenergy band-gap is governedby the relative concentrationof electrons and holes.

Nanoelectronics Era : Novel Device Technologies Enabling Systems on Chips REVIEW

Figure 2: Traditional and Equivalent scaling paths in the NanoelectronicsEra.

Technology Drivers: Memory and LogicMaterials : Silicon and its derivatives

such as SiO2, Si3N4 etc.Device Architecture: Classical CMOS

1960 2000 2020

Technology Drivers: Hybrid Systems On Chip (SOC)Materials : Silicon coexisting with Polymer, Piezo,

Ferroelectric, Magnetic, Shape memory alloysDevice Architecture: CMOS coexisting with MEMS,

chemical sensors, biological sensors etc.

Equivalent Scaling Path (growing function integration)

Traditional Scaling Path (shrinking feature size)Technology Drivers: Memory and LogicMaterials : Silicon coexisting with variety of materials to enable new devices Device Architecture: Non Classical CMOS(short term) and Non CMOS (long term)

Pe r

f or m

a nce

Silicon CMOS

Novel Materials andDevice structures

Technology Drivers: Memory and LogicMaterials : Silicon and its derivatives

such as SiO2, Si3N4 etc.Device Architecture: Classical CMOS

Technology Drivers: Hybrid Systems On Chip (SOC)Materials : Silicon coexisting with Polymer, Piezo,

Ferroelectric, Magnetic, Shape memory alloysDevice Architecture: CMOS coexisting with MEMS,

chemical sensors, biological sensors etc.

Equivalent Scaling Path (growing function integration)

Traditional Scaling Path (shrinking feature size)Technology Drivers: Memory and LogicMaterials : Silicon coexisting with variety of materials to enable new devices Device Architecture: Non Classical CMOS(short term) and Non CMOS (long term)

Pe r

f or m

a nce

Silicon CMOS

Novel Materials andDevice structures

electrical field set-up by the gate to source voltage(Vgs), and not by the lateral electric field set-up bythe drain to source voltage (Vds). In other words,Vds should only influence the drift velocity of thecarriers in the channel. However, with decreasingLg , drain and source electrodes come into closeproximity. Hence, the drain electric field startsinfluencing the height of the barrier at the source forthe injection of free carriers into the channel. As aresult, the drain electric field starts competing withthe gate electrode to gain control over the channelconductivity. The transistor will no longer be anideal gate controlled device. This phenomenon isreferred to as Short Channel Effect (SCE). Theimmediate consequence of SCE is lowering ofthe threshold voltage (Vt ) of the transistor withdecreasing Lg as shown in Fig. 4. The short channeltransistor needs to be designed properly so thatVt roll-off is controlled to yield the required valueat the minimum Lg for a given technology. In aclassical CMOS, this has been typically achieved by acombination of decrease in SiO2 gate insulatorthickness to increase the vertical electric fieldcoupling to the channel, increase in substratedoping concentration to decrease the penetration ofdrain electric field towards source, and decrease insource/drain junction depths to reduce the couplingvolume. However, these techniques will not besufficient to scale the device in the nanoelectrronicsera. Several non-classical approaches are required inthe immediate future to extend the scalability ofCMOS architecture. Table 1 summarizes the overallprojections of nanoelectronics device technologyand the corresponding chip performance for thehigh end microprocessor.

2.1. Non classical CMOS2.1.1. High-k gate dielectrics

Figure 5(a) shows the SiO2 gate oxide thicknessscaling trend in CMOS technology. For the 65 nmtechnology node, the SiO2 thickness is about 1nmwhich is essentially two mono-layers of SiO2film.Figure 5(b) shows the energy band diagram ofthe NMOS structure in the vertical direction for apositive applied bias. (This discussion holds goodfor the negative gate bias as well, except that thegate Fermi level, Ef, will be above the substrateand the electrons will be tunneling from the gateelectrode). Typically, the conduction across theSiO2 insulator layer is negligible due to very largeband offset (∼3.1eV) between the conductionband of gate/substrate and the conduction bandof the oxide. However, for an ultra-thin gateoxide with Tox < 5 nm, carriers can quantummechanically tunnel through the oxide and resultin large gate leakage current. Furthermore, thetunneling probability increases exponentially withdecrease in Tox . Figure 6 shows the gate leakagecurrent density for different gate oxide thickness.The gate leakage current density of 100 A/cm2

indicates that, the transistor with 50 nm gate lengthresults in a gate leakage of 50 nA per unit micronwidth (50 nA/µm). This is more than 20% ofthe total off state leakage current budget of thetransistor. Hence it is not possible to scale Tox anyfurther. This calls for replacement of SiO2 with analternate gate insulator which has higher dielectricconstant (k). The high-k dielectric of thicknessof Tk is equivalent to effective oxide thickness ofEOT = 3.9/

k ×Tk , where SiO2 dielectric constantis 3.9. Hence, it is possible to use thicker insulatorand reduce the gate tunneling current (Fig. 7),while maintaining capacitive coupling of the gateelectric field to the channel that is equivalent tothinner oxide. Table 2 lists the properties of somepotential gate insulators that are being explored.In addition to high-k, the insulator should alsohave other important properties such as very goodinterface with Si resulting in minimal interfacetraps, thermodynamic stability, large band gap andband offset with Silicon. Among the various high-kdielectrics, HfO2 and some of the rare earth metaloxides are very promising at this time [10–14]. Thehigh-k gate dielectrics are expected to be introducedin the 45 nm CMOS technology node.

2.1.2. Transport enhanced FETThe increase in substrate doping concentration

to suppress short channel effects has adverselyaffected the carrier mobility in the MOSFETchannel. Fig. 8 shows the electron mobility in thechannel of NMOS transistor for different technology



Table 1: Projected technology nodes from International Technology Roadmap for Semiconductors. The technology nodes are scaled by a factor of 0.7,corresponding to doubling of device density (except the year 2020). Note that the transistor size in any given technology node is significantly smallerthan the node nomenclature.

Year of Production 2007 2010 2013 2016 2019 2020

Technology Node (nm) 65 45 32 22 16 14

Transistor Gate Length in Microprocessors circuits (nm) 25 18 13 9 6 5

Wafer diameter used in fab (inch) 12 12 18 18 18 18

Number of masks required for fabrication of Microprocessor 33 35 37 37 39 39

Number of Transistors in Microprocessor (billion) 1.1 2.2 4.4 8.8 17.7 17.7

Number of interconnect wiring levels in the Microprocessor chip 15 16 17 17 18 18

Number pins for packaged Microprocessor chip 1088 1450 1930 2568 3418 3760

Operating voltage (V) 1.1 1.0 0.9 0.8 0.7 0.7

Microprocessor frequency (GHz) 9.3 15.1 23 39.7 62.4 73.1

Chip power dissipation (Watts) 189 198 198 198 198 198

nodes [15]. The significant decrease in mobility ofthe scaled device is due to the increased impurityscattering in the channel, which gets worse withincreased doping concentration. This necessitates anew class of non-classical CMOS transistors, namelythe transport enhanced FETs. The technique relieson material engineering to enhance the channelmobility of the carriers. This class of devices includesstrained-silicon MOSFETs and hetero epitaxiallygrown Germanium (Ge) or Gallium Arsenide(GaAs) channel MOSFETs on the silicon substrate.

The strained-silicon channel MOSFETs relyon a very well known phenomenon that thecarrier mobility in silicon can be enhanced byintroducing stress in the silicon lattice. The tensilestrain enhances the electron mobility and thecompressive strain enhances the hole mobility.Several techniques have been employed for thestrain engineering in MOSFET. Figure 9 illustratesthe strain engineering using Si-Ge. The inter-atomicdistance in Ge (2.45 nm) is more than that of Si(2.36 nm) and the technique exploits this differenceto create tensile or compressive strain. Si-Ge thinfilm is grown on a silicon substrate by grading theGe concentration from 0 to about 30%. This gradedlayer typically contains the defects and ensures thatthe defect-free films can be grown on top. ThenSi0.7Ge0.3 thin film is grown with an effective latticeconstant higher than that of silicon. The thin siliconchannel layer (about 10 nm) is epitaxially grown onSi0.7Ge0.3, thus leading to a strained silicon channel.A very important consideration in creating thisstructure is to ensure that the strained silicon film isdefect-free, so that very high channel mobility canbe obtained. A variation of this technique has beenused for PMOS transistor to create compressivestrain. The source/drain region is recessed into thesubstrate and the Si-Ge is selectively grown in the

source/drain regions. This induces a compressivestress in the channel due to the lateral confinementfrom the two directions of the channel, leading toenhanced hole mobility.

The other strain engineering technique relieson gate stack capping with appropriate materialto induce stress in the underlying channel region.For example, capping the gate stack with Si3N4

can induce tensile stress and enhance the electronmobility. The isolation oxide in shallow trenchregion has also been utilized to induce strain in thechannel region. One of the issues in utilizing thestrain engineered MOSFETs in building the chipsis to ensure that the NMOS and PMOS regionsin the chip get different processing steps to createthe respective channel regions. The strained siliconchannel MOSFETs have been successfully integratedwith channel mobility improvement of more than30% [16,17]. The strained silicon MOSFETs aregoing through continuous improvement, and thistechnique will help scale the CMOS technologyfor the next 5 years or so. However, more radicaltechniques of transport enhancement will berequired beyond that. Some of the potentialcandidates include Ge and GaAs MOSFETs onthin films grown hetero-epitaxially on the siliconsubstrate. The electron mobility in Ge is morethan twice that of silicon and the hole mobilityis about four times that of silicon. Similarly theelectron mobility in GaAs is about six times that ofSilicon. Historically, Ge and GaAs have never beenamenable for building MOSFETs. While Si has anexcellent insulator in terms of SiO2, which resultsin an ideal interface with minimal trap density, Geand GaAs did not have this advantage. But nowthat SiO2 is being replaced with alternate high-kgate dielectrics, similar technique can potentially beemployed for Ge and GaAs as well. There are recent


propagation delay: The timerequired for a change indigital logic state at the inputnode of a logic gate toappear as the correspondingchange in logic state at theoutput node.

dynamic power: The powerdissipated in switching theoutput digital logic state of alogic gate.


Table 2: Comparison of potential high-k dielectrics with SiO2

Material Dielectric constant (k or εr ) Bandgap (eV) Conduction band offset (eV)

SiO2 3.9 9 3.15

Si3N4 7.9 5.3 2.4

Al2O3 10 8.8 2.8

HfO2 16–30 4.5–6 1.5

ZrO2 12–16 5.8 1.5

TiO2 80–170 3.05 0

ReO2* 12–30 2.5–5.5 1–3

*ReO2 : Rare earth metal oxides

reports with high quality Germanium devices builtusing high-k gate dielectrics [18]. These techniqueswill potentially lead to “enhanced silicon CMOS”technologies, while continuing to exploit the siliconinfrastructure.

2.1.3. Silicon On Insulator (SOI)The SOI technology utilizes a very thin silicon

film, on top of an insulator (typically SiO2),to build devices. The difference between theconstruction of bulk Silicon devices and theSOI devices is schematically shown in Fig. 10.The insertion of SiO2 underneath the activeSilicon devices offers some unique advantages. InCMOS circuits, the propagation delay (τ = CV/

I)

and the dynamic power (Pd = CV 2f ) are directlyproportional the load capacitance (C) which ischarged and discharged to change the logic states.The load capacitance consists of three components:the gate capacitance of the driven gate (Cg ),the source/drain capacitance of the driving gate(Cds), and the interconnect capacitance (Ci) ofthe line connecting these two nodes. In the SOItechnology Cds is almost equal to zero, since thesource/drain regions are placed directly on top of the

thick insulator. In addition, Ci is also significantlylower, since the device density in SOI is typicallyhigher than the bulk technology. This is becausethe isolation between the transistors in the SOItechnology is excellent because the transistors are inan island surrounded by an insulator. Hence thelatch-up issue is non existent in SOI, thus enablingvery close placement of neighbouring transistors,leading to shorter interconnect lengths between anytwo nodes in a circuit. The SOI technology typicallyoffers a performance improvement equivalent to onegeneration of bulk technology (i.e. nth generationof SOI is equivalent to (n + 1)th generation ofbulk) [19,20]. There are two variants of SOIdevice technologies: Partially Depleted SOI (PDSOI)and Fully Depleted SOI (FDSOI). In PDSOI, thethickness of the silicon film is typically 100 nmor more so that only part of the entire siliconbody is depleted when the transistor is turnedon. In contrast, the silicon film thickness forFDSOI is typically 50 nm or less so that theentire silicon body is depleted when the transistoris turned on. Each of these devices have theirown advantages and disadvantages. The PDSOIdevices are relatively easy to fabricate. However,they have a very unique problem of floating bodyinduced threshold voltage (Vt ) instability i.e. the Vt

becomes a strong function of the charge stored in thefloating body. This requires very challenging circuitdesign techniques because the circuit behaviourwill have history dependence. On the other handFDSOI devices have challenging fabrication processrequirements due to thin Silicon body. Howeverthey do not suffer from Vt instability. In additionFDSOI devices offer a very good platform for moreexotic non-classical CMOS transistors, namely themulti-gate MOSFETs.

Figure 3: The cross section of NMOS transistor and typical dimensions in 65 nm CMOS technology.

P type Si substrate

SiO2

~1017/cm3Substrate doping

~1020/cm3Source/Drain doping

Source/Drain depth: extension and deep region

1 nm SiO2 thickness

100 nm Poly-Si gate thickness

50 nm Poly-Si gate length, Lg

Lg

n+ PolyGate

n+Source

n+Drain

40 nm and 100 nm



2.1.4. Multi Gate FETsThe conventional technique of increasing the

substrate doping concentration to suppress the shortchannel effect cannot be continued indefinitely.This is because the leakage at the drain/source tosubstrate junction due to tunneling will adverselyaffect the transistor’s performance. An efficienttechnique to restore the gate control of the channel,without increasing the substrate doping, is essential.The scaling of MOSFETs has also been accompaniedby the scaling of the operating voltages (Vdd). Thisis essential to ensure that the electric fields in theMOSFET are acceptable and the long term reliability

Figure 4: Vt of NMOS decreases in the shortchannel regime.

of the devices and circuits is not compromised. Thescaling of the supply voltage also necessitates thescaling of the Vt , since the speed of the CMOScircuit depends on the drive current available fromthe transistor which is proportional to (Vdd −Vt ).This has resulted in an exponential increase inoff state current of the transistor over the last fewtechnology generations. This is because the sub-threshold conduction in a MOSFET is essentiallygoverned by the sub-threshold slope (S) which isa non-scalable quantity [21], as shown in Fig. 11.For any given Vt the drive current can also beenhanced by preventing the mobility degradation.Hence, it is desirable to create a transistor withvirtually intrinsic channel doping, while ensuringthe adequate gate control of the channel. Theserequirements are the motivation for creating muti-gate FETs which include double-gate FET, tri-gateFET, Fin-FET and surround-gate FET [22–24].By providing additional gates, the voltage on thegate can effectively couple to the channel therebyenhancing the FET performance. Figure 12 showsthe typical structure of FinFET, wherein the gatewraps around the channel region. Fin-FETs withvery good characteristics have been experimentallydemonstrated. However, the manufacturable processintegration has a long way to go. All these multi-gatedevices require an ultra-thin silicon channel regionwhich can be efficiently controlled.

Figure 5: (a) Gate oxide thickness trend as a function of technology scaling; (b) Energy band diagram forNMOS with positive gate voltage.

100 Lg (nm)

Tox (nm)

50

1.5

1.0

Tox

Gate SiliconOxide

TUNNELING Ec

Ef

EvEf

(a) (b)


Chalcogenides: Thecompounds consisting ofchalcogen element – groupVI element in the periodictable – can be switchedbetween a high resistanceamorphous phase and a lowresistance crystalline phase. Avery common chalcogenideused in phase changememory is Telurium (Te)compound – GeSbTe.


Figure 6: Gate leakage current due to direct tunneling [8].

104

102

100

10-2

10-4

10-60 0.5 1 1.5 2 2.5 3

Gate voltage (V)

Gat

e cu

rren

t den

sity

(A

/sq.

cm

)

Tox = 1.4 nm = 1.5 nm = 1.8 nm

Symbols – Data

Solid line – Model

2.1.5. Metal Gate ElectrodeThe early MOSFET technology was based on

metal gate electrodes. However, the metal gatewas replaced with highly doped poly-Si electrode,since the self aligned transistor was possible bydoping the gate and source/drain during the singleimplantation step. The current CMOS technology isa dual gate technology with n+ poly-Si and p+ poly-Si gate electrodes for NMOS and PMOS respectively.However, the resistivity of the poly-Si will limitthe performance in the sub-65 nm technology andhence the need for the metal gate electrode. Howeverthe choice of the material for metal gate electrode isnot trivial because the work function of the gateplays an important role in deciding the Vt of thetransistor. The NMOS and PMOS transistors may

Figure 7: Gate leakage current for high-k dielectrics [9].

1E 2

1E 0

1E-2

1E-4

1E-6

1E-8

1E-100 1 2 3

Gat

e le

akag

e (A

/cm

2 )

Physically effective oxide thickness (nm)

need different gate work functions, complicatingthe integration of the gate metal in the CMOStechnology [25]. The work function engineeringof the gate electrode will play an important rolein deciding the Vt of the transistor and hence thechoice of the appropriate material.

The combination of all these techniques maybecome essential to enable scaling of the CMOSdevice technology to an ultimate limit of about 5nm physical gate length by the year 2020. Howeverseveral innovations are required in semiconductorprocess technology to enable such devices. Thedetailed discussion of the process technologyrequirements is beyond the scope of this article.One of the key process technology requirementsis the scalability of the photolithography processbeyond 65 nm technology node. In the immediatefuture, 193 nm UV with immersion techniquemay be sufficient. However, alternative lithographytechniques such as Extreme UV lithography, maskless lithography, imprint lithography, electron beamlithography may be necessary to reach the ultimateCMOS scaling limit.

2.2. Non CMOS architecturesThe non-CMOS architectures will be requiredto continue the performance enhancement ofnanoelectronics systems beyond the ultimatelyscaled CMOS. Some of these device structureswill also require completely different informationprocessing paradigms. Any electronics systemfundamentally does two tasks: computation andstorage. The computational element is referredto as “Logic” block and the storage element isreferred to as “Memory” block. A particular systemarchitecture combines these blocks to yield therequired functionality. For example, the currentCMOS technology is utilized to build systems basedon digital – boolean architectures, operating on thebinary variable.

2.2.1. Non-CMOS Memory architecturesThe conventional CMOS memories are charge-

based, and hence they become very vulnerable tonoise with scaling because the charge stored on thememory cell is decreasing with every technologygeneration. The alternate memory structures exploitdifferent principles for storing the information.

Phase Change Memory (PCM) cell consists of amaterial (such as chalcogenides) whose phase canbe changed reversibly between a high resistancestate and low resistance state [26]. FerroelectricRAM (FeRAM) exploits the effect of remnantpolarization on a ferroelectric gate dielectric such aslead zirconate titanate (PZT) [27]. MagnetoresistiveRAM (MRAM) utilizes the magnetic tunnel junction


Cellular Nonlinear Networks(CNN): Cellular neuralnetworks (CNN) are systemsbased on a parallelcomputing architecture withan array of weak computeelements, wherein thecommunication is allowedonly between theneighbouring compute units.


Figure 8: Electron mobility in NMOS for different technology nodes [15].

500

450

400

350

300

250

200

150

100

50

0-0.2 -0.1 0 0.1 0.2

Mob

ility

(cm

2 /V-s

)

Towards Source Towards DrainDistance along the channel (µm)

L=0.5µm

0.25µm

0.35µm

0.18µm

0.09µm0.12µm

to modulate the resistance of memory cell [28].Polymer memory relies on a memory cell withorganic-metal-organic film stack, whose resistancecan be programmed into high and low valuesto store information [29]. Molecular memory isa very broad class of memory cell, which storesinformation on a single molecule connecting twoelectrodes, by modulating the conductivity of themolecule [30]. It is expected that some of thesealternate memory structures, especially the firstthree options, may be integrated along with theCMOS logic some time in the next decade.

2.2.2. Non-CMOS Logic architecturesThis class of devices attempts to realize the

fundamental element of a Logic block, the transistor,

Figure 9: Strained silicon NMOSFET structure with tensile strain in thechannel.

Strained Si

Relaxed Si0.7Ge0.3

Relaxed Graded Si1-xGex

x = 0 to 0.3

Silicon substrate

10 nm

n+ n+

in a completely radical fashion. In some cases suchdevices are not amenable to integrate into theconventional digital architectures and a completelynovel system architecture paradigm will be required.

Nano-wire and nano-tube based 1-D transistorstructures are potential candidates. The notableamong them is the Carbon Nano Tube (CNT)transistor [31]. In order to integrate it with theconventional architecture, the issue of selectivelydefining the CNT based NMOS and PMOStransistors in giga-scale by growing the CNTs atprecise locations on the chip should be resolved.The Resonant Tunneling Transistor (RTT) isanother alternative with a negative differentialresistance and very high switching speed [32].Single Electron Transistors (SET) are structurallysimilar to the conventional MOSFET except thatthe source to substrate and drain to substratejunctions are tunnel junctions and the channelis ideally formed by a quantum dot [33]. A SETcan be potentially used to represent a binary bitby a single electron, but alternate architecturessuch as Cellular Nonlinear Networks (CNN) willbe required to realize such systems. Another classof transistors exploits the spin of the electrons,leading to a field that is popularly referred to as“Spintronics”. There are several concepts proposedto build such devices. The spin MOSFET is a hybriddevice which relies on gate control (electro staticchannel control) and drain control (spin dependentscattering at the drain). However, this requires theefficient injection of spin polarized electrons into thechannel, necessitating half-metallic-ferromagneticcontacts at the source and drain [34]. There areother concepts such as spin-torque transistor [35]and spin-gain transistor [36]. However, all theseconcepts are still far from surpassing the capabilityof the ultimately scaled CMOS.

The “Optoelectronics” or “Photonics” proposesto build digital computers by using photons forinformation processing and transmission at thespeed of the light [37]. However, the componentsize will be limited by the diffraction phenomenon.Furthermore, the compatibility with the existingcomputer architecture is unclear. On the other hand,the integration of optical interconnects for chip levelwiring in the CMOS technology is considered to bemore promising. “Organic electronics” or “plasticelectronics” builds the transistors on organic thinfilm substrate such as pentacene [38]. These devicesare extremely slow due to low channel mobility,and hence they do not compete with the ultimateCMOS in building the conventional computearchitectures. However, these devices are expected tocomplement the CMOS technology and extendthe electronics applications into new domains


Qubit: A unit of quantuminformation wherein the bitcan take a superposition of 0and 1 states due to quantumentaglement.


Figure 10: Schematic comparison of bulk MOSFET and SOI MOSFET.

Si wafer

Insulator

Si wafer

Bulk Silicon technology SOI technology Si film(100nm)

500µm

such as flexible displays, wearable electronics,electronic paper, and low cost sensors. The organicelectronics devices will utilize the conventionalprinting technology (printable electronics) andprovide very low cost solutions. The Nano-Electro-Mechanical-Systems (NEMS) open up the possibilityof nanomechanical computer where the digitalbit is represented in mechanical domain, bydisplacement of cantilevers [39]. However, thespeed of signal propagation is limited by thevelocity of the sound. Quantum electronics andquantum computing exploit the phase informationin the quantum mechanical wave function forinformation processing [40]. Unlike the binarystate bit in the conventional computers, the qubitin quantum computing can hold the state of 1 or0 or superposition of these at the same time. Theunderlying devices fall into the class of devices whichare based on particles with 2 spin states. Due toinherent massive parallelism, such computers willbe ultra-fast in applications such as cryptography.Several issues are yet to be overcome for such devicesto become practical. Also, it is not clear whether all

Figure 11: Subthreshold conduction in MOSFET.

log (Ids)

VgsVt

The inverse slope of this lineis ‘sub threshold slope’, S , in mV/decade

Vt1 <

classes of problems addressed by CMOS computingarchitecture are amenable for quantum computingarchitecture.

The molecular transistor, or the possibility ofcreating a switching device on a single molecule, hasraised the expectations for the fascinating fieldof “Molecular electronics” [41]. These devicescan potentially result in very high density withthe device size of the order of 1nm. However,some of the major issues include assemblingthese devices on giga-scale and interconnectingthem appropriately to yield complex systems. Infact, a completely different system architecturemay be required to utilize these devices. Anotherimportant issue relates to the fabrication of thesedevices. These devices will likely be fabricatedusing chemical synthesis, i.e. atoms-up approach,rather than the conventional top-down approachusing photolithography. This could be a disruptivetechnology that can enhance the nanoelectronicssystem performance very significantly beyond theultimately scaled CMOS.

It is expected that none of the non-CMOSarchitectures can really replace the ultimately scaledCMOS. Instead, CMOS architectures will co-existwith a variety of other device technologies andenable the nanoelecronics system performanceenhancement beyond 2020.

3. Circuits and Systems DesignThe two important issues in realizing the giga-scaleintegrated circuits is the exponential increase inthe power dissipation and the device variability. Itis absolutely essential to manage these issues for asuccessful scaling of the CMOS technology to reachthe ultimate limit by 2020. Although some of thenovel device technologies are attempting to addressthese issues to some extent, novel design techniquesat the circuits and systems level are considered to bevery important.

3.1. Power dissipationAs indicated in Table 1, the high performancechips are already consuming more than 150 W ofpower. The high power dissipation also impacts theperformance and reliability of the chip and requiresvery elaborate heat extraction techniques from thechip. Figure 13 shows the power dissipation trendsin Intel microprocessors [5]. The biggest concern isa dramatic increase in the standby power of the chip.This is especially troublesome in battery operateddevices. This increase is attributed to the exponentialrise in the sub-threshold leakage in nano transistors.

The circuit techniques utilizing the multi-Vt

transistors are useful in this context [42]. This isbased on the notion that the performance of a



Figure 12: 3-Dimensional FinFET structure. The current flows from source(S) to drain (D) in lateral direction, through the channel wrapped aroundby the gate fin (G).

Figure 13: Power dissipation trends with technology scaling [5].

102

101

100

10-1

10-2

10-3

10-4

10-5

10-6

Pow

er (

W)

1.0 0.8 0.6Technology Generation (µm)

.35 .25 .18

Active Power

386486DXCPU

Pentium IIProcessor

R

Standby Power(Transistor T=110C)

Figure 14: Impact of device variability on circuit performance.

PROCESS

C IRCU IT

Tox

Tsp

Na

Xj

Oxidation

Deposition

Implantation

Diffusion

Speed

Dynamic power

Static power

Yield

Id

CL

Vt

ΔVt

complex circuit with several million transistorsis dictated by a few critical paths in the circuit.The number of transistors that occupy the criticalpaths is a very small fraction of the total numberof transistors on the chip. It is sufficient to ensureonly these transistors have a low-Vt . The rest of thetransistors can have high-Vt and thereby reducethe static leakage power. The other techniquesinclude the use of sleep transistor for powergating the unused circuit blocks on the chip [43],Additionally, the system level innovations suchas low power architectures exploiting parallelismfor performance enhancements [44], softwaretechniques to implement low power algorithmsto implement energy efficient algorithm for a giventask are beneficial to move forward [45].

3.2. Device variabilityThe device-to-device variability and its impact onthe circuit design methodology has been regardedas a potential show-stopper for the scaling of CMOStechnology. This refers to the statistical differencesbetween pairs of identically designed and processedtransistors. This arises due to statistical natureof underlying processes used to fabricate MOStransistor as shown in Fig. 14. The variation inthe process parameters results in the variationin the structural parameters of the device suchas junction depth (Xj), oxide thickness (Tox),doping concentration (Na). This in turn leads tovariation in the electrical parameters of the device,eventually resulting in circuit parameter fluctuations.This results in a stringent trade-off betweenprecision/speed versus yield for analog/digital VLSIapplication. Typically any given device parameter,such as Vt , has a normal distribution around itsexpected target value. The standard deviation, σ,of this distribution describes the extent of thevariability. Figure 15 shows the variability trend withscaling. While the signal levels are going down withscaling, the noise due to variability is increasing withscaling [46]. This is because the intrinsic factorsinfluencing the variability such as random dopantnumber fluctuation in nano transistors, get worsewith scaling. Thus, it is becoming extremely difficultto create the nano transistors that are identical toeach other.

The conventional technique of over-designingfor the worst case becomes very pessimistic. Onthe one hand, it has become very essential toaccurately predict and model the variability andon the other hand it is essential to developrobust design techniques at the circuit and systemlevels. Recently statistical modeling techniqueshave been proposed to relate the circuit anddevice variability to the underlying semiconductor



Figure 15: Variability is increasing with technology scaling [46].

VDD

Signal amplitude

Technology1μm 0.1μm

6σVt

σVt

processes [47–49]. The circuit design techniquessuch as adaptive body biasing to tune the transistorparameter, and post fabrication corrections for nonidealities are becoming essential [50–52]. The systemarchitecture level techniques are also essential tohandle variability in the long term. The adaptiveneural network based architectures are attractive inthis context [53,54]. The defect tolerant and bio-inspired architectures are capable of correcting theerrors due to variability and realize very robust highperformance systems [55,56].

Figure 16: Hybrid Systems on Chip enabled by the functional integrationof non CMOS components

Switch

INERTIAL MEMS

OPTICAL MEMS

ACOUSTIC MEMS

RF MEMS

BIO MEMS

POLYMER ELECTRONICS

INTEGRATED ENERGY SOURCES

Ultra sound sensor Microphone

Varactor Resonator Switch Phase-shifter Antenna array

Accelerometer Pressure sensor

Grating

LED Photovoltaic diode Polymer IC

Thin film fuel cell Energy harvesting Super capacitor

Bio sensor Micro probes DNA chips PCR Cell-culture

Functional integration : More than Moore…

Gyroscope

Cross connects

CHEMICAL / GAS SENSORS

Micro heater Trace elements Hazardous gases

Micromirror

4. Hybrid Systems on a ChipTraditionally, the electronics system performancehas been enhanced in the context of Moore’s law byincreasing the computing performance and storagecapacity of the chips. However, for the past few years,it is becoming increasingly important to exploitthe silicon technology infrastructure into otherapplication domains. Specifically, the functionalintegration of nonelectronic domain componentsonto the chip is being driven by, what is popularlyknown as, the More than Moore philosophy. Thesechips are also referred to as Hybrid Systems on Chipsbecause there is on chip interaction of multipleenergy domains.

Figure 16 illustrates the different possibilitiesin terms of functional integration. In a majorityof these cases the same set of semiconductorprocesses that are traditionally used to buildtransistors, are utilized to create micro/nanomachined (MEMS/NEMS) structures on silicon.These structures can act as sensors and actuatorsand interface with the on chip electronics. Siliconhas excellent mechanical properties, which enablesthe creation of robust mechanical building blockssuch as beams, membranes, rigid masses, etc [57].The success of such hybrid SOCs can be illustratedthrough some of these chips that have penetratedthe consumer applications. Most of the airbagrelease systems deployed in automobiles employa MEMS accelerometer chip [58]. It consists ofa suspended poly-silicon proof mass created ontop of Silicon substrate through surface micro-machining technique. The mass is configured asone of the plates of the capacitor, and hence thecapacitance changes in response to acceleration. Themovement of the proof mass is measured throughcapacitance sensing using the electronics interfacecircuit on the chip. This integration results in highreliability, low cost and high performance solutionwhich can be deployed in a variety of applications.Another great success story has been the DigitalMicromirror Display (DMD) device in the opticalMEMS domain [59] which is routinely used toreplace the LCD projectors. In this case, the pixelarray of suspended micromirrors is created on topof electronics chip which provides the informationto be displayed. Each of the micromirror is electro-statically actuated to control the reflection of thelight to produce the appropriate grey level for thepixel. Similar opportunities exist in various otherdomains as illustrated in Fig. 16. These systems arealso expected to be autonomous through harvestingthe energy from the environment. Eventually theconvergence of electronics and biology for lab-on-a-chip applications in diagnostics and therapy maybe the biggest technological revolution in the 21stcentury.



5. ConclusionsThe Silicon CMOS technology will continue tobe scaled to an ultimate limit of about 5 nmphysical gate length of a transistor, albeit requiringseveral innovations in process technology, materialsengineering, and exploitation of new device physics.The nanoelecronics system performance is expectedto scale according to the predictions of Moore’s lawalong this path. However, the circuit and systemlevel issues of power management and variabilitytolerance should be addressed through noveltechniques. After the end of the CMOS roadmap,beyond 2020, radically new device technologieswill be required for further enhancement of systemperformance. The performance enhancement ofthe SOCs will also evolve along a new trajectoryof functional integration to include non electricaldomain components. The sensors and actuatorsintegrated along with the conventional computeand storage functions will open up new applicationdomains.

A. Centre of Excellence in NanoelectronicsThe Ministry of Communication and InformationTechnology (MCIT), Government of India, hasinitiated an ambitious project to set-up two Centresof Excellence in Nanoelectronics at the IndianInstitute of Science, Bangalore and the IndianInstitute of Technology, Bombay. This project hasan outlay of Rs. 100 crores over 5 years (2006–2010)to create comprehensive nanofabrication facilities(nanofabs) at these two institutes. These nanofabswill act as nodal centres in the country to facilitatethe state-of-the-art experimental research. Thenanofab infrastructure will enable the fundamentalexploration in several areas of nano science andengineering and it is also expected to seed newtechnologies that will have societal and commercialimpact.

At IISc, a large number of faculty members fromvarious disciplines of science and engineering areinvolved in this project. The institute has taken a leadto foster this interdisciplinary effort by initiating thecreation of a new building to support the nanofabinfrastructure. The nanofab is expected to be fullyfunctional by 2008. When completed, it would beon-par with some of the best university nanofabselsewhere. The facility will also be available forother researchers in the country through the IndianNanoelectronics Users Program (INUP).

Received 07 December 2006; revised 31 January 2007.

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Navakanta Bhat Navakanta Bhat receivedhis B.E. in Electronics and Communicationfrom University of Mysore in 1989, M.Tech.in Microelectronics from I.I.T. Bombay in1992 and Ph.D. in Electrical Engineering fromStanford University, Stanford, CA in 1996.Then he worked at Motorola’s Networking andComputing Systems Group in Austin, TX until

1999. At Motorola he worked on logic technology developmentand he was responsible for developing high performance transistordesign and dual gate oxide technology. He joined the IndianInstitute of Science, Bangalore in 1999 where he is currently anAssociate Professor in the Electrical Communication Engineeringdepartment. His current research is focused Nano-CMOStechnology and Integrated CMOS-MEMS sensors. The workspans the domains of process technology, device design, circuitdesign and modeling. He has several research publications ininternational journals and conferences and 3 US patents to hiscredit. He has received the Young Engineer Award (2003) from theIndian National Academy of Engineering. He is also the recipientof the Swarnajayanti fellowship (2005) from the Department of


http://qist.lanl.gov/

http://www.analog.com/index.html

http://www.analog.com/index.html

http://www.dlp.com/dlp_technology/images/dynamic/white_papers/153_Reliability_paper.pdf

http://www.dlp.com/dlp_technology/images/dynamic/white_papers/153_Reliability_paper.pdf


Science and Technolgy, Govt. of India and Prof. Satish Dhavanaward (2005) from the Govt. of Karnataka. He was the foundingchair of the IEEE Electron Devices and Solid-State Circuits society,Bangalore chapter which was recognized as the OutstandingChapter of the Year by the IEEE SSC society (2003) and IEEE EDS

society (2005). He has been on the program committees of severalinternational conferences. He was the technical program chairfor the international conference on VLSI design and Embeddedsystems (2007). He is a Distinguished Lecturer of the IEEE ElectronDevices Society.


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