NAT64 SERVERNetwork Address Translation using vertex-5

D.P.G.S.R FernandoI.U. LiyanageJ.R. KodagodaR.S.A De Silva

Overview

Why Vertex-5

We had three choices for FPGA boards: Virtex-5,Vertex-2 & Altera

Embedded tri-mode Ethernet MAC wrapper is available only for Virtex-5 and Vertex-6

Because of which we used Virtex-5 board for our project.

ProcedureImplemented the Tri-mode Ethernet MAC Wrapper

Implemented the IPv4 to IPv6 conversion algorithm

Implemented the IPv6 to IPv4 conversion algorithm

Combine two algorithms to get the NAT64 module

Tri Mode Ethernet MAC wrapper

IPv4 to IPv6 Conversion

IPv6 to IPv4 Conversion

Header Mapping

IPv4 IPv6

Ether Type: 0x0800 Ether Type:0x86dd

DSCP, ECN Traffic class

Header Length, Total Length

Payload Length

Protocol Next Header

Time to Live Hop Limit

Ipv4 address Ipv6 address

Static NAT Table  IPv4 IPv61 200.2.2.2 2000:2000:2000:2000:2000:2000:

2000:20002 200.3.3.3 3000:3000:3000:3000:3000:3000:

3000:30003 200.4.4.4 4000:4000:4000:4000:4000:4000:

4000:40004 200.5.5.5 5000:5000:5000:5000:5000:5000:

5000:5000Default Source Address

200.6.6.6 6000:6000:6000:6000:6000:6000:6000:6000

Broadcast Address 200.255.255.255 ff02::1Multicast(to all host)

224.0.0.1 ff02::1

Multicast (to all routers)

224.0.0.2 ff02::2

unspecified 0.0.0.0 ::Loopback address 127.0.0.1 ::1

Hardware Debug Tools ChipScope Pro AnalyzerWe use ChipScope Pro Inserter flow, to capture signals in ChipScope Pro

Wireshark packet sniffer software application

Issues Virtex-5 board only has one Ethernet port

though out NAT64 server needs at least two ports.

Virtex-5 device designs of Tri-mode Ethernet MAC require a Verilog LRM-IEEE 1364-2005 encryption-compliant simulator ModelSim v6.6d Cadence Incisive Enterprise Simulator (IES) 10.2 Synopsys VCS and VCS MX 2010.06)

But any of those simulators are not freely available