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Nanoscale III-V Electronics: from Quantum-Well Planar MOSFETs
to Vertical Nanowire MOSFETs
J. A. del AlamoMicrosystems Technology Laboratories, MIT
Purdue University,West Lafayette, IN; September 29, 2015
Acknowledgements:• D. Antoniadis, J. Lin, W. Lu, A. Vardi, X. Zhao• Sponsors: DTRA, Lam Research, Northrop Grumman, NSF, Samsung• Labs at MIT: MTL, EBL
Contents
1. Motivation: Moore’s Law and MOSFET scaling2. Planar InGaAs MOSFETs 3. InGaAs FinFETs4. Vertical nanowire InGaAs MOSFETs 5. Conclusions
2
1. Moore’s Law at 50: the end in sight?
3
Moore’s Law
Moore’s Law = exponential increase in transistor density
4
Intel microprocessors
What if Moore’s Law had stopped in 1990?
5
Cell phone circa 1990GPS handheld device circa 1990
6
What if Moore’s Law had stopped in 1980?
Laptop computer circa 1981
7
What if Moore’s Law had stopped in 1970?
TV set, circa 1970
8
What if Moore’s Law had never happened?
Insulin pump circa 1960 “Personal calculator” circa 1960
1960
Moore’s Law
9
?
How far can Si support Moore’s Law?
Transistor scaling Voltage scaling Performance suffers
Transistor current density (planar MOSFETs):
Transistor performance saturated in recent years10
Moore’s Law: it’s all about MOSFET scaling
Enhanced gate control improved scalability
1. New device structures:
11
Moore’s Law: it’s all about MOSFET scaling
2. New materials:Si Strained Si SiGe InGaAs
Si Strained Si SiGe Ge InGaSb
Future CMOS might involve twodifferent channel materials with two different relaxed lattice constants!
del Alamo, Nature 2011 (updated)12
Measurements of electron injection velocity in HEMTs:
• vinj(InGaAs) increases with InAs fraction in channel• vinj(InGaAs) > 2vinj(Si) at less than half VDD
• ~100% ballistic transport at Lg~30 nm
Electron velocity: InGaAs vs. Si
13
del Alamo, Nature 2011
III-V electronics in your pocket!
14
del Alamo’s group at MIT: Current and future activities
N-type InGaAs MOSFETs:
P-type InGaSb MOSFETs:future
Jianqiang Lin Xin ZhaoAlon Vardi
Wenjie Lu
New students:Xiaowei CaiDongsung Choi
15
2. Self-aligned Planar InGaAs MOSFETs
Lin, IEDM 2012, 2013, 2014
WMo
Lee, EDL 2014; Huang, IEDM 2014
selective MOCVD
Sun, IEDM 2013, 2014 Chang, IEDM 2013
reacted NiInAs
dry-etched recess
implanted Si + selective epi
16
Self-aligned Planar InGaAs MOSFETs @ MIT
Lin, IEDM 2012, 2013, 2014
Recess-gate process:• CMOS-compatible• Refractory ohmic contacts (W/Mo)• Extensive use of RIE
WMo
Jerome Lin17
Fabrication process
• Ohmic contact first, gate last • Precise control of vertical (~1 nm), lateral (~5 nm) dimensions • MOS interface exposed late in process
W/Mon+ InGaAs/InPInGaAs/InAsInAlAs
SiO2
InPδ-Si
Resist
MoPad
HfO2
Mo/W ohmic contact + SiO2 hardmask
SF6, CF4 anisotropic RIE CF4:O2 isotropic RIE
Cl2:N2 anisotropic RIE Digital etch
Waldron, IEDM 2007
Finished device
Lin, EDL 2014
O2 plasma H2SO4
18
Lin, IEDM 2013
Ti/Au pad
Spacer: OxideGate: Mo
Contact: Mo
Lg = 20 nm, Laccess= 15 nm MOSFET most compact III-V MOSFET made at the time
Lg=20 nm InGaAs MOSFET
n+ cap
Channel
Mo
W
Mo/HfO2
20 nm
Buffer
SiO2
InAs 0.0 0.1 0.2 0.3 0.4 0.50.00.20.40.60.81.0 Lg=20 nm
Ron=224 Ω.µm 0.4 V
I d (m
A/µm
)Vds (V)
Vgs-Vt= 0.5 V
20 nm
15 nm
19
• Channel: In0.7Ga0.3As/InAs/In0.7Ga0.3As • Gate oxide: HfO2 (2.5 nm, EOT~ 0.5 nm)
Highest performance InGaAs MOSFET
• Record gm,max = 3.1 mS/µm at Vds= 0.5 V• Ron = 190 Ω.µm
-0.4 -0.2 0.0 0.20.00.51.01.52.02.53.03.5
gm,max= 3.1 mS/µm
Lg = 80 nmVds= 0.5 V
g m (m
S/µ m
)Vgs (V)
0.0 0.1 0.2 0.3 0.4 0.50.00.20.40.60.81.01.21.4
I d (m
A/µm
)
Vds (V)
Vgs = -0.3 to 0.4 V in 0.1 V stepLg = 80 nmRon=190 Ω.µm
Lg =80 nm, tc=9 nm
Lin, IEDM 201420
Excess OFF-state current
OFF-state current enhanced with Vds
Band-to-Band Tunneling (BTBT) or Gate-Induced Drain Leakage (GIDL) Lin, IEDM 2013
-0.6 -0.4 -0.2 0.010-11
10-9
10-7
10-5 Lg=500 nm
Vds=0.3~0.7 Vstep=50 mV
I d(A/µ
m)
Vgs (V)
Transistor fails to turn off:
Vds ↑
21
-0.4 -0.2 0.0 0.210-11
10-9
10-7
10-5 W/ BTBT+BJT W/O BTBT
Vds=0.3~0.7 Vstep=50 mV
I d (A/
µm)
Vgs (V)
Excess OFF-state current
Lg↓ OFF-state current ↑ additional bipolar gain effect due to floating body
Lin, EDL 2014
-0.6 -0.4 -0.2 0.010-11
10-9
10-7
10-5 Lg=500 nm
Vds=0.3~0.7 Vstep=50 mV
I d(A/µ
m)
Vgs (V)-0.6 -0.4 -0.2 0.0
10-8
10-7
10-6
10-5
10-4
500 nm280 nm
120 nm
T=200 KVds=0.7 V
I d (A/
µm)
Vgs-Vt (V)
Lg=80 nm
Vds ↑
Simulationsw/ BTBT+BJTw/o BTBT+BJT
Lg=500 nmLin, TED 2015
22
Impact of channel thickness scaling
• tc ↓ S ↓ but also gm,max ↓• Even at tc=3 nm, Lg,min~40 nm
planar MOSFET at limit of scaling
Lin, IEDM 2014Lin, TED 2015
0.01 0.1 1 100
1
2
3
g m,m
ax (m
S/µm
)Lg(µm)
4 nm
tc=9 nm
11 nm
12 nm7 nm
3 nm
8 nmVds=0.5 V
0.01 0.1 1 100
100
200
300
400
S min (m
V/de
c)
Lg(µm)
Vds=0.5 Vtc ↓
3 nm
Vds=0.5 V
tc=12 nm
23
Benchmarking: gm in MOSFETs vs. HEMTs
del Alamo, ESSDERC 2013 (updated)
MIT MOSFETs
Latest: 3.7 mS/µm!
– Very rapid recent progress in MOSFET gm
– Best MOSFETs now surpass best HEMTs– No sign of stalling more progress ahead!
gm of InGaAs MOSFETs vs. HEMTs (any VDD, any Lg):
24
3. InGaAs FinFETs and Trigate MOSFETs
Kim, IEDM 2013
60 nm
dry-etched fins
SiWaldron, VLSI Tech 2014
Epi-grown fin inside trench
25
InGaAs FinFETs @ MIT
Key enabling technologies: • BCl3/SiCl4/Ar RIE • digital etch
Zhao, EDL 2014; Vardi, DRC 2014
Alon Vardi
26
0.0 0.1 0.2 0.3 0.4 0.50
5
10
15
20 Wf=12 nm
VGS=0 VI D [µ
A/µm
]
VDS [V]
VGS=0.5 V
Interface-state study on sidewalls of InGaAs FinFET
At sidewall: Dit,min ~ 3x1012 eV-1.cm-2
Lg=5 μm
Vardi, DRC 2014
Long-channel MOSFET characteristics (Wf=12~37 nm):
27
Sub-10 nm fin width InGaAs FinFETs
Wf=7 nm, Lg=3 µm MOSFETInGaAs doped channel: • 50 nm thick• ND~1018 cm-3
Oxide: Al2O3/HfO2 (EOT~3 nm)
Fin width: 5 ~ 35 nmFin height: 130 nm100 fins
Vardi, IEDM 2015 28
4. Lateral vs. Vertical Nanowire MOSFETs
Yakimets, TED 2015Bao, ESSDERC 2014
• Nanowire MOSFET: ultimate scalable transistor• Vertical NW: uncouples footprint scaling from Lg and Lc scaling
power, performance and area gains wrt. Lateral NW
5 nm node
30% area reduction in 6T-SRAM19% area reduction in 32 bit multiplier
29
InGaAs Vertical Nanowires on Si by direct growth
Björk, JCG 2012
Selective-Area Epitaxy
Au seed
Vapor-Solid-Liquid (VLS) Technique
InAs NWs on Si by SAE
Riel, MRS Bull 2014
30
Persson, DRC 2012Tomioka, Nature 2012Tanaka, APEX 2010
InGaAs VNW-MOSFETs by bottom-up techniques
Many device demonstrations:
31
InGaAs VNW-MOSFETs fabricated via top-down approach @ MIT
Zhao, IEDM 2013
Top-down approach: flexible and manufacturable
n+ InGaAs, 70 nm
i InGaAs, 80 nm
n+ InGaAs, 300 nm
Starting heterostructure:
n+: 6×1019 Si doping
Xin Zhao
32
Key enabling technology I: RIE by BCl3/SiCl4/Ar chemistry
• Sub-30 nm resolution• Aspect ratio > 8• Smooth sidewall and surface• Substrate temperature critical during RIE
Zhao, EDL 2014
28 nm
240 nm
33
Key enabling technology II: digital etch
• Planar etching rate: ~1 nm/cycle• Shrinks NW diameter by 2 nm per cycle• Unchanged shape• Reduced roughness
Self-limiting O2 plasma oxidation + H2SO4 oxide removal
before after 5 cycles
Lin, EDL 2014Zhao, EDL 2014
0 200 400 6000.0
0.5
1.0
1.5
2.0ExperimentModel
Rate
(nm
/cyc
le)
Oxidation time (s)
34
Optimized RIE + Digital Etch
• Sub-20 nm resolution• Aspect ratio = 16, vertical sidewall• Smooth sidewall and surface
15 nm
240 nm
Zhao, EDL 2014
35
Process flowTomioka, Nature 2012Persson, DRC 2012
36
NW-MOSFET I-V characteristics D=30 nm
Single nanowire MOSFET: • Lch= 80 nm • 4.5 nm Al2O3 (EOT = 2.2 nm)
At VDS=0.5 V:• gm,pk=280 μS/μm• Ron=759 Ω.μm
0.0 0.1 0.2 0.3 0.4 0.5Vds (V)
Vgs=-0.6 V to 0.8 V in 0.1 V stepRon=759 Ω.µm (at Vgs=1 V)
0
50
100
150
200
I d (µ
A/µm
)
-0.6 -0.4 -0.2 0.0 0.2 0.4 0.60
50
100
150
200
Vgs (V)0
50
100
150
200
250
300gm, pk(Vds=0.5 V)=280 µS/µm
Vds=0.5 V
I d (µ
A/µm
)
g m (µ
S/µm
)
Zhao, IEDM 201337
Impact of nanowire diameter
D↓ S ↓, DIBL ↓, gm ↓, Ron ↑
30 35 40 45 50
150
200
250
300
350
S (m
V/de
c)
Diameter (nm)
Vds=0.5 V
Vds=0.05 V30 35 40 45 50
150200250300350400450
Diameter (nm)
DIBL
(mV/
V)
30 35 40 45 50
200
400
600
800
g m (µ
S/µm
)
Diameter (nm)
Vds=0.5 V
30 35 40 45 50200
400
600
800
1000
1200
Vgs=1 V
R on (
Ω.µ
m)
Diameter (nm)
Error barsindicatedistributionof ~10 devices
38
Impact of digital etch
Digital etch S ↓, gm ↑ Better sidewall interface
Single nanowire MOSFET: D= 30 nm (final diameter)
Zhao, EDL 2014
39
200 400 6000
200400600800
10001200
Vds=0.5 V
S(mV/dec)
g m,p
k(µS/
µm)
Tanaka, APEX 10 Tomioka, IEDM 11 Tomioka, Nature 12 Persson, DRC 12 Persson, EDL 10 This work (Top down)
Bottom up
This work
Benchmarking
• Trade-off: D↓ S↓ but also gm↓• Top-down approach as good as bottom-up approach
Persson, DRC 2012
Tomioka, Nature 2012 Tanaka, APEX 2010
Persson, EDL 2012
40
InGaAs VNW MOSFET Concerns(a short list…)
• Relatively poor subthreshold behavior
small VDS
0 5 10 15 20 25 300
100
200
300
400
500
600
Lg/λeff
S [m
V/de
c]
0 5 10 15 20 25 300
100
200
300
400
Lg/λeffDI
BL [m
V/V]
Auth, EDL 1997Electrostatic characteristiclength for GAA NW
41
InGaAs VNW MOSFET Concerns(a short list…)
• Excess Ioff due to BTBT + Floating BJT Quantization enhances bandgap Vertical bandgap engineering
Wang, ACSNano 2008
InAs NWs
42
• InGaAs low DOS limits current Increase in injection velocity with carrier density more than compensates for this
Yu, TED 2008
InGaAs VNW MOSFET Concerns(a short list…)
D=5 nm (?) NW MOSFET
43
• VT sensitivity to nanowire diameter very tight manufacturing tolerance
Agrawal, TED 2013
Wf=8 nm Trigate MOSFETs
InGaAs VNW MOSFET Concerns(a short list…)
Individual nanowires
Gray: nanowire array
Teherani, PhD MIT, 2015 44
• Asymmetric device behavior: D down ≠ D up more restrictive circuit wiring
InGaAs VNW MOSFET Concerns(a short list…)
Drain at bottom Drain on top
0.0 0.1 0.2 0.3 0.4 0.50
100
200
300
400
500
I d (µ
A/µm
)
Vds(V)
Vgs = -0.6 to 0.6 V in 0.2 V stepD = 40 nm, Lg = 80 nm
45
• Sensitivity to few defects
InGaAs VNW MOSFET Concerns(a short list…)
0.0 0.1 0.2 0.3 0.4 0.5Vds (V)
Vgs=-0.6 V to 0.8 V in 0.1 V stepRon=759 Ω.µm (at Vgs=1 V)
0
50
100
150
200I d
(µA/
µm)
D=7 nm, Lg=14 nm (5 nm design rules) Sg=540 nm2
Dit=2x1011 cm-2.eV-1 Nit~1 eV-1
46
• Top contact resistance • Difficult to introduce mechanical stress• Self-heating• …
InGaAs VNW MOSFET Concerns(a short list…)
47
Conclusions1. Great recent progress on planar, fin and nanowire III-V MOSFETs
2. Vertical Nanowire III-V MOSFET: superior scalability and power/performance characteristics
3. Vertical Nanowire n- and p-type III-V MOSFET: plausible path for co-integration on Si
4. Many demonstrations of InGaAs VNW MOSFETs by bottom-up and top-down approaches
5. Many issues to work out:
– sub-10 nm diameter nanowire fabrication, self-aligned contacts, device asymmetry, Introduction of mechanical stress, VT control, device variability, BTBT and parasitic HBT gain, trapping, self-heating, reliability, co-integration with p-type VNW on Si, …
48
A lot of work ahead but…exciting future for III-V electronics
49
