nanoscale cmos technology

Jong-Ho Lee2nd US-Korea NanoForum, LA

Fabrication and Characterization of bulk FinFETs for Future Nano-

Scale CMOS Technology

Jong-Ho Lee

[email protected] of EECS and National Education Center for Semiconductor Technology

Kyungpook National University, Daegu, 702-701 Korea

2nd US-Korea NanoForum, LA


Contents

Fabrication of Bulk FinFETsby Spacer Technologyby Selective Si3N4 Recess

Device and SRAM Cell CharacteristicsSummary

IntroductionSimulation Study


Introduction

S/D

2010 Time200820062004

Perf

orm

ance

Double/Triple-Gate

Double-Gate CMOS

TG

BG

TG

BG

S/DS/DS/D

G

S/D

Fin Double/Triple-Gate FET

SOI/SiGeG

SOI PD/FD CMOS

G

S/D S/D

Si

SiGe

SiGe CMOS (high mobility)

GHalo

Bulk LDD CMOS (Halo)

Bulk

: Technology Roadmap Beyond Bulk LDD CMOS


Why Double/Triple-Gate Transistor?Robustness against SCEHigher Current DrivabilityGood Subthreshold Swing

Driving Force of CMOS Scaling-down:High Performance and High Integration Density

Introduction

G

G

Si film

S D

A Promising Device StructureDouble/Triple-Gate MOSFETs (or FinFETs)


ZY

X

Silicon Wafer

Current- CarryingPlane

Bottom Gate

S

Top Gate

D

Silicon Wafer

Right Gate

Cur

rent

-Car

ryin

g

Pla

ne

S

D

ZY

XLeft Gate

directioncurrent

(a) Type I (b) Type II

(c) Type III

ZY

X

Silicon Wafer

Right Gate

current directionS

D

Current-Carrying Plane

Left Gate Process technology of FinFET is

easy and compatible with conventional fabrication process

Introduction : Types of Double-Gate Transistors

∗ H. P. Wong et al., IBM, vol. 87, no. 4, p.537, 1999, Proceedings of the IEEE


Type I(Planar DG

FETs)

Type II(Vertical DG

FETs)

Gate Position Top/Bottom Left/Right (or

Cylinder)

Body Shape Horizontal Vertical

Current Carrying

Plane

Horizontal Surfaces Side Surfaces

Current Flow

DirectionHorizontal Vertical

Type

Key Geometry

Type III(FinFETs)

Left/Right

Vertical

Side Surfaces

Horizontal

Types of Double/Triple-Gate Transistors

(Triple-GateMOSFETs)

Left/Right/Top

Vertical

Side Surfaces

Horizontal


Double-Gate Transistor (SOI FinFET)

FinFETsimple, self-aligned double-gatesgood process compatibilitythickness control of fin bodyRIE damage on the channel, high S/D resistance

∗ D. Hisamoto et al., UC Berkeley, p.1032, IEDM 1998


Body-Tied Double/Triple-Gate MOSFET Using Bulk Wafer (Bulk FinFET)

Low wafer costLow defect densityLess back-bias effectHigh heat transfer rate to substrateGood process compatibility

S/D

OxideSi Substrate

S/D

Body

Gate

HFinxj

0

WFin

TFOX

World 1st Cost-Effective Double/Triple-Gate MOSFETs

∗ J.-H. Lee., Korea/Japan/USA patent

Schematic 3-D View


Cross-Sectional Views (Body Structure) for 3-Dimensional Device Simulation

Bulk FinFET

Si sub Si sub

SiO2SiO2

GateGate

SOI FinFET

Fin body Fin body


10 20 30 40 500.1

0.2

0.3

0.4

0.5

Na=1x1019 cm-3

TOX=1.5 nm

xj,S/D=66 nmHFin=70 nm

Bulk SOI

Fin Width (nm)

VT (V

)

LG=25 nm

0

30

60

90

120

150

180

DIB

L (mV

/0.9V)

VT and DIBL versus Fin Width

3-D Simulation Results

∗ J.-H. Lee et al., KNU, p. 102, Si Nanoelectronics Workshop 2003

10 20 30 40 5070

75

80

85

90

95

100

xj,S/D=66 nmHFin=70 nm

Na=1x1019 cm-3

TOX=1.5 nm

LG=25 nm

VDS=0.9 V

Sub

thre

shol

d S

win

g (m

V/d

ec)

Fin Width (nm)

Bulk SOI

VDS=0.05 V

Subthreshold Swing versus Fin Width

22sub bT MS Box

qN tVC

φ= Φ + + for fully depleted body


3-D Simulation Results

S/D

OxideSi Substrate

S/D

Body

Gate

HFinxj

0

WFin

TFOX

0.0 0.2 0.4 0.6 0.8 1.0

300

325

350

375

400

425

450

475

VDS=0.9 V

TOX=1.5 nmSOI

Bulk

Dev

ice

Tem

pera

ture

(K)

Gate Voltage (V)

LG=30 nmsubstrate electrode@ temperature=300 K

Heat

Device Temperature versus Gate Voltage

∗ J.-H. Lee et al., KNU, p. 102, Si Nanoelectronics Workshop 2003

∆T~130 °C

3-D Schematic View of Heat Transfer from Body to Substrate


Si

SiO2 30 nmSiN 25 nmSiO2 30 nm

SiN 80 nm

Poly-Si Spacer30 nm

4 Stack Layer Growth and Deposition

Photo Lithography, SiN Etching, Poly-Si Depo., and Dry Etching

SiN Removal Using Phosphoric Acid

Poly-Si Spacer

Si

Fabrication Steps by Using Spacer Technology


SiO2, SiN, and SiO2 Dry Etching

Top Si Width 25 nmBottom Si Width 100 nm

Si Fin Height 230 nm

Fin Dry Etching

Fabrication Steps

Fin body

Jong-Ho Lee2nd US-Korea NanoForum, LA / 27

SiO2

Thin Ox., Filling, and Densification

Chemical Mechanical Polishing (CMP)

Wet Etch-back

SiO2

Field Oxide Thickness 80 nm

Fabrication Steps


First Body-Tied Triple-Gate MOFET (Bulk FinFET)

As+, 20 keV 3x1015/cm2, 2 Fin

25 nm

50 nm

40 nm

-0.5 0.0 0.5 1.0 1.510-10

10-9

10-8

10-7 VDS = 0.1 V

Vbs = 0 V Vbs = -1 V Vbs = -2 V

Dra

in C

urre

nt (A

)

Gate Voltage (V)ID-VGS Characteristics of 40 nm bulk NFiNFET

Poly-Si

40 nm

Gate Poly-Si Etching

∗ T. Park et al., SNU/KNU, Physica E19, p.6, 2003∗ T. Park et al., SNU/KNU, Nanomes03 2003


Gate Elec

trode

SiO2

SiN

Si Sub

strate

Fin

SiO2

Modified Structure of Bulk FinFET

∗ E. Yoon, J.-H. Lee, and T. park, Korea/Japan/USA/Germany patent

Thick SiN liner formation &SiN liner only recessed

Oxide

Si

CMP andpartial etch-back

Top Si Width 25 nmBottom Si Width 100 nmSi Fin Height 230 nm

Clear Sidewall OpenPlanarization of the Top Surface of Poly-Si Gate

Easy nano-scale patterning of gate poly-Si

unclear


Key Process Steps of Modified Bulk FinFET


Si Substrate

SiN

Gate

SiO2

Act

ive

Fin

SiN

Si Substrate

SEM Views of Key Process Steps

SiN Liner Deposition SiN Recess Etch


Gate Etch Profiles

Along Gate Line Across Gate Line

Mask SiN Width = 70 nm, Poly-Si Neck Width = 47 nmPoly-Si Bottom Width = 64 nm

Si Substrate

SiO2

SiN

Gat

e St

ack SiN

Si Substrate

Poly

-SiGate Stack

Fins

SEM Views of Key Process Steps

∗ T. Park et al., Samung/SNU/KNU, Symp. on VLSI Tech., 2003


SiN Liner Deposition

181 nm

99 nm

61 nm

30 nm

82˚

Si Substrate

SiO2

SiN

Poly-Si

SEM and TEM Views of Key Process Steps

finGate Poly-Si

SiN

Si Fin

Along Gate Line

∗ T. Park et al., Samung/SNU/KNU, IEDM., 2003

12 nm fin body


-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.010-14

10-13

10-12

10-11

10-10

10-9

10-8

10-7

10-6

10-5

10-4

10-14

10-13

10-12

10-11

10-10

10-9

10-8

10-7

10-6

10-5

10-4

IDISUB

ISUB

|I D | , |I SU

B| (

A)

Gate Voltage (V)

VBS = 0 V

TOx,top=5.5 nmTOx,top=1.8 nmHFin=100 nm

LG=100 nmWFin=25 nm

VDS=-0.05 V

-1 V 1 V

VDS=0.05 V

-0.05 V

VDS=-1 V

0.05 V

VDS=1 V

Measured ID-VGS of N and P type bulk FinFETswith drain bias

high Ion(~200 µA/µm @ VGS=1.5 V) compared to that of first lot devices

low Ioff (<0.2 nA/µm @ VDS=1.0 V)

Isub/ID < ~10-7

ID-VGS plot: ID, DIBL, SS, and Isub

Bulk FinFET Measurement


Bulk FinFET

Static Noise Margin (SNM)

Planar MOSFET

Load: 35 nm/90 nmPass: 35 nm/90 nmPull-Down: 50 nm/90 nm

Pull-Down

LoadPass

W/L


Summary

Briefly introduced key features of double/triple-gate FinFETs

Bulk FinFETs were compared with SOI FinFETsNearly the same device scalabilityBetter wafer quality Better characteristics regarding the body connected to sub.

Bulk FinFETs have been demonstrated experimentallyFirst nano-scale bulk FinFET realized by using spacer technologyModified bulk FinFETs realized by adopting selective Si3N4 recess

Good device characteristics were achieved and SNM of 280 mV was obtained from SRAM cell at VCC of 1.2 V


3-D Device Structure for Simulation

LG=25 nm TOX=1.5 nmS/D

Gate

S/D

Si substrate

SiO2

body

S/D S/D

body

Si substrate


Key Process Steps for Thinning of the Fin Body

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nanoscale cmos technology