Nanoarchitectures – Spring 2005copyright Vijay CSE 598 Nanoarchitectures Spring 2005 Lecture 1: Introduction Vijay Narayanan ( vijay)

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  • Nanoarchitectures Spring 2005copyright Vijay CSE 598 Nanoarchitectures Spring 2005 Lecture 1: Introduction Vijay Narayanan (www.cse.psu.edu/~vijay)
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  • Nanoarchitectures Spring 2005copyright Vijay
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  • Nanoarchitectures Spring 2005copyright Vijay What is Nanoscale?
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  • Nanoarchitectures Spring 2005copyright Vijay Nanoscale Dimensions
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  • Nanoarchitectures Spring 2005copyright Vijay Nanoscale Properties A characteristic feature of moving to the nanometer scale (besides the growing domination of quantum physical effects) is that properties of surfaces or boundary layers play an increasing role compared with the bulk properties of the material. Basic structures of nanotechnology are: l Pointlike structures smaller than 100 nm in all three dimensions (e.g. nanocrystals, clusters or molecules) l linear structures which are nanosized in two dimensions (e.g. nanowires, nanotubes and nanogrooves) l layered structures which are nanosized in only one dimension, "inverse" nanostructures (i.e. pores) and complex structures such as supramolecular units or dendrimers.
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  • Nanoarchitectures Spring 2005copyright Vijay Nanoscale properties The reduction of size into the nanometer area often results in characteristic properties of substances and materials which can be exploited for new applications and which do not appear in macroscopic pieces of the same materials. l significantly higher hardness and breaking strength l superplasticity at high temperatures l the emergence of additional electronic states l high chemical selectivity of surface sites l significantly increased surface energy
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  • Nanoarchitectures Spring 2005copyright Vijay How to achieve Nanoscale Features? There are two fundamental strategies for penetrating the nanodimension. "top-down" approach, which is predominant particularly in physics and physical technology. l Here,starting from microtechnology structures and components are more and more miniaturised. "bottom-up/self-assembly" approach in which increasingly complex structures are specifically assembled from atomic or molecular components. l This approach is primarily featured in chemistry and biology, where dealing with objects of the nanometer scale has long been familiar practice.
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  • Nanoarchitectures Spring 2005copyright Vijay Interdisciplinary by Nature Nanotechnology requires a high degree of interdisciplinary and transdisciplinary cooperation and communication. This is due to the fact that at the nano level the terminology of physics, chemistry and biology overlaps and blurs, and also to the fact that techniques from a single discipline can or must be supplemented by techniques and expertise from other disciplines.
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  • Nanoarchitectures Spring 2005copyright Vijay
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  • Nanoarchitectures Spring 2005copyright Vijay What we will cover in this class? Nanoscale CMOS technologies l Process Variations, NonClassical CMOS Structures l Lithography Limits, Interconnect Challenges Novel Memory Architectures l SEM, FeRAM, MRAM, PRAM Nanosensor Architectures Molecular Electronics Spintronics and SET Quantum Cellular Architectures Carbon Nanotube Architectures BioChips
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  • Nanoarchitectures Spring 2005copyright Vijay Class Grading Midterm Exam 30% Final Exam 30% Class Presentations and Project 30% Class Participation 10%
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  • Nanoarchitectures Spring 2005copyright Vijay Reference Books Emerging Nanoelcetronics: Life with and after CMOS, Kluwer Academic Publishers Several Research Papers Books on Library Course Reserve in Pattee Library
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  • Nanoarchitectures Spring 2005copyright Vijay CSE 598 Nanoarchitectures Spring 2005 Lecture 2: Top 10 Challenges Vijay Narayanan (www.cse.psu.edu/~vijay)
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  • Nanoarchitectures Spring 2005copyright Vijay Silicons Roadmap Year199920022005200820112014 Feature size (nm)180130100705035 Chip size (mm 2 )170214235269308354 Clock rate (GHz)*1.21.62.22.83.64.4 Power supply V dd (V)1.81.51.20.90.70.6 Power (W)90130160170174183 For a Cost-Performance MPU (L1 on-chip SRAM cache; 32KB in 1999 doubling every two years) http://www.itrs.net Specification of what must be provided if Moores Law is to continue to hold. * clock rates double the SIA Roadmap
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  • Nanoarchitectures Spring 2005copyright Vijay Moores Law No. of trans./chip doubles every generation (~18 mo.) 100X increase in performance on SPECmarks in the last 10 years (from 33MHz 486 in 1990 to the 1.5GHz Pentium 4 in 2000) l 20X from technology scaling l 4X from architecture l 1.25X from compiler technology How much longer can we track Moores Law ? Source: ISCA01 Panel
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  • Nanoarchitectures Spring 2005copyright Vijay Silicon MOSfet Scaling Effects ParameterRelationScaling W, L, t ox 1/S Area/DeviceWL1/S 2 V dd, V T 1/U C ox 1/t ox S C gate C ox WL1/S I sat C ox W V dd 1/U Current DensityI sat /AreaS 2 /U R on V dd /I sat 1 Intrinsic DelayR on C gate 1/S Intrinsic EnergyC gate V dd 2 1/SU 2 Intrinsic PowerE/Delay1/U 2 Power DensityP/AreaS 2 /U 2 For short-channel transistors (W < 1000nm) Voltages scale by factor U (U < 1.25) Dimensions scale by factor S (S > 1.35)
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  • Nanoarchitectures Spring 2005copyright Vijay Gate Length Scaling
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  • Transistor Integration Capacity On track for 1B transistor integration capacity
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  • Is Transistor a Good Switch? On I = I = 0 Off I = 0 I 0 I = 1ma/u I 0 Sub-threshold Leakage
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  • Hot Chips Hot Chips Why worry about power consumption ? l determines battery life for mobile units and... Year199920022005200820112014 Logic trans/Chip (M) 15602359253,650 14,40 0 Clock rate (GHz) 1.21.62.22.83.64.4 Power supply V dd (V) 1.81.51.20.90.70.6 Power (W) 90130160170174183 E (joules) = C L V dd 2 P 0 1 + t sc V dd I peak P 0 1 + V dd I leakage P (watts) = C L V dd 2 f 0 1 + t sc V dd I peak f 0 1 + V dd I leakage
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  • Challenge #1 Challenge #1
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  • Sub-threshold Leakage Sub-threshold leakage increases exponentially Assume: 0.25 m, I off = 1na/ 5X increase each generation at 30C
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  • SD Leakage Power SD leakage power becomes prohibitive
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  • Leakage Power Leakage power limits Vt scaling A. Grove, IEDM 2002
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  • Challenge #2
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  • Gate Oxide is Near Limit Poly Si Gate Electrode Si Substrate 1.5 nm Gate Oxide 70 nm Si 3 N 4 CoSi 2 130nm Transistor Will high K happen? Would you count on it? Will high K happen? Would you count on it?
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  • Gate Leakage Power If Tox scaling slows down, then Vdd scaling will have to slow down
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  • Energy per Logic Operation Energy per logic operation scaling will slow down
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  • Challenge #4
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  • Frequency & SD Leakage 0.18 micron ~1000 samples 20X 30% Low Freq Low Isb High Freq Medium Isb High Freq High Isb
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  • ~30mV Vt Distribution 0.18 micron ~1000 samples Low Freq Low Isb High Freq Medium Isb High Freq High Isb
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  • Vdd & Temp Variation Heat Flux (W/cm 2 ) Results in Vcc variation Temperature Variation (C) Hot spots
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  • Challenge #6
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  • Exponential Costs G. Moore ISSCC 03 Litho Cost www.icknowledge.com FAB Cost $ per Transistor $ per MIPS
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  • Nanoarchitectures Spring 2005copyright Vijay Fabrication Costs Year199920022005200820112014 Feature size (nm)180130100705035 Chip size (mm 2 )170214235269308354 Logic trans/Chip (M)15602359253,65014,400 Cost of building factories increases by a factor of two every three years; by 2010 a fab may cost $30 billion Mask costs are growing rapidly adding more to upfront NRE for new designs l next-generation lithography methods require expensive complex masks (optical proximity correction (OPC) and phase shift (PSM)) that are computationally complex to generate and that have low error tolerances l multiple masks that require longer write times increase mask production costs
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  • Nanoarchitectures Spring 2005copyright Vijay Exploding NREs A mask set for a complex chip today can cost $500,000 (up from $100,000 a decade ago) At 150nm SEMATECH estimates that we will be entering the regime of the $1M mask set A 70nm ASIC will have $4M NRE ! Source: www.InnovationRevolution.com
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  • Nanoarchitectures Spring 2005copyright Vijay Optical Lithography
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  • Nanoarchitectures Spring 2005copyright Vijay Mask Costs
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  • Nanoarchitectures Spring 2005copyright Vijay Optical Proximity Correction
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  • Nanoarchitectures Spring 2005copyright Vijay Phase Shift Masks Selectively altering the phase of the light passing through certain areas of a photomask in order to take advantage of destructive interference l improve resolution and depth of focus in op