45nm NEW ASICs

1

The Concern: Rising Custom IC Design Costs

(Gate Count)

Source: IBS

2

Why eASIC Exists – There is a Problem

3

Nextreme-2: A New Generation of ASIC

  Standard Cell ASIC Structured ASIC The NEW ASIC

Up -front Costs Very High High Low

Customization Layers All layers Multiple layers One Via layer

Design Flow Very complex verification Complex verification Simple FPGA-like flow

Design Risk Very High High Low

Manufacturing Cycle 12-16 weeks 10-16 weeks 8-10 weeks

Wafer Sharing No No Yes

4

eASIC Testimonials

Time to Market

“In addition to the substantial system cost saving, we were pleasantly surprised at how quick we received working devices and how much lower the power consumption was compared to the low density FPGA we were using.”

Kevin Chiang, R&D Manager of AVTECH.

Time, Cost & Performance

““We were able to develop our eASIC device in a reduced time and cost of a standard cell ASIC and with development costs that were even lower than an FPGA approach and the eASIC device worked right first time on our PBX-A9 validation and development board,”

John Goodacre, Director,ARM

Power, Performance, Price

"Fujitsu Advanced Technologies Ltd is pleased to see that eASIC is delivering a 45nm product. This New ASIC is able to deliver the right combination of performance, power and price combined with low up-front cost. We find the power reduction especially important as we look to add more functionality to our world-class ICT infrastructure products."

Akira Itoh, Director of the Fujitsu Circuit Technology Center of Fujitsu Advanced Technologies Ltd

Power, Cost, Tools, Support

“We successfully ported an existing production FPGA design to eASIC’s Nextreme, validating the power savings, tools suite effectiveness, cost, scheduling and support. All were validated with flying colors, making us eager to proceed to the next phase.” Pierre Boulanger, VP Engineering FLIR Systems

Power, Cost, Market Enabler

“By working with eASIC’s Nextreme NEW ASIC, we were able to develop a reference design for RemoteFX hardware solutions that is low in power consumption as well as low in up-front development cost. We see eASIC’s Nextreme as a catalyst in enabling our RemoteFX partner ecosystem to ramp up their solutions to market readiness.”

Dai Vu, director of Virtualization Solutions Marketing, Microsoft Corp

5

eASIC 45nm Technology Alliance

Common Platform Alliance (GDS Compatible)

Multi-Site Transferable Platform(ATP, ATK, ATT, ATC)

Design Packaging

6

Manufacturing Process

7

Wafer production starts in during design stage

Single Via configuration reduces time and risk

Tested devices delivered

7

Nextreme-2 Overview

• True Dual-Port, 36Kb blocks• Register files • ViaROM

• Differential• Single-ended• Voltage-referenced• Dynamic Phase Alignment (DPA)

• Vertical & Horizontal Spines

• Top, bottom, left & right

• 740K eCells

• 500MHz Logic• 500MHz bRAM

• Support for: - DDR3 up to 1067Mbps - DDR2, DDR, Mobile DDR - RLDRAM II, QDR II+

• Patented Power Management• Clock Gating• Triple-oxide Transistors• Very low leakage

45nm

32 Fully Balanced Clocks

Up to 792 I/Os

Up to 7.4M ASIC Gates

Up to 11.5 Mb Embedded Memory

Up to 16 PLLs

Up to 52 DLLs

Power Optimized Architecture

500 MHz Performance Fabric

8

Nextreme-2 Device HierarchyDevice eGroup

eUnit

eUnit

eUnit

eUnit

bRAM

RF

RF

Block RAM(36Kbits) True Dual Port

32K x116K x 2 8K x 4 4K x 8 4K x 9 2K x 16 2K x 18 1K x 32 1K x 36

512 x 1256 x 2128 x 4 64 x 8 32 x 16 16 x 32

Register File(512 bits) Simple Dual Port

eUnit

576 eCells384 eDFFs

eDFF

eCell

D Q

en

eMotif

3 eCells2 eDFFs

9

Nextreme-2 / 2T Device Family

  N2X260 N2X380 N2X550 N2X580 N2X740

eCells 258,048 387,072 552,960 580,608 737,280

Equivalent Gates (Million) 2.6 3.9 5.5 5.8 7.4

bRAM (# of blocks) 112 168 240 468 320

bRAM (Kbits) 4,032 6,048 8,640 16,848 11,520

Register File (# of blocks) 224 336 480 - 640

Register File (Kbits) 112 168 240 - 320

ViaROM (# of 256Kbit blocks) 4 4 4 4 4

PLL 16 16 16 16 16

DLL 28 36 52 52 52

MGIO 6.5Gbps Transceivers - - - - -

Packages and MGIO / User I/Os

BG480 (23x23) 334 314    

FC480 (23x23) 338 338    

BG484 (23x23)

305* 305*

BG672 (27x27)   452 458

FC672 (27x27)   482 468 468

FC780 (29x29) 480* 480*

BG896 (31x31)     600

FC896 (31x31)     620 620 620

FC1152 (35x35) 792

FC1152 (35x35)    

FC1152 (35x35)     792* 792*

* Note: FPGA Drop-in-Replacement10

DSP Advantage

32

eCell-basedMultiply Accumulate

(MAC)

16

16

16

• Using eCells• 1 TeraMAC DSP processing using eCells* • Granular eCells enable bit-specific implementation

• Using Soft DSP cores• Free Tensilica Diamond DSP cores

     eCells Stratix-IV**      GMACs GMACs

10x10 MAC 196 1,880 1,673

16x16 MAC 384 960 941

18x18 MAC 590 624 74332x32 MAC 710 360 353

** Combination of DSP Blocks and Logic-based MACs

* Raw processing capability

DSP functions implemented using eCells or soft DSP cores

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Nextreme-2 Multiplier Performance

12

Multiplier Size Area Optimized Performance Optimized

Quantized Output eCELLs Performance

(MHz)eCELLs Performance

(MHz)

8x8 112 378 157 452

12x12 241 339 316 392

16x16 429 258 551 342

18x18 495 231 629 337

24x24 914 184 1,083 303

32x32 1,539 150 1,735 265

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36

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Combinatorial Multiplier‘Full Precision’

Multiplier implementation has no pipelining Device Core Voltage: 1.1V

All DSP arithmetic is constructed out of eCells

Power Advantage

Low Power Silicon ProcessLowest Power silicon without performance compromise

No SRAM cells in LUTs or routingVia optimized look-up tables and routing

Lower core voltage options1.1V, 1.2V

GreenPowerViaPower down unused eCells and Memory (zero leakage)

Sleep mode via clock gatingLow power mode

Dynamic power controlColumn based clock gating to control dynamic power

Power Management TechniqueStatic Power

ReductionDynamic Power

Reduction

GreenPowerVia

Technology

Enabled

GreenPowerVia: eASIC’s single Via configuration scheme enables customers to design eco-friendly, green solutions. Enabling up to 80% lower power consumption than FPGAs GreenPowerVia empowers designers to reduce system power or power per channel for their solutions and customers.

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GreenPowerVia – Turn OFF unused Logic!

DUC

DUC CFR

CFR DPD

DPD

AGC

AGCDDC

DDC

Most designs at no more than 80% utilized some as

low as 50-60%

• Unused Logic, Memories, PLLs, I/O are turned OFF to save Power

CPRI

50% Utilization – 50% Lower Power

50% 60% 70% 80% 90% 100%0.000

0.020

0.040

0.060

0.080

0.100

0.120

0.140

0.160

0.180

0.200

Static Power Consumption vs Device Utilization

N2X380

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Lower Static Power with eASIC

Sources:eASIC: Nextreme-2 Power EstimatoreASIC: NX1500 – NX5000 MeasuredAltera: PowerPlay Early Power EstimatorsXilinx: XPower Early Power Estimators

Notes: a. 1 Altera Logic Element = 1 Xilinx Logic Cell = 1 eASIC eCell b. Typical Conditions

Virtex-6

Stratix-4

Stratix-3

Virtex-5

Nextreme

Nextreme-2

Tj – 70 degrees

Note: Static Power even lower if <100% resources usedCyclone-III Spartan-6 LX / LXT

15

Lower Dynamic Power with eASIC

Sources:eASIC: Nextreme / Nextreme-2 Power EstimatorAltera: PowerPlay Early Power EstimatorsXilinx: XPower Early Power Estimators

Medium Density Design: 100K LC, 67K FF, Tj=70C, TR = 25%

Nextreme

Nextreme-2

Virtex-6

Stratix-3

Virtex-5

Stratix-IV

Frequency (MHz)

Cyclone-III

Spartan-6

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Power Advantage Over FPGAs

Market FPGA Total Power (Watts) eASIC Total Power

(Watts)Power

Savings

Wireless Altera EP3SE260 12.2 N2X380 2.61 79%

Ultrasound Altera EP4S530 20.3 N2X740 5.32 75%

Wireless Altera EP3SL150 8.5 N2X380 3.51 59%

Ultrasound Altera EP3SL70 5.26 N2X260 1.44 73%

Wired Xilinx 5VLX150 5.8 N2X550 1.45 75%

Wireless Altera EP4GX230 10.68 N2X550 3.95 63%

~50% to 80% Power Savings over FPGA!

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Nextreme-2 I/Os

• Nextreme-2 IO Slice is common to every I/O• eIO – via configurable single ended, voltage referenced and differential

physical layer• eOLogic - Output DDR logic• eILogic – Input DDR logic• eSERDES – ability to configure multiple channels to support 1.2Gbps

source synchronous interfaces LVDS, SERDES, DPA etc• Eg SPI4.2, Hypertransport, CSIX, UTOPIA, SONET / SDH, SoftCDR

eIO

eOLogic

eILogic

eSERDES

Nextreme-2 I/O Slice

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FPGA Drop-in Replacement Service

• eASIC offers custom package development

service for FPGA drop-in replacement packages

• Both for Xilinx and Altera

• Ask eASIC for Technical Feasibility

• Drop-in devices already implemented

include:

Device Package FPGA

N2X260, N2X380

BG484FC780

Altera •Stratix-III•Stratix-IV

N2X550, N2X740

FC1152 Altera •Stratix-III•Stratix-IV

Dro

p-in

Rep

lace

men

t

Benefits• No PCB redesign needed• Shorter board re-qual time• Faster time to production• No need to pay high ASIC NRE

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Up to 16.8Mb Embedded Memory

Nextreme-2T Overview

• True Dual-Port, 36Kb blocks• ViaROM

• Differential• Single-ended• Voltage-referenced• Dynamic Phase Alignment

• Vertical & Horizontal Spines

• Top, bottom, left & right

• 64 bit eFUSE• 40 bit for user• One bit disables scan

• 128 Extended IO (Do not support SERDES or DDR)

• Support for: - DDR3 up to 1067Mbps - DDR2, DDR, Mobile DDR - RLDRAM II, QDR II+

• 208 Gbps bandwidth

• 1.0V Core Voltage Support• Similar performance to N2X 1.2v

45nm

32 Fully Balanced Clocks

32, 6.5Gbps MGIO Transceivers

Up to 630 I/Os

eFUSE

Up to 20 PLLs

Up to 50 DLLs

Power Optimized Architecture

Extended IO

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Nextreme-2T Device HierarchyDevice eGroup

eUnit

eUnit

eUnit

eUnit

bRAM bRAM

eUnit

576 eCells384 eDFFs

eDFF

eCell

D Q

en

eMotif

3 eCells2 eDFFs

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Block RAM(36Kbits) True Dual Port

32K x116K x 2 8K x 4 4K x 8 4K x 9 2K x 16 2K x 18 1K x 32 1K x 36

Nextreme-2T Device Family

  N2XT330 N2XT580

eCells 331,776 580,608

Equivalent Gates (Million) 3.3 5.8

bRAM (# of blocks) 288 468

bRAM (Kbits) 10,368 16,848

ViaROM (# of 256Kbit blocks) 4 4

PLL 20 20

DLL 50 50

MGIO 6.5Gbps Transceivers 24 32

Packages and MGIO / User I/Os FC780 (29x29) 16 / 400 16 / 400

BG896 (31x31)

FC896 (31x31)

FC1152 (35x35) 8 / 630 8 / 630

FC1152 (35x35) 24 / 556 24 / 556

FC1152 (35x35) 32 / 480

* Note: FPGA Drop-in-Replacement22

MGIO Physical Block Diagram

P2S

S2P

SAPIS (SATA)

General

PIPE (PCIe)

TX

PLL

RX

PLL

P2S

S2P

SAPIS (SATA)

General

PIPE (PCIe)

TX

PLL

RX

PLL

P2S

S2P

SAPIS (SATA)

General

PIPE (PCIe)

TX

PLL

RX

PLL

P2S

S2P

SAPIS (SATA)

General

PIPE (PCIe)

TX

PLL

RX

PLL

CMU

REF_CLK BUF.PMA

PCS

Channel 0 Channel 1 Channel 2 Channel 3

Tx Rx Tx Rx Tx Rx Tx Rx

MGIO arranged as Quads. Each Quad shares a common PLL. Clock division supported.

PCS allows user to select between:• PCI Express PIPE interface• SATA SAPIS interface• more general interface for use with other

standards

3 Power States:Normal - 42mW (1.25Gbps), 70mW (5.0Gbps)

Partial - : 31mW (1.25Gbps), 53mW (5.0Gbps)

Slumber - 16mW (1.25Gbps), 20mW (5.0Gbps)

Lanes operate at 1x 2x or 4x multiples

Multi-Protocol Support with up to 6.5Gbps

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Single MGIO Block Diagram

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RX CLR (local)

8b/16b/10b/20b BIST Checker

Polarity / Bit Order

(reg 0)

Symbol Alignment

Clock Compensation

FIFO

Lane Deske

wFIFO

20b/16b Decoder

Polarity /Bit Order

(reg1)

Runlength Detect

OOB Detect

RX-PCS

S2P

RX

Inp

ut

Bu

ffer

RX-EQ/ DFE

CDR

RX-PMA

TX CLK

TX Data / Control8/10 bits

OR16/20 bits

TX CLK(from CMU)TX CLK(Quad)

TX CLK(local)

TX-PCS

Termination

P2STX

D

rive

r

OOB

TX-PMA

Polarity / Bit Order

(treg0)

16b/20b Encoder

Polarity / Bit Order

(treg1)B A

BIST Data Delay

8b/16b/10b/20b BIST Generator (One per Quad)

Serial Links

eCells

Termination

RX Data / Status

8/10 bitsOR

16/20 bits

Nextreme-2T MGIO Protocol Support

CPRI -1228 CPRI-2457

SFI-5

Networking

Li ne Rate - Gbps

Computing

0 1 2 3 74 5

1G-FC

1GbE

iSCSI

HD-SDI

SATA 1.5

SAS 3.0

OC-48

Infiniband

PCIe Gen 1

SRIO v1.3

SATA 6

SAS 6.0

OBSAI 3072SRIO v2.1

XAUI HiGig/HiGig+

PCIe Gen 2

3G HD-SDI

Video

Storage

Telecom

6

Double/R XAUI

SATA 3

Interlaken

8

CEI-6G

CPRI-3072OBSAI 6144OBSAI 1536

SGMII

SPAUI 3.125

DisplayPort 1.62 DisplayPort 2.7

USB3.0

GEPON

2G-FC 4G-FC

SPAUI 6.25

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CPRI-6144

Low Power 6.5G Transceivers

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Device Power per channel @ 6.144 Gbps** Power Savings

eASIC Nextreme-2T 141mW

Altera Stratix-IV GX 232mW* 39%

Xilinx Virtex-6 253mW* 44%

Altera Arria-2 GX 230mW* 39%

*data sourced from FPGA power estimator spreadsheets. ** Power is per lane (in active quad configuration) including PMA, PCS and CMU (PLL)

~40% Power Savings over FPGA!

CPRI Demonstrator

Low Power Nextreme-2T 6.5 Gbps device driving CPRI interface to RRH.

CPRI Mask Compliant

Spectral Plots from RRH Antenna -1.4% EVM.

Radiocomp CPRI / OBSAI RRH

10M optical fiber

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MGIO Characterization Report

• MGIO characterization report is

available now

• Includes:• MGIO test board setup

• PLL characterization

• PMA Tx characterization

• PMA Rx characterization

• Power consumption

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Familiar IDE Environment: - Easy FPGA Conversion

- eZ-IP Wizards - Graphical Layout - Pin Placement - Macro Placement - Floorplanning

- Push Button Flow

eTools – A Familiar IDE for FPGA Designers

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eTools 8.2 – More Control…..Better Results

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New features in 8.2:

Improved QoR for ePlacer/Resynthesis

• ~20 / 30% improvement in “Push-Button” Results*

• Run time improvement as high as 50% over eTools 8.1

• Automatic pre-buffering and post-buffering netlist

resynthesis (worst path optimization)

• Ability to use propagated clocks and OCV in

ePlacer/Resynthesis

• Automatic netlist constant propagation after floorplanning

More Control of Implementation Tools

Synthesis 3rd Party Support

• Support for DC Ultra, derating, multiple CPUs and wire loads

for DC Synthesis

Available Now

Evaluate Today!

* QoR improvements are design dependent

Nextreme-2 (eTools 8.2) Design Flow

(Design Services required)

Hand-off - Option 1(Synthesized Netlist)

Hand-off - Option 2(Placed Netlist)

Design Conversion

Back End Implementation

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eZ-IP Alliance

• eZ-IP Cores • Digital Signal Processing

• FFT, FIR Compiler, NCO, CIC Filter• Turbo CODECs, Digital Pre-Distortion

• Embedded Processing• µP cores: Coldfire, Tensilica, Gaisler Research, OpenCores• DSP cores: Tensilica

• Interfaces• PCIe Gen1/2, PCI, PCI-X• 10/100/1G/10/40G Ethernet• CPRI, sRIO, OBSAI• Interlaken• DDR3, DDR2, DDR, M-DDR• USB, SPI, I2C

• Encryption/Decryption• AES, DES, MD5, SHA

• Video/Image Processing• H.264, MPEG-4, VGA

Silicon proven with Development Board

Synthesizable RTL

Flow Verified

Level 3

Level 1

Level 2

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6.5 Gbps Transceiver Fully Functional

• MGIO operate at all speeds (1.25-6.5 Gbps)

• All physical layer characterization completed

• MGIO characterization report available now

• Next Step: Protocol and

IP qualification:• CPRI & OBSAI

• PCI Express Gen 1 & Gen 2

• XAUI, Double XAUI

• Gigabit Ethernet

• SRIO

• Interlaken

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2.5 Gbps PRBS 16

34 Inch – FR4 @ 6.5 Gbps

Summary

• eASIC 45nm devices, proven, in volume production• Low up-front costs

• Fast turnaround

• Simple design flow

• Up to 80% lower power than FPGAs

• N2XT330 and N2XT580 available now – Up to 32 MGIO

• MGIO characterization report available now

• Evaluate eTools 8.2 Today and get a Power Reduction

Estimate from eASIC

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Thank You

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