Upload
others
View
1
Download
0
Embed Size (px)
Citation preview
MultiMulti--site Probing forsite Probing forWaferWafer--Level ReliabilityLevel Reliability
Louis Solis De AnconaLouis Solis De Ancona11
Sharad PrasadSharad Prasad22, David Pachura, David Pachura22
11AgilentAgilent TechnologiesTechnologies22LSILSI Logic CorporationLogic Corporation
s �
2Southwest Test Workshop 2003
OutlineOutline
Introduction
Multi-Site Probing Challenges
Multi-Site Wafer Level Reliability ExamplesTDDBNBTI
Conclusions
3Southwest Test Workshop 2003
Traditional ReliabilityTraditional Reliability
Long-term reliability is often equated to packaged parts tests
Predictive of lifetime which is the key for designers
Slice the wafer; package the devices; apply the stress in a special oven
Packaging a wafer requires time, and several steps at extra cost
Separate packaging handling operations may introduce damages and limits the number of available pins
Spatial correlation is often lost
If a lot of wafers is “defective” you have to do it all over
4Southwest Test Workshop 2003
Wafer Level ReliabilityWafer Level Reliability
On-wafer does not require extra steps and is immediately available!
On-wafer differentiates damage introduced by packaging operations!
Spatial correlation is preserved!
As oxides become thinner the effects of packaging damage due to ESD are unknown. ESD effects on new gate materials are unknown
Cu difficult to bond. In general, for interconnect reliability additional Al bond pads are required
5Southwest Test Workshop 2003
OutlineOutline
Introduction
Multi-Site Probing Challenges
Multi-Site Wafer level Reliability ExamplesTDDBNBTI
Conclusions
6Southwest Test Workshop 2003
MultiMulti--Site Probing OpportunitiesSite Probing Opportunities
Stressing many devices at the same time, or
Devices can be grouped in categories, thus stress groups of devices can be created
Different oxide thickness, or device types, can be stressed at the same time
User defined parameter tests pre- and post-stress, can be achieved individually or by group
Instrumentation and software are required to have features to manage multiple devices and conditions
7Southwest Test Workshop 2003
InstrumentationInstrumentation
Voltage measurement resolution 2 µV and forcing voltage resolution 100µV
Current measurement resolution 10fA and force current resolution 50fA
Switching Matrix < 0.1pA leakage per channel and fast switching times
Support matrix or multiplexor cards
8Southwest Test Workshop 2003
I. SoftwareI. Software
Traditional package level testers can group test hundreds of devices, however because the number of devices and tester architecture their scan time can be in hours
Software must scans in milliseconds to determine the exact time to breakdown, or NBTI phenomena, etc
Prevents relaxing the devices under stress. This is, the devices are always under stress, unless they are being measured
Each DUT may be stressed individually, or devices grouped in multiple sets
9Southwest Test Workshop 2003
II. SoftwareII. Software
Effectively the system has a per-pin architecture
Scanning can be linear, logarithmic or the intelligent, rules based, Owl Adaptive Scan™
The intelligent Owl Adaptive Scan™ changes the scan frequency as device parameters change, thus breakdown, or other phenomena, can be accurately determined
10Southwest Test Workshop 2003
Adaptive ScanAdaptive ScanTMTM
Owl Adaptive Scan™ adapt to changes in the device behavior and can determine soft breakdown
1.00E-08
1.00E-07
1.00E-06
1.00E-05
1.00E-04
1.00E+00 1.00E+01 1.00E+02 1.00E+03 1.00E+04 1.00E+05 1.00E+06
Time [secs]
Cur
rent
[A]
Logarithmic Adaptive Scan
0.00E+00
2.00E-07
4.00E-07
6.00E-07
8.00E-07
1.00E-06
1.20E-06
1.40E-06
1.60E-06
3.00E+05 3.00E+05 3.00E+05 3.00E+05 3.01E+05 3.01E+05 3.01E+05 3.01E+05 3.01E+05 3.02E+05
11Southwest Test Workshop 2003
TDDBTDDB
For oxides > 4nm oxide breakdown and breakdown model is well understood.
For oxides <4nm there is a need to determineWhat is breakdown?How do you model it?
12Southwest Test Workshop 2003
Oxide BreakdownOxide Breakdown
For thick oxides there is a clear breakdown.
Thin oxide breakdown is not clearly definedThere is a soft breakdownSelf annealing effect?How do we define this breakdown and how do we determine it experimentally?
13Southwest Test Workshop 2003
Thick Oxide Breakdown BehaviorThick Oxide Breakdown Behavior
Thick oxides have a “hard” breakdown
Breakdown is well defined
1.00E-07
1.00E-06
1.00E-05
1.00E-04
1.00E-03
1.00E-02
1.00E-01
1.00E+00
1.0E+00 1.0E+01 1.0E+02 1.0E+03 1.0E+04 1.0E+05 1.0E+06
Time [secs]
Cur
rent
[A]
14Southwest Test Workshop 2003
Thin Oxide BreakdownThin Oxide Breakdown
Where is the breakdown?
How do you detect this behavior?
In thin oxides the breakdown is not well defined and the challenge is to detect this atypical behavior
1.00E-04
1.00E-03
1.00E-02
1.0E+00 1.0E+01 1.0E+02 1.0E+03 1.0E+04 1.0E+05 1.0E+06
Time [sec]
Cur
rent
[A]
15Southwest Test Workshop 2003
TDDB Data From MultiTDDB Data From Multi--ProbeProbe
16Southwest Test Workshop 2003
QBD QBD
Spatial resolution is preserved
Weak dies, if present, can be located immediately
Further analysis can be done to verify the causes of early failure
17Southwest Test Workshop 2003
TTF wafer map and Weibull PlotTTF wafer map and Weibull Plot
Spatial resolution and statistical data is obtained at the same time
18Southwest Test Workshop 2003
OutlineOutline
IntroductionIntroduction
MultiMulti--Site Probing Challenges Site Probing Challenges
MultiMulti--Site Wafer level Reliability ExamplesSite Wafer level Reliability Examples
TDDBTDDB
NBTINBTI
ConclusionsConclusions
19Southwest Test Workshop 2003
NBTI Measurement IssuesNBTI Measurement Issues
NBTI is a mechanism that degrades PMOS devices
Removing stress can recover the device
Recovery time is very short
In actual circuits devices may not recover, however during measurements:
If the instrumentation is not fast enough then it will give false information
20Southwest Test Workshop 2003
STUDY OF Sub-Quarter-Micron PMOSFET NBTI UNDER DC and AC STRESSErhong Li, Sharad Prasad, Sangjune Park and John Walker ,PV2003-06 p408 Electrochemical
Society Proceedings, Paris 2003
1 10 1000.1
1
10
22A, 50/0.13, 25oCVstress = -1.8 V
∆ Vt
(mV)
& ∆
Icp
(pA
) & ∆
Vt d
ue to
∆Ic
p (m
V)
T im e (M in)
∆Vt ∆ Icp ∆Vt due to ∆ Icp
21Southwest Test Workshop 2003
Stress Relaxation Effect in NBTIStress Relaxation Effect in NBTI
Die 1
Die 30V
t[a
.u.]
Vt
[a.u
.]
Die 1
Die 30∆∆
Time [a.u.]Time [a.u.]
22Southwest Test Workshop 2003
I. ConclusionsI. Conclusions
In this presentation we have highlighted several advantages and opportunities of multi-site wafer level probing for reliability measurements
Multi-site wafer level probing offers the distinctive advantage of rapidly and accurately characterize new materials or products.
A challenge for multi-site probing is to have and properly configure equipment and software to take full advantage of the architecture
Actual measurement times must be in milliseconds
23Southwest Test Workshop 2003
II. ConclusionsII. Conclusions
System must avoid relaxation effects
It is key to design an appropriate probe card pattern for testing multiple sites common to several tests, and schedule tests to maximize probe card test coverage
Multi-site probing offers exciting challenges, but great benefits, to characterize new materials or products and predict accuratelytheir reliability:
e.g TDDB: In one touchdown is possible to measure and calculate the Voltage Acceleration factor, Γ
Probe card and prober should must be able to withstand high temperatures for a full characterization set
24Southwest Test Workshop 2003
User InterfaceUser Interface