Readregister 1

Readregister 2

Writeregister

Writedata

Writedata

Registers

ALU

Add

Zero

Readdata 1

Readdata 2

Signextend

16 32

Instruction[31–0] ALU

result

Add

ALUresult

Mux

Mux

Mux

Address

Datamemory

Readdata

Shiftleft 2

4

Readaddress

Instructionmemory

PC

1

0

0

1

0

1

Mux

0

1

ALUcontrol

Instruction [5–0]

Instruction [25–21]

Instruction [31–26]

Instruction [15–11]

Instruction [20–16]

Instruction [15–0]

RegDstBranchMemReadMemtoRegALUOpMemWriteALUSrcRegWrite

Control

   

Multi Cycle Datapath

Slides courtesy of Professor Tod Amon, Southern Utah University, with minor modifications by Nathan Sprague

   

ALU control lines0000 = and0001 = or0010 = add0110 = subtract0111 = slt1100 = NOR

   

Simple combinational logic

Operation2

Operation1

Operation0

Operation

ALUOp1

F3

F2

F1

F0

F (5– 0)

ALUOp0

ALUOpALU control block

R­format Iw sw beq

Op0Op1Op2Op3Op4Op5

Inputs

Outputs

RegDst

ALUSrcMemtoReg

RegWriteMemReadMemWrite

BranchALUOp1

ALUOpO

   

Control lines based on opcode

Instruction RegDst ALUSrcMemto­

RegReg 

WriteMem Read

Mem Write Branch ALUOp1 ALUp0

R­format 1 0 0 1 0 0 0 1 0lw 0 1 1 1 1 0 0 0 0sw X 1 X 0 0 1 0 0 0beq X 0 X 0 0 0 1 0 1

   

Problems with single cycle implementation...

   

Mult­cycle design...

Readregister 1

Readregister 2

Writeregister

Writedata

Registers ALUZero

Readdata 1

Readdata 2

Signextend

16 32

Instruction[25–21]

Instruction[20–16]

Instruction[15–0]

ALUresult

Mux

Mux

Shiftleft 2

Instructionregister

PC 0

1

Mux

0

1

Mux

0

1

Mux

0

1A

B 0123

ALUOut

Instruction[15–0]

Memorydata

register

Address

Writedata

MemoryMemData

4

Instruction[15–11]

   

Readregister 1

Readregister 2

Writeregister

Writedata

Registers ALUZero

Readdata 1

Readdata 2

Signextend

16 32

Instruction[31–26]

Instruction[25–21]

Instruction[20–16]

Instruction[15–0]

ALUresult

Mux

Mux

Shiftleft 2

Shiftleft 2

Instructionregister

PC 0

1

Mux

0

1

Mux

0

1

Mux

0

1A

B 0123

Mux

0

1

2

ALUOut

Instruction[15–0]

Memorydata

register

Address

Writedata

MemoryMemData

4

Instruction[15–11]

PCWriteCondPCWrite

IorDMemReadMemWrite

MemtoRegIRWrite

PCSource

ALUOp

ALUSrcB

ALUSrcA

RegWrite

RegDst

26 28

Outputs

Control

Op[5–0]

ALUcontrol

PC [31–28]

Instruction [25­0]

Instruction [5–0]

Jumpaddress[31–0]

   

Instruction Fetch Instruction Decode and Register Fetch Execution, Memory Address Computation, or 

Branch Completion Memory Access or R­type instruction 

completion Write­back step

INSTRUCTIONS TAKE FROM 3 ­ 5 CYCLES!

Five Execution Steps

   

Use PC to get instruction and put it in the Instruction Register.

Increment the PC by 4 and put the result back in the PC.

      IR <= Memory[PC];PC <= PC + 4;

Can we figure out the values of the control signals?

What is the advantage of updating the PC now?

Step 1:  Instruction Fetch

   

Read registers rs and rt in case we need them Compute the branch address in case the 

instruction is a branch

A <= Reg[IR[25:21]];B <= Reg[IR[20:16]];ALUOut <= PC + (sign ­ 

extend(IR[15:0]) << 2);

We aren't setting any control lines based on the instruction type (we are busy "decoding" it in our control logic)

Step 2:  Instruction Decode and Register Fetch

   

ALU is performing one of three functions, based on instruction type

Memory Reference:ALUOut <= A + sign­extend(IR[15:0]);

R­type:ALUOut <= A op B;

Branch:if (A==B) PC <= ALUOut;

Step 3 (instruction dependent)

   

Loads and stores access memory

MDR <= Memory[ALUOut];or

Memory[ALUOut] <= B;

R­type instructions finish

Reg[IR[15:11]] <= ALUOut;

Step 4 (R­type or memory­access)

   

• Reg[IR[20:16]] <= MDR;

Which instruction needs this?

Write­back step

   

Value of control signals is dependent upon:– what instruction is being executed– which step is being performed

Use the information we’ve accumulated to specify a finite state machine– specify the finite state machine graphically, or– use microprogramming

Implementation can be derived from specification

Implementing the Control

   

Note:– don’t care if not mentioned– asserted if name only– otherwise exact value

How many state bits will we need?

Graphical Specification of FSMMemRead

ALUSrcA = 0IorD = 0IRWrite

ALUSrcB = 01ALUOp = 00

PCWritePCSource = 00

ALUSrcA = 0ALUSrcB = 11ALUOp = 00

ALUSrcA = 1ALUSrcB = 00ALUOp = 10

ALUSrcA = 1ALUSrcB = 10ALUOp = 00

MemReadIorD = 1

MemWriteIorD = 1

RegDst = 1RegWrite

MemtoReg = 0

RegDst = 1RegWrite

MemtoReg = 0

PCWritePCSource = 10

ALUSrcA = 1ALUSrcB = 00ALUOp = 01

PCWriteCondPCSource = 01

Instruction decode/register fetch

Instruction fetch

0 1

Start

Jumpcompletion

9862

3

4

5 7

Memory readcompleton step

R­type completionMemoryaccess

Memoryaccess

ExecutionBranch

completionMemory address

computation

   

Implementation:

Finite State Machine for Control

PCWritePCWriteCondIorD

MemtoRegPCSourceALUOpALUSrcBALUSrcARegWriteRegDst

NS3NS2NS1NS0

Op5

Op4

Op3

Op2

Op1

Op0

S3 S2 S1 S0State register

IRWrite

MemReadMemWrite

Instruction registeropcode field

Outputs

Control logic

Inputs

   

PLA Implementation Op5

Op4

Op3

Op2

Op1

Op0

S3

S2

S1

S0

IorD

IRWrite

MemReadMemWrite

PCWritePCWriteCond

MemtoRegPCSource1

ALUOp1

ALUSrcB0ALUSrcARegWriteRegDstNS3NS2NS1NS0

ALUSrcB1ALUOp0

PCSource0