Multi Clock Design

8/18/2019 Multi Clock Design

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Vietnam National University

Integrated Circuit Design Research and Education Center

Hardware Description Language

Verilog HDL

Multiple Clock Domains

D+ Training Program

Lecturer: Đỗ Ngọc Quỳnh

E-mail:[email protected]


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Introduction Clock Domain Crossing Issues

Synchronous clock domain crossings

examples

Exercise – Dual clock FIFO design

Contents


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INTRODUCTION



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Introduction

CPU_core

cpu_clock

UART

uart_clock

bus_clock

TIMER

MEM_

CONTROLLER

timer_clock

Timer clock domainUART clock domain

CPU clock domain


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Signal A is output of the C1 clock domain and be

captured by the C2 clock domain.

Depending on the relationship between the two clocks,

there could be different types of problems in transferring

data from the source clock to the destination clock.

Along with that, the solutions to those problems can

also be different.

Two clock domains

FA FB

D

A

Q D Q

B

C1 C2


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CLOCK DOMAIN CROSSING

ISSUES



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FF Setup & hold times (review)

7

tsu th

D

CLK

Q

DFF

DQ

CLK

setup time hold time

clock edge


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Data change at clock edge

C2

C1

A

B

A generated by C1

A sampled by C2Clock signal isinitially metastable

setup or hold violation


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If the unstable data is fed to several other places in the

design, it may lead to a high current flow and even chipburnout in the worst case.

The design can enter into an unknown functional state,leading to functional issues in the design.

The propagation delay could be high leading to timing

issues.

Metastability effect

Imax

Ileakageon

on

NOT gate

Vdd


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Metastability problems can be avoided by addingspecial structures known as synchronizers in the

destination domain. The synchronizers allow sufficient

time for the oscillations to settle down and ensure that a

stable output is obtained in the destination domain. Acommonly used synchronizer is a multi-flop

synchronizer.

Metastable solution

FA FB

D

A

Q D Q

B

C1

C2

FB

D Q

Bsync


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Data Loss

C2

C1

A

B

A generated by C1

Data capture in 2nd clock cycle

Data capture in 1nd clock cycle

A change very closely

with C2 posedge


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Clock C1 is twice as fast as the destination clock C2 andthere is no phase difference between the two clocks.

Assume that the input data sequence “A” generated on thepositive edge of clock C1 is “00110011”. The data B capturedon the positive edge of clock C2 will be “0101”.

All the transitions on signal A are captured by B, the data is

not lost.

No loss data example

C1

C2

A

B


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The data change in the C1 domain must held long enough tobe properly captured in the C2 domain

After every transition on A, at least one C2 clock edgeshould arrive where there is no setup or hold violation so thatthe source data is captured properly in the destination

domain.

Data bit loss

C1

C2

A

B

Data bit loss


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X[1:0] signals change from 00 to 11, but Y[1:0] signals

change from 00 to 01 to 11

Data Incoherency

C1

C2

X[0]

Y[0]

X[1]

Y[1]

Valid data

Invalid data


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MUX recirculation technique

FA FB

D

EN

Q D Q

B

C1

C2

FB

D Q

Bsync

FA

D Q

C1

FA

D Q

C1

FB

D Q

B[1]

FB

D QB[0]

0

1

0

1

A[1]

A[0]Data captured when Bsync = 1(2 cycles of C2 after EN = 1)

G E di t A id D t


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Decimal Bin [3:0] Gray [3:0]

0

0000

0000

1 0001 0001

2 0010 0011

3

0011

0010

4 0100 0110

5

0101

0111

6 0110 0101

7 0111 0100

8

1000

1100

9 1001 1101

10

1010

1111

11

1011

1110

12 1100 1010

13

1101

1011

14 1110 1001

15

1111

1000

Gray Encoding to Avoid Data

Incoherence

For vector controlsignals (multi-bit

signals, such as

address buses), the

usual solution is to use

a Gray code when

crossing a clock domain

boundary. A Gray code

ensures that only a

single bit changes asthe bus counts up or

down.

H d h ki D t b t Cl k


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Handshaking Data between Clock

Domains (1/2)

ClockDomain

C1

ClockDomain

C2

FB

D Q

B

C2

FB

D Q

req_syncreq

FA

DQ

A

C1

FA

DQ

ack_sync ack

Data bus

(Transit active)

(transit_done)

H d h ki D t b t Cl k


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Handshaking Data between Clock

Domains (2/2)

ClockDomain

C1

ClockDomain

C2

C2

req_syncreq

C1

ack_syncack

Data bus

(Transit active)

(transit_done)

Process

ack

Idle

StartDone

req_sync

S

y n c h or ni z er

S y n c h or ni z er

Wait

req

Idle

Start

reqDone

go

!ack_sync

ack_sync

U i FIFO f P i D t


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One of the most popular methods of passing data

A dual port memory is used for the FIFO storage.

One port is controlled by the sender, the other port is controlled bythe receiver.

Two control signals are used to indicate if the FIFO is empty, full

Using FIFO for Passing Data

between Clock Domains

Clock

Domain

C1

Clock

Domain

C2

Dual clockFIFO

Dual clock

FIFO

C1 C2


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SYNCHRONOUS CLOCK

DOMAIN CROSSINGS

EXAMPLES



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The clocks C1 and C2 have the same frequency and 0phase difference.

The clocks C1 and C2 are identical and generated fromthe same root clock, the data transfer from C1 to C2 isessentially not a clock domain crossing.

For all practical purposes, this is the case of a single

clock design.

Same frequency, same phase clocks

C1

C2

A

B

Same frequency and constant


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These are the clocks having the same time period but aconstant phase difference. A typical example is the use of aclock and its inverted clock.

Another example is a clock which is phase shifted from itsparent clock, for example by T/4 where T is the time periodof the clocks.

Same frequency and constant

phase difference

C1

C2

A

B3/4 clock

cycle


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Integer multiple clocks (TC2 = 3TC1)

C1

C2

T

2T3T

Data change points

T, 2T, or 3T time available for data capture

depending on data change point

The worst case is T time

problem of data loss in

the case of fast to slowclock crossing ?

Vi t N ti l U i it


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Questions and

iscussion

Vi t N ti l U i it


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EXERCISE – DUAL CLOCK

FIFO DESIGN



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Single clock FIFO

26

clk rst_n

data_out[7:0]

data_in[7:0]

status signals

wr

rd


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Dual clock FIFO

waddr

wq2_rptr

wdata

wfull

winc

wclk

wrst_n

raddr

rq2_rptr

rdata

rinc

rclk

rrst_n

rempty

wdata rdata

waddr raddr

wenable

FIFOwptrandfullflag

FIFOrptr andempty

flag

wclk domain rclk domain


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Upgrade the single clock FIFO in subject 2 to dual clock

FIFO

Two clock domains are asynchronous

Using Gray code technique for read & write pointers

Checking RTL code with Leda Simulating the design with ModelSim

Problem

Binary count values sampled in


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Binary count values sampled in

mid-transition


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Binary-to-Gray

b[n-1]

g[n-2]g[n-1]

b[n-2]

g[n-3]

b[1]

g[0]

b[0]b[n-3]

(MSB)

Binary to Gray

converter

gray[0] = bin[0] ^ bin[1];

gray[1] = bin[1] ^ bin[2]; gray[2] = bin[2] ^ bin[3];

gray[3] = bin[3] ^ 1'b0 ; // same as gray[3] = bin[3];


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FIFO full & empty with Binary


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Counter with different size problem


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Full & empty flags with Gray


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FIFO empty flag

rinc

rempty

+

rgnext rptr [ASIZE:0]

rbnext rbin [ASIZE:0]

only use n-1 bits to address the FIFO memory

binary

reg

gray

regrclk

rrst_n

rq2_wptr wptr [ASIZE:0]

=?rempty

rq1_wptr

Binary toGray

converter

rptr [ASIZE:0] = rq2_wptr [ASIZE:0]


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FIFO full flag

winc

wfull

+

wgnext wptr [ASIZE:0]

wbnext wbin [ASIZE:0]

only use n-1 bits to address the FIFO memory

binary

reg

gray

regwclk

wrst_n

wq2_rptr rptr [ASIZE:0]

{~wptr [ASIZE:ASIZE-1],

wptr [ASIZE-2:0]

=?wfull

wq1_rptr

Binary to

Grayconverter

{~wptr [ASIZE:ASIZE-1], wptr [ASIZE-2:0] == wq2_rptr



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Multi Clock Design