Multi Carrier Modulation - DTU Electronic Theses and ...etd.dtu.dk/thesis/219798/nilsson.pdf · Multi Carrier Modulation 2 Abstract Class-D amplifiers yield high efficiency but are

Daniel Nilsson

Multi Carrier Modulation Bachelor thesis, January 2008

Multi Carrier Modulation

Rapporten er udarbejdet af: Daniel T. Nilsson Vejleder(e): Michael A.E. Andersen Arnold Knott (Harman/Becker Automotive Systems GmbH)

Ørsted•DTU Sektion eller center Danmarks Tekniske Universitet Adresse Bygning 2800 Kgs. Lyngby Denmark Udgivelsesdato:

31. Januar

Klasse:

Offentligt

Udgave:

1. udgave

Bemærkninger:

Denne rapport er indleveret som led i opfyldelse af kravene for opnåelse af Bachelor på Danmarks Tekniske Universitet. Rapporten repræsenterer 15 ECTS point.

Rettigheder:

© Daniel T. Nilsson, 2008


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Multi Carrier Modulation Abstract ................................................................................................................................................2 Referat (Danish)...................................................................................................................................2 1 Introduction.......................................................................................................................................3 2 Theory of Modulation .......................................................................................................................4

2.1 Basic PWM Modulation ............................................................................................................4 2.2 Multi Carrier Modulation...........................................................................................................6 2.3 ORing and ANDing MCM.........................................................................................................6 2.4 Master-Slave MCM....................................................................................................................7

3 OrCAD Simulations..........................................................................................................................9 4 Amplifier.........................................................................................................................................14

4.1 Conceptual Diagram ................................................................................................................14 4.2 Clock divider............................................................................................................................15 4.3 Integrators ................................................................................................................................18 4.4 Level Shifter.............................................................................................................................21 4.5 Gate Driver IRS20124 .............................................................................................................23

4.5.1 Low-side Driver ................................................................................................................23 4.5.2 High-side Driver and Bootstrap Circuitry.........................................................................24 4.5.3 Programmable dead-time ..................................................................................................24

4.6 Active Turn-off ........................................................................................................................25 4.7 Output Filter.............................................................................................................................26 4.8 Feedback Loop.........................................................................................................................27 4.9 2.5V Biasing.............................................................................................................................28

5 PCB Layout.....................................................................................................................................29

5.1 Important Measures When Laying Out PCB ...........................................................................29 5.2 The Prototype...........................................................................................................................31

6 Measurements .................................................................................................................................35 7 Results and Conclusions .................................................................................................................38 8 Outlook ...........................................................................................................................................38 9 References.......................................................................................................................................39 10 Appendix.......................................................................................................................................40


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Abstract Class-D amplifiers yield high efficiency but are very noisy EMI-wise because of the switching of the MOSFETs, and this is usually corrected using LC filters. These are expensive and bulky. Master Slave Multi Carrier Modulation (MS_MCM) provides a means to reduce the amplitude of the switching frequency by employing multiple switching frequencies, hence distributing the energy across several frequencies, lowering the amplitude of the peaks at the cost of having to control intermodulation components arising from the use of different frequencies. Simulations using OrCAD show this is the case, however they also show a tendency of high THD. A prototype Class-D amplifier using the MS_MCM modulator is constructed and measurements reveal high THD, but it is inconclusive as to whether the high THD stems from the modulator or the layout of the PCB. A technology employing a similar strategy is called Spread-Spectrum by Maxim, but it uses one frequency that is dithered to reduce the peak.

Referat (Danish) Klasse D forstærkere har høj effektivitet, men de er meget støjende i forhold til EMI på grund af MOSFETs, der konstant switcher hurtigt. Dette er normalt løst ved brug af LC filtre, men disse er dyre og rummelige. Master Slave Multi Carrier Modulation (MS_MCM) kan være en metode til at reducere amplituden af switching frekvensen ved brug af flere switching frekvenser. På denne måde distribueres energien i en frekvens over flere frekvenser, så amplituden af peaks’ene bliver formindsket på bekostning af intermodulationskomponenter, der opstår på grund af de forskellige frekvenser. Simulationer med OrCAD viser dette, men de viser også en tendens til høj THD. En prototype af en klasse D forstærker med MS_MCM er konstrueret, og målinger viser en høj THD, men det er ikke bevist, om det skyldes MS_MCM eller PCB’ets layout. En teknologi, der bruger en lignende strategi er Spread-Spectrum, udviklet af Maxim, men den bruger en enkelt frekvens, der bliver spredt (dithered) for at reducere peak’en.


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1 Introduction First proposed sometimes in the 1950’ies, PWM technology has been in use since the 70’ies for switch mode power supplies. The past 10 years have seen substantial improvements of components and ICs, and today Class-D audio power amplifiers (using PWM technology) are a dominating factor in the audio market. On the technical side, the Class-D amplifiers have had a reputation of trading fidelity or audio quality for very high efficiency compared to other topologies. Today, this is not the case with Class-D amplifiers achieving a THD+N of less than 0.01%. However, there are still some inherent challenges that Class-D amplifiers must overcome, that its competitive topologies are not encumbered by. The advantages in using a Class-D amplifier by far exceed the drawbacks in most situations. One of the challenges that Class-D faces is its proneness to emit high frequency electromagnetic interference (EMI) due to the radically different approach of amplifying the audio signals in comparison with other topologies. This can be particularly problematic when the audio amplifier must work in the vicinity of other electronic devices – as the trend in the automobile market is pointing towards cramming more and more electronics in lesser space (DVDs, navigation, 7-channel audio etc.), the Class-D amplifier must be constantly evolved to be ‘quieter’ with respect to EMI. The traditional way of eliminating EMI is by using an output filter composed of an inductor and a capacitor. The inductor is a bulky and expensive component, and reducing the dependence of the inductor is a sure-fire way to reduce the cost of that 7-channel 300W car audio amplifier. This project investigates one possible solution using a topology called Master-Slave Multi Carrier Modulation. The theory of the Multi Carrier Modulation will first be presented along with actual simulation results using OrCAD. The other stages of the amplifier will also be presented along with a schematic and PCB layout of a prototype, however emphasis lies equally in both theory and practical aspects of the Class-D amplifier. Finally there will be conducted measurements of the amplifier’s properties and a few comments will be made comparing this solution with other ways of reducing EMI, particularly the new spread-spectrum technology. This project is carried out as a Bachelor project in Ørsted, Technical University of Denmark (DTU) with the help of supervisor prof. Michael A.E. Andersen (DTU) and Arnold Knott (with Harman/Becker Automotive Systems GmbH) and also with the kind help and assistance of Mikkel Høyerby (with Motorola). The motivation for this project is the fact that good amplifier design encompass many different fields of electronic engineering, it can be said to be interdisciplinary. A good design requires knowledge and skills within the following areas: digital electronics, analogue electronics, power electronics, signal analysis and filtering, controls and feedback, knowledge of electromagnetics and EMI, and practical implementation skills (PCB design etc.), measurements and error detection. Gaining knowledge in such a broad spectrum of fields is desirable in the Bachelor degree (and in any case) and facilitates specialization in a future Master programme.


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2 Theory of Modulation Today several different topologies of Class-D amplifiers exist, for instance self-oscillating types, GLIM, AIM, etc. The most straight-forward implementation (and conceptually easiest to understand) can be described as follows. Linear amplifiers drive the load with the MOSFETs in the linear or triode region. While this approach results in a very precise reproduction and amplification of the sound, a lot of energy is dissipated in the form of heat and the circuitry has a low efficiency due to biasing of the FETs. In Class-D, the MOSFETs operate in the saturation region instead of the linear or triode region, and they are either on or off. In the on state, the MOSFETs are conducting current with almost no voltage drop, resulting in power dissipation 0P UI W= . In the off state, the MOSFETs are like a closed switch, having an extremely high resistance and hence maximum voltage drop across the source and drain, which is why (almost) no current is flowing, and again there is no power dissipation. This is why some claim that theoretically Class-D has a 100% power efficiency. Only in the transition state between on and off there is a substantial (compared to on-off-states) loss of power. Otherwise almost all the power is dissipated in the load/speaker.

2.1 Basic PWM Modulation How can we produce sound when the MOSFETS are always either on or off? In the same sense that we can listen to the radio by tuning into frequencies well above the audible range, i.e. 100MHz, and still have sounds, we can also generate sound by turning power on/off to the speaker with some frequency. This is called modulation, and the theory of modulation says that if two signals are modulated, the resulting signal still contains information from both signals. Hence the 100MHz frequency still contains audio information, as well as the ‘information’ of the carrier frequency. In Class-D amplifiers, the modulation topology is called PWM for Pulse Width Modulation (sometimes also NADD or natural sampled two level single side modulation), and these pulses turn the MOSFETs on and off, the width of the pulse containing the audio information. The pulses are generated using a triangular carrier that is fed to a comparator along with the audio signal (called the reference signal). The comparator compares the two signals, and the output is high or low depending on which signal is the highest. This way a square wave signal is produced, and the duty-cycle (the high-time in relation to the period) determines ‘on average’ the audio signal. Below are diagrams explaining the operation of the Class-D amplifier.


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Figur 1 Schematic overview of the (half-bridge) Class-D amplifier.1

In order to retain the detailed information from the audio signal, the carrier signal frequency must be several orders of magnitude higher than the audio signal’s. Usually the carrier frequencies range from 200kHz to 500kHz. The MOSFETs, being switched by the output of the modulator, produce an amplified signal, but with minimum power being dissipated in the MOSFETs because of the inherent nature of the signal (either on or off). This is what makes Class-D amplifiers effective. At this point we understand why referring to Class-D amplifiers as being digital amplifiers is wrong, in fact they could hardly become more analogue (certainly all the components are analogue). At the very least, digitalization implies quantization in both time as well as voltage levels.

Figur 2 The modulator compares reference and carrier signals to produce PWM.2

The problems of the Class-D amplifier begin shortly after the MOSFETs. Actually the output of the MOSFETs could be connected directly to the speakers and we would have sound, but all the ‘information’ contained in the carrier frequency, that is, the high frequency energy, would be distributed to the speaker and dissipate power. Conducting wires to the load would also serve as antennas emitting high frequency radiation to the surroundings due to the high frequency content of the carrier. This will violate FCC regulations and ‘pollute the airwaves’. For these reasons an output filter is used. The output filter is essentially a low-pass filter taking care of ‘averaging’ or ‘smoothing’ the incoming signal. It consists of an inductor and a capacitor to ground, as seen in the schematic above (LF and CF). So, essentially, the input of the amplifier is first modulated, then amplified, and then ‘demodulated’ or low-pass filtered to get rid of all the high-frequency content from the modulation 1 Figure taken from Maxim Application Note AN3977. 2 Figure taken from Maxim Application Note AN3977.


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process. Usually, some of the output is fed back to the input either before or after the filter, but this is not shown in the diagram. Most open-loop configurations have a high THD+N, and hence feedback is mandatory. The output filter parts (inductor and capacitor) are by far the most expensive items in terms of cost and space. This project focuses on trying to alleviate the demands for the output filter by investigating a different modulator topology to the standard PWM.

2.2 Multi Carrier Modulation The idea behind using multiple carriers is to lower the switching frequency peaks that need to be attenuated by the filter stage simply by dividing the energy in one peak into two peaks (if two carriers are used). Theoretically, the amplitude of the peaks would be cut in half, but the energy in the entire spectrum would be contained. This would work well towards reducing EMI and the size of the output filter, since the amplitude of the peaks is the determining factor with regards to EMI. The current chapter will deal with the challenges with respect to the modulation technique. It is easy to imagine feeding in the audio signal into a number of comparators (two, in this project) that are each fed a carrier signal with a distinct frequency. But then the question arises, how do we re-collect the signals?

2.3 ORing and ANDing MCM For an MCM system with two comparators, one idea could be to use a simple decision rule such as an OR or an AND. Practically it would be quite easy to implement, but even easier to simulate. The algorithms for merging the two signals are shown below, where y is the output, x is the reference (audio) input, and car1 and car2 are the carriers, and this can be simulated using e.g. Matlab. Algorithm for ORing and ANDing MCM y = 1 if x < car1 | x < car2 y = 0 else y = 1 if x < car1 & x < car2 y = 0 else However, there are some problems using either one of the above options, as a simulation might show. First, there is a DC offset (positive for the ORed MCM and negative for the ANDed MCM). This DC offset is highly undesired, because it results in power dissipation in a later stage. Also, the harmonic distortion is not quite satisfactory. The DC offset presumably exists because of the statistical distribution of high and low output, which can be seen in the truth tables.


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Figur 3 Left: OR truth table. Right: AND truth table.

With a flat probability distribution (0’s, 1’s occurring equally random), there would be a higher average output with OR and lower average output with AND. A different binary rule that posses ‘even distribution’ among 0’s and 1’s is the XOR, however its truth table features 50% redundancy due to symmetry, and hence the output frequency is doubled with respect to the input, this renders it useless with regards to audio amplification.

2.4 Master-Slave MCM The Master-Slave method achieves a higher degree of linearity by using a combination of the two techniques above. The idea is to use a third ‘Master’ clock to switch evenly between the two outputs, the OR and the AND. This would eliminate the DC component in the output. However, it also presents the possibility of having a third switching frequency in the output, namely that of the Master clock. The schematic below shows such a possible implementation.

Figur 4 Schematic diagram of Master-Slave MCM.3

Basically, two different carriers are fed into two comparators, each comparator output goes to the AND and OR. Then, a different carrier (in the schematic above, the first carrier is reused, however it can be any carrier) chooses between the two outputs by feeding the two ANDs alternating 0’s and 1’s, acting as a selector. If the ANDs receive a 1, the output from the comparators will also pass, but if they receive a 0, they will block the output from the comparators. In conjunction with the last OR,

3 Figure by Arnold Knott (Harman/Becker Automotive Systems GmbH).


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this works like an alternating switch between the AND/OR, the frequency of the switch being determined by the Master clock. The two other carrier frequencies are then said to be Slaves.


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3 OrCAD Simulations The multi carrier modulation can be simulated in OrCAD using ideal or modelled electrical components such as comparators and flip flops to obtain the circuit that is described above. In the schematic below, the bottom op-amp U9 simulates a regular PWM output. The (ideal) op-amp is fed the carrier and reference (audio) signal, and with no feedback loop the op-amp acts as a comparator with maximum gain (in this case the supply voltages are GND and 5V). The master-slave multi carrier modulator consists of the two ideal op-amps that are each fed the same reference signal but different carrier signals (250kHz and 333kHz). Their outputs are then AND’ed and OR’ed using the flip flops and the square clock signal of 250kHz as described in the theory of the modulator. In the simulation, the output of the modulator is pulled up by resistor R1 to force the simulation to analogue mode instead of digital.

Figur 5 OrCAD simulation of MS_MCM modulator (top op-amps and flip-flops)

and ordinary PWM modulator (bottom op-amp). The simulation compares the output of the regular PWM modulator and the master slave multi carrier modulator. Below is a Fourier transform of the output. The reference (audio) signal is a mere 5kHz sinusoidal that can barely be seen in the graph all the way to the left, close to 0Hz. The red curve is the multi carrier output and the blue is the regular PWM output.


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Figur 6 Comparison of spectrum of NADD PWM (blue) and MS MCM PWM (red).

Both modulators contain the same information in the audio range as the reference signal (and this can be verified using more precise plots). The curve of the ordinary PWM shows the highest peak in 250kHz as expected from the switching or carrier frequency. The harmonics repeat at around 500kHz (notice the 5kHz shift in both directions caused by the input, no peak at exactly 500kHz) and at 750kHz (notice the two shifts and the middle peak in exactly 750kHz – square waves have only odd harmonics). All these are the peaks that are later attenuated by the output filter, and lowering the peaks before the output filter results in a lesser demand for a sizable output filter, hence saving cost and space. The curve of the multi carrier modulator exhibits some different properties. The highest peak occurs in 250kHz because of one of the carrier frequencies, however it is much lower than the same peak of the ordinary PWM about 2/3 of the amplitude (or 66%). The next peak is found at 332kHz, also from the fundamental carrier frequency, it has an amplitude of 1/3 (or 33%) of the 250kHz regular PWM peak. The sum of the amplitude of the two carrier peaks equals the amplitude of the single carrier peak. That means that the energy in the single frequency of the PWM equals the energy in the two frequencies of the MCM, and hence the peaks are lowered – the energy is distributed across two frequencies. Besides the two switching frequency peaks we observe the intermodulation components at f2 – f1 = 333kHz – 250kHz = 83kHz. However, because of the 5kHz input frequency, the intermodulation components are dispersed to 83kHz – 5kHz = 78kHz (marked on the graph) and 88kHz. It is


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essential that these frequencies be above the cut-off frequency of the output filter (usually at least 30kHz). These intermodulation components reappear in f2 + f1 = 583kHz. Table of peaks, red curve Peak no. Frequency Amplitude Cause / raison d’etré 1. 5kHz 0.75V Input signal components 2. 77.5kHz / 87.5kHz 163mV First intermodulation component

(IMC), f = f2 – f1 = 333kHz – 250kHz ≈ 82.5kHz. Shifted 5kHz from center frequency 82.5kHz due to input signal.

3. 167.5kHz 660mV 2*f1 – f2 = 167kHz 2*f2 – 2*f1 = 166kHz

4. 250kHz 2V Switching frequency f1 = 250kHz. 5. 332kHZ 1.6V Switching frequency f2 = 332kHz. 6. 416kHz 100mV 2*f2 – f1 = 416kHz (IMC)

3*f1 – f2 = 417kHz (IMC) 7. 500kHz 350mV First harmonic of switching frequency

f1. Again, shifted 5kHz due to input. 8. 582kHz 100mV f1 + f2 = 583kHz (IMC) 9. 664kHz 150mV First harmonic of switching frequency

f2. Again, shifted 5kHz due to input. 10. 750kHz 600mV 3*f2 – f1 = 749kHz (IMC) 11. 833kHz 660mV 2*f1 + f2 = 833kHz (IMC) Tabel 1 Peaks from MCM modulator, from left to right. Generally we can expect intermodulation components at any linear combination of the two switching frequencies. It can be noted that mathematically the Fourier representation allows negative frequencies (because of Eulers identity), and hence literally every linear combination can be created, for instance: 2*f2 – 3*f1 = 2*333kHz – 3*250kHz = -84kHz, which is peak no. 2. And again, 2*f2 – 4*f1 = -334kHz, which is peak no. 5, and 2*f2 – 5*f1 = 584kHz, which is peak no. 8. This has no real practical value. Noting the unexpected irregularity of the 250kHz peak being 2/3rd the value of the original, and the 333kHz peak being 1/3rd of the original, it is actually not that surprising when considering that the Master clock selecting the AND and OR modulator is also 250kHz. That means that basically there are three distinct switching frequencies in the system influencing the high frequency band, and not only two. A different simulation was made using non-ideal components (THS4221 op-amp) with a Master clock of 100kHz instead of 250kHz. Indeed, the energy in the 250kHz peak is then distributed across the three distinct frequencies! This result is even better than the distribution between two peaks.


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Figur 7 The blue NADD PWM features higher peaks than the red MS_MCM PWM.

Above is seen the high frequency content in the range of 20kHz to 40 MHz. It is easily seen that the MS-MCM PWM has lower peaks than the NADD PWM. (Unfortunately, the dependence of the 250kHz Master clock was not discovered in time to make a new testing prototype PCB). A different simulation for determining the THD of the modulator can be done. By injecting a DC in the input of the amplifier and measuring the average DC output, the gain for various inputs can be measured. Naturally, the gain of the modulator should be exactly 1 for all input levels. Using OrCADs parametric sweep function, one simulation for every DC value between 0V and 5V with intervals of 0.05V was made for the duration of 150us. The modulator might have start-up anomalies and the first 50us are removed, then the output is averaged over the entire period. Plotting input versus output should yield a straight line with the gain being the slope, the straighter the better – of course, the line cannot be 100% straight, that would mean unbelievably low THD. Then a linear regression is done in Matlab (using points between 1V and 4V because of non-linearity), and the error in percentage is also plotted. This is not a direct measure of THD, but the THD can be accurately calculated using this information. In the below top figure, the measurement is coloured blue, the regression is coloured red, the bottom figure displays the error in percentage.


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Figur 8 Top: DC input and output. Bottom: Percentage of error with respect to regression.

Open loop THD might be as low as 2%, unfortunately this simulation shows what might be a much worse THD, especially in the extremes (to the left, the curve continues to 200% most probably because the lower values cause higher percentages). This is not the THD curve, but the THD can be calculated accurately on the basis of this curve by simulating an injection of a sinusoid. Unfortunately this is beyond the scope of this project.


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4 Amplifier In this project we are also interested in testing the modulator in an amplifier system containing a half-bridge power stage, feedback circuitry, etc. This chapter revolves around the rest of the Class-D system. In general, the strictest requirement for an audio amplifier is a flat response in the audio band. A THD+N of 1% is audible, so lower THD is required, and of course as low as possible. Of course low power consumption is important in these global warming days as well as high output power, mostly for marketing reasons.

4.1 Conceptual Diagram As do most electrical systems, the amplifier as a whole consists of several blocks, each performing its own function. For a general overview the operation of the amplifier is described below.

Figur 9 Overview of the amplifer. Modulator (MOD, level shifter (LS), gate driver (GD), power stage (PS), output

filter (OF), feedback loop (FB) are the parts comprising a general Class-D amplifier, in this case the modulator is the MS_MCM.

Basically, the amplification of the audio signal occurs in the power stage (PS) where the MOSFETs reside. The power stage has the supply voltages of -30V and 30V with GND in the middle, so the output will also span these voltages. In order to turn the MOSFETs on quickly (low rise/fall times) and securely (avoiding shoot-through using dead-time), the power stage and MOSFETs are driven by a gate driver (GD). This gate driver is referenced to the lowest voltage -30V. The incoming audio signal on the other hand has the references of GND and +5V. Therefore the modulated audio signal must go through a level shifter (LS) so the span of the GND to 5V becomes -30V to -18V. When the amplified signal leaves the power stage, the high frequency content must be filtered before being output to the load. The feedback can be taken before or after the output filter (or both) and introduces error correction capabilities.

Figur 10 Synthesizing the carriers. The crystal connects to a clock divison scheme. The outputs are integrated.


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In the above diagram, the modulator includes the comparators that are fed the audio and carriers. The carriers must also be generated. It has been decided to use a single crystal and dividing that clock into two square wave clocks with different frequencies. This square wave must be integrated, resulting in a triangular carrier. The following chapters describes in detail the aspects of the amplifier.

4.2 Clock divider The topology of the modulator requires two carrier waves for comparison against the incoming audio signal, hence a pair of integrators are fed two clock signals to generate the triangular carriers. Class-D topologies usually make use of switching frequencies between 200kHz and 500kHz, and because of the intermodulation components being an inherent problem in using multi carriers, the carriers need to be spaced far from each other frequency wise to avoid intermodulation components in the audio band. The intermodulation components of two sinusoids are mathematically explained as a special case of amplitude modulation of a signal and a sinusoid resulting in spectral shifting or frequency shifting. Given a function f(t) and its Fourier transform F(ω), modulating that function by a real sinusoidal (as opposed to an imaginary sinusoidal, eg. ejωt) corresponds to shifting the frequency by ω0 of the Fourier transform F(ω) away from zero in both directions (implying negative frequencies are in use). Only real sinusoidal signals can be used for modulation, giving:4

( ) ( ) ( ) ( )( )0 0 01cos2

f t t F Fω ω ω ω ω⇔ − + +

In case of two sinusoids modulating each other, we have:

( ) ( ) ( ) ( )1 1cos cos cos cos2 2

A B A B A B⋅ = + + −

The former term on the right hand side is harmless – it means that energy is dissipated at the frequency A+B, and giving switching frequencies in the range 200kHz to 500kHz this energy lies well above the audio band and will also be attenuated by the output filter. The latter term is important, since it determines that some energy will be dissipated in the frequency A-B. It proves that the two frequencies must be interspaced by at least the audio band to avoid intermodulation components distorting the audio signal. However, the 2nd order output filter has a resonance frequency, and it would be desirable to have the intermodulation components above that frequency to avoid resonance, but also to attenuate the intermodulation components. Finally, the solution must be tractable from a practical electrical engineering point of view. Clock division circuitry is easily created using one crystal and a batch of flip-flops. D-flip-flops can be set up to halve the incoming frequency and maintain a duty-cycle of ½, which is important when

4 Mathematically the relation for frequency shifting is expressed as ( ) ( )0

0j tf t e Fω ω ω⇔ − where j is the

imaginary unit, t is time, and ω is angular frequency. For a more in-depth discussion refer to B.P. Lathi – Signal Processing & Linear Systems pp. 256 or any other text book on signals and linear systems.


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generating the triangle carrier. J-K-flip-flops can be combined to form a division of any rational number of practical use. The chosen solution requires a clock crystal of 2MHz which is divided down to 250kHz using 3 D-flip-flops and to 333kHz using two J-K-flip-flops and one D-flip-flop. The schematic from the OrCAD simulation is shown below:

Figur 11 Simulation of clock division circuitry using flip-flops. Three pull-up resistors force simulation into analogue mode and can be ignored when implementing. The pulse voltage source on the lower left corner simulates the 2MHz clock (which is achieved using a 2MHz crystal in conjunction with an inverter). The top three D-flip-flops have their inverted output connected to their D-input. Looking at the truth table for the D-flip-flop we realise that the flip-flop is cycling between the two states in the middle of the table. When Q is 0, then D is 1 (because Q-inverted is 1), and when Q is 1, then D is 0 (because Q-inverted is 0).

The two J-K-flip-flops in the bottom are a tad more complicated, however what is important is that they divide by 3, and depending on where the output is taken the achieved duty-cycle is .333 or .666, which corresponds to a multiplication of frequency by 1/3 or 2/3. In this case, none of the duty-cycles are acceptable, and hence the output signal is routed through another D-flip-flop to achieve a duty-cycle of .5, while halving the frequency once again. This way the 2MHz clock is divided by 6 resulting in a 333kHz clock.


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This is quite satisfactory, since the lower intermodulation component now lies in 333kHz – 250kHz = 83kHz outside the audio band and above the resonance frequency of the output filter. All of the above is verified by simulation. Below is a time-domain representation of the clock input and two outputs.

The flip-flops change state very quickly. The green curve is the 2MHz clock, the red curve is the 333kHz, and the blue is the 250kHz, as it is readily seen by which curve changes the fastest. Taking the Fourier-transform we can verify that the frequencies are correct.


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The green curve is the 2MHz input, and the blue and red curves are the outputs of 250kHz and 333kHz. There are a lot of harmonics due to the square wave nature of the clock.

4.3 Integrators The integrators featured are practically standard inverting integrators (or Miller intergrators) with some biasing circuitry. Many textbooks5 on analogue electronics feature a detailed discussion on these integrators. For the sake of completeness, I will also venture a short discussion on this topic. The inverting integrator resembles a lot the inverting closed-loop op-amp configuration, but the resistor in the feedback path is replaced by a capacitor. The figure below shows the configuration. Since the virtual ground appears in the negative input node, the current iI = vI/R through the resistor

charges the capacitor by the amount ( ) ( )2

1

1 t

t

v t i dC

τ τ= ∫ . Since one end of the capacitor is always at

ground, the voltage at the other end must be pushed below ground when the capacitor is charged – or, the output voltage vO equals -vC. By substituting i(t) in the equation, we arrive at the formula:

5 An excellent textbook is the Sedra/Smith – Microelectronic Circuits, it contains a discussion on inverting integrators on page 107.


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( ) ( )2

1

1 t

O It

v t v t dtRC

= − ∫

From the equation it is seen that the output voltage is proportional to the integral of the input voltage. The product RC is referred to as the integrator time-constant. The negative sign is the reason of the inversion.

Figur 12 The Miller integrator.

Now, the problem with this particular integrator is the ability of the capacitor to become fully charged and hence the circuit is ‘saturated’. This happens if there is a DC component in the incoming signal, because the capacitor acts as an open circuit DC-wise, and hence there is no feedback loop (or the DC component saturates the capacitor). The op-amp will ramp up the output until the supply rail is reached (which rail depends on the polarity of the DC). A possible solution would be to include a resistor in parallel with the capacitor, but that would not be advised because of non-linearity using a low resistance and high DC offset using a high resistance (looking at the resistor going to infinity, the close we get to the circuit above, when the resistance is infinitely high as in an open circuit). Another solution is to ‘counteract’ the DC at the input, which is done by feeding the DC at the output back to the positive terminal. This is done by adding another integrator at the output with a high time constant, the output of that integrator being fed into the first integrator (see figure below). The resister R3 is added to provide a phase margin to avoid stability issues, and the 2.5V DC offset is to center the output. Another capacitor is added to improve linearity.


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Figur 13 Schematic of integrator with DC tracking.

The integrator needs a short period of time to establish stability. This start-up time is shown in the plot below.

Figur 14 Integrator stabilized after about 3ms.

Keeping the run-time of the simulation for a prolonged period of time we see that the integrator is now stable. We also verify the linearity of the generated triangle carrier. A very low-tech way of doing so is to use a graphics program (e.g. MS Paint) to draw a straight line for comparison.


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Figur 15 Comparing the carrier (red) with a straight line (black) we see that the carrier is linear.

The linearity of the triangle carrier is important, because bad linearity introduces THD.

4.4 Level Shifter The supply voltages of the comparator are 0V and 5V, and hence the comparator output will also be either 0V or 5V. However, the gate driver receiving the PWM signal is referenced to -30V (as its ground) and -18V (as its VCC), and hence the PWM signal needs to be referenced to these voltages as well. The level shifter accomplishes this task.

Figur 16 Level shifter circuitry feeds the gate driver with -30V referenced PWM signal.


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The mode of operation of the level shifter can be described as follows. The incoming PWM signal is fed into the first BJT (on the left), that is connected to a resistor and +5V in series. When the PWM signal is low, there is a voltage drop of 5V across that resistor, and thus a current runs through that resistor and the BJT. The signal is now inverted, since there is a current running when the PWM signal is low. The current enters the next BJT, and that pulls down the node above the BJT to -30V. Now the PWM signal is inverted twice, the net result is no inversion - when the PWM signal is 0V, the output is -30V. When the PWM signal goes high, there is no voltage drop across the first resistor, and there is no current running through the first BJT. The second BJT is turned off, and the output node is pulled up to -18V. The net result is, when the PWM signal is 5V, the output of the level shifter is -18V. This is also verified by simulation. Below is seen the schematic for the simulation and the output.

Figur 17 Simulation schematic of level shifter.

Figur 18 Output of simulation. The level shifter shifts the incoming signal from 0V to -40V.


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The green curve is the input between 0V and 5V, and the blue curve is the output between -40V and -28V. The simulation used 40V, however this project utilizes only 30V to simplify the design.

4.5 Gate Driver IRS20124 The half-bridge power stage containing the two mosfets needs a gate driver in order to ensure high rise/fall-times, typically 25ns6 (quick calculations show the driver must supply about .3A7). After the modulated audio signal has been level shifted, it is referenced to the negative supply voltage –V which is -30V and to the positive supply of the gate driver of -18V (hence the gate driver receives 12V supply). The negative supply voltage –V is the ground of the gate driver. The input of the gate driver has to have a maximum of 1.2V above ground (-28.8V) for a logic zero and a minimum of 2.5V above ground (-27.5V) for a logic one (values found in datasheet), so the input signal by far exceeds the requirements with its 12V span. The IRS20124 gate driver was chosen mainly because the used topology was a success in a different project.8

Figur 19 Gate driver IC, IRS20124.

The IRS20124 gate driver features internal inversion of the input signal, over-current detection and shut-down for protection of the MOSFETs, resistor-programmable dead-time in steps of 10ns with the smallest being 15ns, and generally a robust design with respect to noise. However, an external bootstrap circuit must be supplied.

4.5.1 Low-side Driver The low-side driver delivers current to the low-side MOSFET through the LO-pin (low-out, pin 7), using the supply voltage of VCC (pin 8) and supply return COM (pin 6). The COM connection is grounded (-30V), as is the low-side MOSFET. The driver’s output is 180 degrees out of phase with the input due to the internal inversion (only one input is needed), so when the input is high, the high-side MOSFET is on and the low-side MOSFET is off, and vice versa.

6 Taken from datasheet of IRS20124, page 3, tr. 7 Taken from datasheet of FDD3672 p.2: Gate-to-source charge Qgs = 8.6nC, hence I = dQ/dt = 8.6nC/25ns = 0.3A. Another way: Input capacitance CISS = 1710pF and VGS ≈ 6V, hence I = C*dVGS/dt = 1710pF*6V/25ns = 0.41A. 8 Jacob Lillie & Henrik Schneider – Design of Self Oscillating Class-D Amplifier


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4.5.2 High-side Driver and Bootstrap Circuitry The high-side driver delivers current to the high-side MOSFET through the HO (high-out, pin 11), using a floating supply with a bootstrap circuit. The supply input for the high-side driver is VB (hot, pin 12) and VS (cold, pin 10).

Figur 20 Gate driver with bootstrap circuitry (C12GD and D1GD).

The bootstrap circuitry is required since the supply voltage for the high-side driver must exceed the supply rail of VCC when the high-side driver is on. This is because the supply return is connected to the source of the MOSFET which is also the input of the inductor (the switching node). When the MOSFET has to be turned on, the switching node and VS is +V, 60V above the ground of the gate driver(!), and VB needs to be 12V above VS. The bootstrap circuit provides the additional 12V. The bootstrap circuit (sometimes also called a charge pump) consists only of a capacitor and a diode. In the above schematic, the bootstrap circuit is C12GD and D1GD. The operation of the bootstrap circuit can be described in the following way. When the gate driver is first enabled, VS will be grounded to -30V and the bootstrap capacitor will be charged to 12V through the diode connected to -18V. When the PWM signal goes high, the high-side driver turns on the high-side FET by injecting charge from the bootstrap capacitor into the gate of the FET. When the FET is turned on, VS finds itself at a voltage of +V, and the bootstrap capacitor simply ‘drags’ or forces the voltage of VB to become +V + VC12GD (because the capacitor holds the voltage across it). Now the diode prevents the capacitor to discharge from the VB node to -18V. When the PWM signal goes low again, the switching node or VS is tied to ground, the VB node follows down, and the bootstrap capacitor is recharged through the diode. Hence the supply of the high-side driver is called a floating supply.9

4.5.3 Programmable dead-time IRS20124 features selectable dead-time through the DT/SD pin. Too short a dead-time may lead to short-circuiting the MOSFETs (if the fall-time is too long due to high gate charge) causing device 9 More information pertaining to bootstrap circuitry can be found on datasheet of FAN53418 p. 8, also Sanjaya Maniktala - Switching Power Supplies A to Z p. 193.


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failure due to overheating. Too long a dead-time results in poor linearity of the PWM signal and hence a decrease in fidelity and sound quality (more distortion). For the IRS20124, the shortest dead-time available is 15ns.

Figur 21 Effective dead-time protects the MOSFETs from short-circuit condition. Figure taken from datasheet.

Programming the desired dead-time is achieved as a voltage division between VCC and GND which is measured in the DT/SD pin, as is shown in the datasheet on page 21. Using resistor values of 5.6k and 4.7k the dead-time is set up to 35ns, which should be sufficient to protect the MOSFETs.

4.6 Active Turn-off The active turn-off circuitry facilitates turn-off of the MOSFET. For the MOSFET to be turned on, the gate driver has to inject a high current in order to charge the gate-source capacitance (since i(t) = C*dv/dt) fast enough and make the gate-source voltage high. This charging current is directed through the 4R7 resistor. Because of the same gate-source capacitance, active turn-off circuitry is used to turn off the MOSFET fast.

Figur 22 Active turn-off circuitry turns off the MOSFET fast.

When the MOSFET has been turned on, the gate of the MOSFET is at high voltage, and so is the source that is connected to the switch node (input of inductor). The BJT is off, because its base and collector are at the same voltages.


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When the gate driver pulls down the voltage, the base of the BJT is lower than the collector, and hence the BJT is turned on. This allows current stored in the gate-source capacitance to flow through the 1 ohm resistor. The current also flows through the diode and the 4R7 resistor, and since the 1R and 4R7 resistors are in parallel (they have the same voltages across them, since the HO output is pulled down to VS) the total resistance is much less than 1R, and more current can flow out. The 4R7 resistor was added in the first place to control ringing, because the inductance of the wires and the gate-source capacitance can create a condition for ringing.

4.7 Output Filter The output filter comprises an inductor and a capacitor and is essentially a lowpass filter. As mentioned before, it takes care of lowering the high frequency peaks from the carriers. This would result in ‘averaging’ the incoming PWM signal.

Figur 23 Schematic, output filter.

When the high-side FET is conducting, the low-side FET must be off, and current goes from the supply voltage through the inductor. When the low-side FET is conducting, the high-side FET must be off, and the current goes from the inductor to ground. The inductor consists of a T94-2 metal powder toroidal core from Micrometal with 8.4nH/turn2 and a 1mmØ wire. To obtain a 15uH inductor, we calculate the no. of turns:

2

15 428.4 /L

L uHN turnsA nH turn

= = = .

The cut-off frequency for such an LC second order low pass filer is 1 412cf kHz

LCπ= = when

choosing the values of 15uH and 1uF. This leaves some ‘headroom’ for the audio band to stay flat. The solution seemed to work well in a different project which is why it is used here as well.


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4.8 Feedback Loop Feedback is a very broad and complex topic and was not the focus of attention in this project. It was first decided to take feedback from before and after the output filter, but the feedback from after the output filter was dropped at a later stage for complexity reasons. The feedback from before the output filter is in general supposed to be filtered a bit by RC filtration, then fed into a differential amplifier along with the audio signal resulting in the output being an error signal. The error signal should be integrated and then fed into the modulator. Below is seen the feedback circuitry that was utilized.

Figur 24 Feedback circuitry, the first op-amp being the differential amplifier and the second performing integration.

The forward gain is the ratio between the span of the triangle carriers and the span of the supply voltages. When testing, the supply voltages were set at +-20V, and the triangle carriers were 4V peak-peak, and hence there is a gain of 10. This means that the feedback loop must reduce the signal by 10 times, and this is done with R1FB/R4FB = 10, and hence R1FB = 10k. The differential amplifier must see the same impedances at the input terminals ‘looking out’, so R4, R6, and R8 provides that symmetry along with biasing the incoming signal with 2.5V. The integrator must have a crossover frequency of about 40kHz. The transfer function is 1/sRC, and at the frequency of 40kHz this must be 0db, that is:

1 1 10 3.970 2 40

dB RC ssRC s dB kHz

µπ

= ⇔ = = =⋅

.

We can choose the component values of 1nF and 3.9k. In a late stage of the project, it was discovered that the feedback topology employed inadvertently caused positive feedback. The reason is that since the rest of the amplifier is non-inverting, the feedback topology used must only have one inversion (or odd no. of inversions), otherwise the error will be amplified. The differential amplifier provides one inversion, since feedback input is fed into the negative terminal, and the output is then vo = A(v+ - v-), and hence the difference is inverted in polarity. The next inversion happens in the integrator, being a Miller integrator it is inherently inverting. That means that if the feedback signal changes in one direction, the input of the modulator goes to the same direction, and the whole system will be locked in one polarity. Employing feedback was altogether abandoned at a late stage in the project.


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4.9 2.5V Biasing Some of the components will need 2.5V biasing for centring the signals between 0V and 5V. This biasing is achieved with the LMV431B regulator. It is basically an op-amp with an internal reference of 1.24V. It will try to make the reference terminal 1.24V by drawing current.

Figur 25 Left: Schematic of biasing. Right: Diagram of LMV431.10

Assuming the reference node is at 1.24V, we know there is a fixed current through R1BIAS. The same current passes R2BIAS, also a 1k1 resistor, and hence the cathode node is at 2*1.24V = 2.48V. The 10n capacitor decouples the output.

10 Right diagram taken from datasheet.


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5 PCB Layout PCB design might not seem like such an important part of the engineering work. Certainly, the innovation and development of new topologies and ICs are getting all of the attention. With respect to the final product, however, a bad PCB layout can turn even the most stable components to oversensitive parts, cause ringing, instability, and ultimately even critical events such as switch failure and device failure. Certainly the above does not apply to the same extent for low frequency analogue designs or low voltage digital designs as it does for switching regulators or Class-D amplifiers (these are closely related in many respects). The result is that ordinary PCB layout persons might not be qualified to route the PCB of high-power switching devices, and it would be up to the designer to handle this task. It is certainly no option to let the autorouter of your favourite layout program do it!

5.1 Important Measures When Laying Out PCB It is of utmost importance to understand the flow of power-related currents in the circuit and the effect of the parasitic inductance. The traces where the current changes both rapidly and from low to high (that is, high dI/dt) are subject to unfavourable conditions due to the parasitic inductance. These are the critical traces, and we will point them out in a short while.

Inductance (parasitic or otherwise) obeys the law dIV Ldt

= , where L is the inductance in henri [H].

What must be understood is that the V in the above equation is ‘induced voltage’ across the inductor that opposes sudden change in current. There can be no current ‘jumps’ or discontinuities across an inductor, just as well as there can be no voltage discontinuities across a capacitor (the ‘dual’ of the inductor, in the sense that the equations are the same, but with V and I interchanged). Suppose an inductor is connected to a DC current source of some value (and in parallel with a resistor), the current through the inductor will not rise instantly, but rather exponentially with the time constant τ = L/R from zero to the DC value. In the beginning, all current goes through the resistor, in steady-state condition, all current goes through the inductor. The inductor is simply a coil, a piece of wounded wire with hardly any resistance, hence it is intuitively difficult to understand that it can hold any voltage at all.11 The V from the above equation is ‘warding off’ the change in current and hence decreases exponentially as the current increases. This ‘induced voltage’ is the same voltage that is known as voltage spikes across traces with high dI/dt. Generally, 1cm of trace contains about 10nH parasitic inductance. In the power stage of the amplifier it is desirable to have the currents change as fast as possible, and therefore the parasitic inductance in the traces must be lowered as much as possible (since inductance wards off change in

11 As a side note, it was equally tantalizing how a capacitor could conduct current when the voltage across it changed, since the capacitor consists of two metal plates and an insulator(!). Duality principle reveals the induced voltage of the inductor as a dual to the conducted current of the capacitor. It boils down to the fact that current and magnetic fields are related, and charge and electric fields are related as well, and the energy is stored and transported by means of these fields, but that is outside the scope of this article.


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current). The induced voltage spikes can appear at the input and output of devices and cause problems for ICs and other components. Induced voltage is not a problem with digital circuitry, since the typical output current can be 10mA, but traces in the power stage can easily reach a couple of amps.

The parasitic inductance of a PCB trace is given12 as 22 ln 0.5 0.2235l wL l nHw l

⎛ ⎞⎛ ⎞= + +⎜ ⎟⎜ ⎟⎝ ⎠⎝ ⎠, and this

logarithmic relation shows that halving the length of the trace results in halving the inductance, but the width needs to be increased almost 10 times to achieve the same effect. Therefore the critical PCB traces must be kept short! This is the reason for the components in the power stage to be kept closely together. Below the critical traces are outlined, and these are the traces that require special attention and must be kept short.

Figur 26 Critical PCB traces are the traces where the dI/dt is high.

First off, the two MOSFETs must be kept close together, and they are conducting a lot of current, so they must not only be kept short because of parasitic inductance, but also wide to dissipate the generated heat due to resistance in the traces. Of course, the MOSFETs benefit from being situated closely to their current source (in this case, the +-30V input current). The figure shows a long line through the two MOSFETs, but the implication is not that one current is running through them both, since this only happens in shoot-through conditions which is dangerous for the components an very undesirable. When the high-side MOSFET is conducting, the current ramps up linearly in the inductor, but when the low-side MOSFET takes over, the current through the high-side MOSFET must be stopped instantly, and the current through the low-side MOSFET must be started instantly. The current through the inductor just ramps linearly up and down, the inductor allows no discontinuities in the current, and therefore the inductor is never in a critical trace.

12 In Switching Power Supplies A to Z, page 243


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Second, the traces for the low-side and high-side driver that charge the gate-capacitance of the MOSFETs must also be kept short. For the high-side driver, this includes the bootstrap capacitor that charges the high-side MOSFET. Also, the traces in the discharging circuitry, that is, the active turn-off, must be kept short to minimize parasitic inductance. Another way of minimizing the stray inductance is by paralleling the forward and return current in the current loop. Inductance exists because of energy stored in magnetic fields, and by having forward and return currents cancelling out each other’s magnetic fields, the inductance is greatly reduced. This has been done to some extent in the case of the bootstrap capacitor. However if a ground plane is used on the opposite side, then the return path automatically ‘images’ the forward current. This is due to the current searching for the path of least impedance, which is not always a straight line, especially in the case of higher frequencies. This is why it is important to retain an intact ground plane, not cutting into it. This way we allow the current to find that path. Even with a large ground plane absorbing a lot of the noise, there is a critical signal path that must be paid close attention to, and that is the feedback loop. Of course this feedback loop must be kept short in order to minimize potential noise interference. Most importantly though is to keep the feedback loop away from noise components and traces (especially critical traces), and it can even be desired to make the feedback loop longer to route it further away from these noise sources. Some more general advices are making sure that the decoupling capacitors are to be placed closely to the ICs that they decouple and the ground connection. Generally, capacitors must be placed ‘strategically’ in the current path, which is very important in the output filter for instance. The best type of bypassing must be achieved, as the figure below suggests.

Figur 27 A bypassing or decoupling capacitor strategically in place.

If possible, thermal vias under ICs can transfer heat away to other layers. However, when prototyping, it is not always possible to create professional vias underneath components.

5.2 The Prototype Laying out a PCB is always a tedious task of trail and error. At first, there are a lot of components in no particular order, and the airwires can be very confusing. It helps breaking down the schematic


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into several blocks and trying to decide on a placement of each block in the overall picture, layout out a block at a time. In the schematic, wires can be crossed as much as desired without ‘short circuiting’ or in any way affecting the performance. When trying to layout a PCB, this is not possible, and sometimes it can be practical to change the schematic instead of using vias to the ground plane. Some special cases that were encountered in this project are shown here. The clock divider: Laying out the clock divider presented a problem since there are a lot of wires crossing on the diagram, and the pins are of course connected differently on the ICs themselves, not to mention the power supply needed. Consider the following two schematics below:

Figur 28 Two implementations of clock division, the bottom turns out to be more practical. The above schematic is the conceptual way of setting up a D-type flip-flop as a T-type (toggle) flip-flop, each time the clock passes, the frequency is halved. However, the result of the bottom schematic is exactly the same, although 3 pins less are used and no lines cross. In this case it made a huge difference when laying out the clock divider. Of course it does not mean that each time lines in the schematic cross, they will have to cross in the layout (there is also the possibility of laying traces beneath the components). The integrator: It turned out to be very practical to switch the gates of the op-amps. The THS4222 comes in a package containing two op-amps, and the pins were situated in such a way that it was useful to switch the two gates/devices. This will become much more apparent when examining the modulator. The modulator: Implemented using quad ANDs and quad ORs (four devices in a package) and hex NOTs (six in a package), the different gates/devices where carefully chosen to be able to interconnect.


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Figur 29 It is not always possible to avoid cutting into the ground.

However, it is not always possible to avoid cutting into the ground plane. When doing so, we must ensure cutting the shortest possible route. The end result of the prototype is shown below.

Figur 30 Final PCB layout of the prototype.

In the bottom left corner is the clock crystal attached to the division circuitry (three ICs in a row, market CLOCK). The two outputs of the division are directed into the integrators (market INT1 and INT2), and from there on to the comparators (COMP1, COMP2), and the MS_MCM modulator


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(MOD). To the right of the modulator is some biasing circuitry used for the integrators, and to the right again, there are voltage regulators of 5V (for logic ICs) and 12V (for gate driver). The signal from the modulator is then routed to the level shifter (marked LS) located a bit above the modulator. The output is then referred to the gate driver circuitry (marked GD), located above, and then the output power stage with the two MOSFETs (they should be easy to spot). Above the MOSFETs there is room for a toroidal inductor, to the left there is the output capacitor, and then the output for the speakers. Also, there is the feedback loop (marked FB), that is close to the amplifier input. It can be seen that the feedback components are kept well away from the noisy output stage. However, the RC filter R17FB and C1FB as well as R18FB and C2FB should have been situated much closer to the toroid inductor in order to avoid having the long feedback trance emit high frequency content, and this was found later on to create a lot of noise at the feedback loop. When testing, it was also found that the first hex inverter for the clock did not receive any supplies and that the pins (reference, anode) of the LMV431 providing 2.5V biasing have been incidentally swapped. This as well as other layout-related problems could be corrected in future prototypes. Below is a picture of the hardware.

Figur 31 The amplifier. Below the amplifier are two 1000uF electrolytics.


35

6 Measurements After verifying the operation of the circuit, the first set of measurements taken with the Audio Precision equipment was of the modulator THD (open loop). Unfortunately, the modulator by itself displayed very high THD, typically 5-10%. Below is the graph showing THD in the audible range.

Figur 32 Percent THD vs. dBV.

Even for an open loop configuration without the correcting benefits of the feedback system, this THD is unreasonably high. The accuracy of the test equipment was also verified and no fault or error was found. The output of the comparators was not found to be fully satisfactory. The rise time was influenced by some ringing at 3V before ramping up to 5V, but this should not influence the flip flops too much. The PCB layout is unlikely to influence the performance of the modulator because of the low signal levels. The high rise on the left at about 2.5dBV is most likely because the signal amplitude exceeds the carrier amplitude. Below is another test that shows the very high harmonic distortion. The input is injected with a 1kHz sinusoid, and an FFT of the output is displayed in the audible range vs. dBA. The red curve with the noise floor at about -60dB contains a very high distortion due to a faulty comparator, and the blue curve shows that the noise and the distorted harmonics dropped 20dB after replacing the faulty comparator.


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Figur 33 FFT of the output, when injected with 1kHz sine. Note the high harmonic distortion. Red curve was taken

with a faulty comparator. Assembling the power stage and output filter, THD measurements are once again performed, however not with much interesting results. There is some resemblance in the characteristics. The same high rise at the high input could suggest clipping or the modulator’s problem from before. Note the scale going up to 22.5dBV (because the output power is much greater with the power stage).

Figur 34 THD+N measured with power stage, dBV vs. %.

Taking a look at the signal going to the output, we do realize that the output filter is not performing its job very well. There is quite the amount of high frequency content. However, setting up the Audio Precision equipment to filter away the injected input of 1kHz and displaying the result on the oscilloscope, we realize that this ‘error’ signal also contains lower frequency components.


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Figur 35 Yellow: Output signal from amplifier (open loop). Red: 'Error' signal.

Looking at the general curvature of the red graph, we see that there is a sinusoidal form with the peaks 1, 4, 6 forming the first period, and 6, 7, 8, forming another period. From the top peak 1 to the bottom peak after 12 we can count 4 high peaks and 4 low peaks, that is, 4 periods. This ranges about 8x2ms = 16ms. The frequency can be easily calculated to 250Hz, and it can also be seen to be roughly twice the input frequency of 100Hz. Another component with a higher frequency can be made out from the red graph, the peaks 1, 2, 3, making one period, 3, 4, 5, another period, 5, between 5 and 6, and 6, marking a third period. We assume there are 18 periods over 8ms, which yields a frequency of 2.25kHz. These two frequencies are currently unaccountable. Not surprisingly, there is also high frequency noise, most likely from the switching frequencies. A long time was spent trying to make the feedback circuitry work, but having measurements with feedback was abandoned in the end. It was then decided to try short-cutting the MCM-modulator and using only the output of one comparator (achieving an NADD PWM), then taking measurements of THD. This could reveal whether the MCM modulator or the layout of the power stage itself is to blame for high THD. Unfortunately, only one set of measurements (FFT of 1kHz signal) was made before an error with the 2.5V biasing circuitry appeared and ruined the carrier signals, offset at the audio input and more. Since it was not possible to correct for that error, these measurements were also abandoned.


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7 Results and Conclusions The last set of measurements from the 1kHz FFT taken with the power stage on did not show a significant improvement. This could suggest that the power stage is to blame for the high THD, and another measurement with the power stage off is desirable. Also, when the power stage was on, at one point it seemed that the input signal was being heavily corrupted by switching noise stemming from either the feedback loop or the power stage, but no measurements have been taken to confirm this. The conclusions are not unambiguous. The first set of simulations using OrCAD has shown no sign of significant THD, but the second set (DC analysis) point indirectly towards an amount of THD. Because of difficulty with performing measurements and problems with the circuitry, not all the desired measurements were made. The measurements that were made were pointing towards a very high degree of THD, and the measurements of the modulator without the other stages corroborate this. However, it is interesting to note that the Spread-Spectrum technology employed by Maxim-Dallas is conceptually close to the MCM and does work.

8 Outlook The MS_MCM tries to minimize the amplitude of the switching frequency peaks by dividing the energy in one peak into several peaks. Conceptually, this is reminiscent of Spread-Spectrum technology by Maxim, also sometimes referred to as dithering.

Figur 36 Spread-spectrum clock spreads the clock frequency over a range of frequencies.

Dithering (varying) the frequency just a couple of percent, the energy in the peak is spread randomly over the spectrum as shown in the figure above. Using a spread-spectrum clock is possible in Class-D amplifiers because the duty-cycle is maintained even though the frequency is varied. A disadvantage is the intermodulation components if the spectrum is varied too much, and this is uncontrollable with spread-spectrum, where it is fully controllable with the MCM. Maxim solves this problem using noise shaping filters. In essence, these two technologies are much alike, and if the spread-spectrum yields good results and low THD, there are no apparent reasons why MCM should not be able to do so.


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9 References Class D Amplifiers: Fundamentals of Operation and Recent Developments (Maxim) http://pdfserv.maxim-ic.com/en/an/AN3977.pdf Spread-Spectrum Clock (Maxim) http://pdfserv.maxim-ic.com/en/an/AN3512.pdf Proper Layout and Component Selection Controls EMI (Maxim) http://pdfserv.maxim-ic.com/en/an/AN716.pdf Maniktala, Sanjaya, “Switching Power Supplies A to Z” Newnes, 2006, ISBN 13: 978-0-7506-7970-1 Sedra, Adel S., Smith, Kenneth C., ”Microelectronic Circuits, fifth edition” Oxford University Press, 2004, ISBN: 0-19-514252-7 Lathi, B.P., “Signal Processing & Linear Systems” Oxford University Press, 1998, ISBN: 0-19-521917-1


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10 Appendix This oscilloscope shot is to verify that the clock division circuitry performs well. The bottom is the input clock of 2MHz, the two upper clocks are 333kHz and 250kHz.

This oscilloscope shot shows the triangle carrier.

www.oersted.dtu.dk Ørsted·DTU Power Electronics Group Technical University of Denmark Ørsteds Plads Building 348 DK-2800 Kgs. Lyngby Denmark Tel: (+45) 45 25 38 00 Fax: (+45) 45 93 16 34 E-mail: [email protected]

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