Much of the Computer’s Architecture / Organization

8/14/2019 Much of the Computers Architecture / Organization

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EE 4504 Section 7 1

EE 4504Computer Organization

Section 7The Instruction Set

EE 4504 Section 7 2

Overview

Much of the computers architecture / organization is hidden from a HLLprogrammer In the abstract sense, the programmer should

not care what the underlying architecture reallyis

The instruction set is the boundary wherethe computer designer and the computerprogrammer can view the same machineThus, an examination of the instruction setgoes a long way to explaining thecomputers CPU itself This section investigates the design of theinstruction set and the impact of the set onthe design of the overall computer systemReadings: Chapters 9 and 10


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EE 4504 Section 7 3

Instruction content

Each instruction must contain 4 basicpieces of information Operation code: specifies the operation to be

performed, expressed as a binary code Source operand references: operands required

for the instruction are specified Result reference: where should the result of the

operation be placed? Next instruction reference: how / where is the

next instruction to be found In most cases, this is not explicitly stated in

the instruction Next instruction is the one that logically

follows the current one in the program(sequential / linear progression through theprogram)

EE 4504 Section 7 4

Instruction types

An instruction set should be functionallycomplete Permit the user to formulate any high-level data

processing task

Five categories of instructions

Arithmetic operations Logic operations Data movement (internal to the system) I/O (data movements between the computer and

external devices) Control operations

Instruction sets have been designed with Small numbers of instructions (1) Hundreds of instructions Trend today is to use enough to get the job

done well (more on this in the RISC/CISCdiscussions to come)


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EE 4504 Section 7 5

Until the 1980s, the trend was to constructmore and more complex instruction setscontaining hundreds of instructions andvariationsIntent was to provide mechanisms to

bridge the semantic gap , the difference inhigh and low level functioning of thecomputer Reconcile the views of the HLL programmer

and the assembly level programmer Provide a diverse set of instructions in an

attempt to match the programming style of HLL Permit the compiler to bridge the gap with a

single instruction rather than synthesizing aseries of instructions

Did not always have the desired impact

EE 4504 Section 7 6

Wulff asserts that compiler writers mightmake the better architects Have had to deal with poor architecture

decisions

Wulffs attributes of a good instruction set

Complete: be able to construct a machine-levelprogram to evaluate any computable function Efficient: frequently performed functions

should be done quickly with few instructions Regular and complete classes of instructions:

provide logical set of operations Orthogonal: define instructions, data types, and

addressing independently

Additional attribute: Compatible: with existing H/W and S/W in a

product line


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EE 4504 Section 7 7

Addresses in an Instruction

In a typical arithmetic or logicalinstruction, 3 addresses are required -- 2operands and a resultThese addresses can be explicitly given orimplied by the instruction

3 address instructions Both operands and the destination for the result

are explicitly contained in the instruction word Example: X = Y + Z With memory speeds (due to caching)

approaching the speed of the processor, thisgives a high degree of flexibility to thecompiler

Avoid the hassles of keeping items in theregister set -- use memory as one large setof registers

This format is rarely used due to the length of addresses themselves and the resulting length of the instruction words

EE 4504 Section 7 8

2 address instructions One of the addresses is used to specify both an

operand and the result location Example: X = X + Y Very common in instruction sets

1 address instructions Two addresses are implied in the instruction Traditional accumulator-based operations Example: Acc = Acc + X

0 address instructions All addresses are implied, as in register-based

operations Example: TBA (transfer register B to A)

Stack-based operations All operations are based on the use of a

stack in memory to store operands Interact with the stack using push and pop

operations


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EE 4504 Section 7 9

Trade off: Fewer addresses in theinstruction results in More primitive instructions Less complex CPU Instructions with shorter length

More total instructions in a program Longer, more complex programs Longer execution times

Consider

Y = (A-B) / (C+D*E)

3 addressSUB Y,A,BMUL T,D,E

ADD T,T,CDIV Y,Y,T

EE 4504 Section 7 10

2 addressMOV Y,ASUB Y,BMOV T,DMUL T,EADD T,CDIV Y,T

1 addressLOAD DMUL EADD CSTORE YLOAD ASUB BDIV YSTORE Y


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0 address Convert to postfix (reverse Polish) notation

Y = AB-CDE*+/

PUSH APUSH B

SUBPUSH CPUSH DPUSH EMULADDDIVPOP Y


Types of Operations


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EE 4504 Section 7 13 EE 4504 Section 7 14

Control Operations

Common operations Branch

Conditional or unconditional Jump to another part of the program for the

next instruction by modifying the programcounter

Skip Useful in loop control

ISZ R1BRA TOP

Subroutine call / return Jump to routine with the expectation of

returning and resuming operation at thenext instruction

Must preserve the address of the nextinstruction (the return address)

Store in a register or memory locationStore as part of the subroutine itself Store on the stack


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Parameters can be passed to / from thesubroutine in similar ways

Use of the stack is the only reentrantapproach

Each called subroutine is allocated a stack frame on the stack

Contains variable to be passedReturn addressResults to be returned


Endian Wars

Architects must specify how data is stored(its byte ordering) in memory and registers This leads to the endian wars

Big endian Little endian

Consider the hex value $12345678 andhow it is stored in memory starting ataddress $100 Big endian stores most significant byte in the

lowest address:100 12101 34102 56103 78

Little endian stores the word in reverse:100 78101 56102 34103 12


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Observations: In storing several data items into a memory

segment, each item will have the same address(big or little endian does not change this)

Endianness does not effect the ordering of itemsin a data structure

No general consensus as to which is best Little endian: Intel X86, Pentium, VAX Big endian: S370, Motorola 680x0, RISCs

No real advantage in one style over the other Decision is based on supporting previous

machines in many cases Biggest problems:

Data transfers between machines of different endianness

Must go though a format conversion

process Manipulation of individual bytes (bits) of

multibyte word


Addressing Modes

Once we have determined the number of addresses contained in an instruction, themanner in which each address fieldspecifies memory location must bedetermined

Want the ability to reference a large rangeof address locationsTradeoff between Addressing range and flexibility Complexity of the address calculation

Immediate Mode The operand is contained within the instruction

itself Data is a constant at run time No additional memory references are required

after the fetch of the instruction itself Size of the operand (thus its range of values) is

limited


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Direct mode The address field of the instruction contains the

effective address of the operand No calculations are required One additional memory access is required to

fetch the operand Address range limited by the width of the field

that contains the address reference Address is a constant at run time but data itself

can be changed during program execution Some machines use variations of direct

addressing: direct and extended addressing onthe 68HC11 -- 8 and 16-bit addresses


Indirect addressing The address field in the instruction specifies a

memory location which contains the address of the data

Two memory accesses are required The first to fetch the effective address The second to fetch the operand itself

Range of effective addresses is equal to 2 n,where n is the width of the memory data word

Number of locations that can be used to holdthe effective address is constrained to 2 k , wherek is the width of the instructions address field

Register-based addressing modes Register addressing: like direct, but address

field specifies a register location Register indirect: like indirect, but address

field specifies a register that contains theeffective address

Faster access to data, smaller address fields inthe instruction word


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Displacement or address relativeaddressing Two address fields in the instruction are used

One is an explicit address reference The other is a register reference

EA = A + (R) Relative addressing A is added to the program counter contents

to cause a branch operation in fetching thenext instruction

Base-register addressing A is a displacement added to the contents of

the referenced base register to form theEA

Used by programmers and O/S to identifythe start of user areas, segments, etc. and

provide accesses within them


Indexing Essentially the same impact as base addressing Our book says that the A field is a memory

address and the referenced register contains thedisplacement value that is added to A

This is not necessarily the case! Indexingas used and defined by Motorola for the68HC11 is exactly as our author definesbase addressing

Better distinction of the base and indexingmight be who / what does the reference.Examples:

Indexing is used within programs foraccessing data structures

Base addressing is used as a controlmeasure by the O/S to implementsegmentation


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Pentium and PowerPC addressing Text shows 9 addressing modes for the Pentium

Range for simple modes (e.g., immediate)to very complex modes (e.g., bases withscaled index and displacement)

The PowerPC, in contrast has fewer, simpleraddressing modes


Instruction Formats

The instruction format defines the layoutof instruction word in terms of itsconstituent partsMost basic issue is the instruction length Longer instruction lengths permit more

opcodes, addressing modes, addressing ranges,etc. Longer does not imply a significant increase in

functionality, however Instruction lengths are equal to the basic

memory transfer data size or a multiple of thatsize

If the memory system retrieves 32 bitwords, instructions should be 32 bits (or 64)

Allocation of bits Tradeoff between number of opcodes supported

(rich instruction set) and the power of theaddressing capability


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PDP-8: 12-bit fixed format

Figure 10.4 PDP-8 instruction format


PDP-10 36-bit fixed format Stressed orthogonality, completeness, and

direct addressing Trade off ease of programming with increased

H/W expense

Figure 10.5 PDP-10 instruction format


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PDP-11 variable length format 16-bit word length minicomputer Variable length instructions to provide

flexibility -- more opcodes and memoryaddressing modes

Cost of the flexibility is a significantincrease in the CPU complexity

Figure 10.6 PDP-11 instruction formatsEE 4504 Section 7 28

PowerPC format

Figure 10.8 PowerPC instruction formats


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Summary

In this section, we have looked at theinstruction set of the machine Content

types of information contained in them Functional completeness

Addressing in instructions Number of addresses included and theimpact on the program

Addressing modes -- how is the effectiveaddress determined

Instruction format Size and amount allocated to different fields Fixed and variable formats Complexity

Documents

Much of the Computer’s Architecture / Organization