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Mr. Vinod P. Tayade (M.Tech. VLSI Tech.)
Definition :Operand and Opcode
1/7/2021Mr. V. P. Tayade, Government Polyechnic, Nashik
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Operand – The data on which the operation is
performed called as operand
MOV A,R1 = A4h
BEFORE A = 20H & R1 = 30H – OPERAND
AFTER A = 30H & R1 = 30 H
Opcode (operational code) – The hexadecimal
code of an instruction is called as opcode.
Addressing Modes
1/7/2021Mr. V. P. Tayade, Government Polyechnic, Nashik
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The Manner in which the operand is specified in an
instruction is called as addressing mode of that
instruction.
Types
Immediate Addressing Mode
Register Addressing Mode
Direct Addressing Mode
Register Indirect Addressing Mode
Immediate addressing mode
1/7/2021Mr. V. P. Tayade, Government Polyechnic, Nashik
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In this Immediate Addressing Mode, the data is provided in theinstruction itself. The data is provided immediately after theOpcode. These are some examples of Immediate Addressing Mode.
MOV A, #0AFH ; A = AF
MOV R3, #45H ; R3 = 45h
MOV DPTR, #0FE00H ; DPTR = FE00H
In these instructions, the # symbol is used for immediate data. In thelast instruction, there is DPTR. The DPTR stands for Data Pointer.Using this, it points the external data memory location. In the firstinstruction, the immediate data is AFH, but one 0 is added at thebeginning. So when the data is starting with A to F, the data shouldbe preceded by 0.
Register addressing mode
1/7/2021Mr. V. P. Tayade, Government Polyechnic, Nashik
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In the register addressing mode the source data
should be present in a register (R0 to R7). These are
some examples of Register Addressing Mode.
MOV A, R5
Before exe :- A=11h and R5=22h
After exe:- A=22h
MOV R0, A
Direct Addressing Mode
1/7/2021Mr. V. P. Tayade, Government Polyechnic, Nashik
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In the Direct Addressing Mode, the source address is
specified by using 8-bit Address in an instruction. Only
the internal data memory can be used in this mode.
Here some of the examples of direct Addressing Mode.
MOV R2, 45H
Before :- R2=33h, 45h=44h
After :- R2=44h
MOV R0, 05H
MOV A, 20H
Register indirect addressing Mode
1/7/2021Mr. V. P. Tayade, Government Polyechnic, Nashik
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In this mode, the source address is given in the registerand this register is represented in an instruction with asymbol ‘@’.
MOV A,@R1
R1 = 30 h & 30 h = 22h (before)
A = 22h
MOV A,#22H – Immediate A = 22h
MOV A,R1 - Register : R1=22h(Before) , A = 22h
MOV A,30H - Direct : 30h = 22 h , A = 22h
Operand = 22 H
Instruction Set
1/7/2021Mr. V. P. Tayade, Government Polyechnic, Nashik
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TRANSFERARITHMETIC LOGICAL BOOLEAN
PROGRAM
BRANCHING
MOV ADD ANL CLR LJMP
MOVC ADDC ORL SETB AJMP
MOVX SUBB XRL MOV SJMP
PUSH INC CLR JC JZ
POP DEC CPL JNC JNZ
XCH MUL RL JB CJNE
XCHD DIV RLC JNB DJNZ
DA A RR JBC NOP
RRC ANL LCALL
SWAP ORL ACALL
CPL RET
RETI
JMP
Data Transfer Instructions
1/7/2021Mr. V. P. Tayade, Government Polyechnic, Nashik
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The Data Transfer Instructions are associated with transfer with data between registers or external program memory or external data memory.
The Mnemonics associated with Data Transfer are given below.
MOV
MOVC
MOVX
PUSH
POP
XCH
XCHD
Data Transfer Instructions
1/7/2021Mr. V. P. Tayade, Government Polyechnic, Nashik
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Rough Work Slide
1/7/2021Mr. V. P. Tayade, Government Polyechnic, Nashik
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MOV A,#33H A = 33H
MOV R0,A R0 = 33H
MOV 30H,R0 30H = 33H
MOV 33H,A 33H = 33H
MOV A,@R0 A = 33H
R0H =55H & R2H = 77H
A = R1=
MOV A,#55H & MOV R1,#77H
MOV A,30H & MOV R1,31H
MOV A,R0 & MOV R1,R2
Data Transfer Instructions
1/7/2021Mr. V. P. Tayade, Government Polyechnic, Nashik
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XCHD A,@R1
Before
A = 35 h
@R1 = 79h
After
A = 39h
@R1= 75h
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Mr. V. P. Tayade, Government Polyechnic, Nashik
Arithmetic Instructions
1/7/2021Mr. V. P. Tayade, Government Polyechnic, Nashik
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Using Arithmetic Instructions, you can perform addition, subtraction, multiplicationand division. The arithmetic instructions also include increment by one, decrement byone and a special instruction called Decimal Adjust Accumulator.
The Mnemonics associated with the Arithmetic Instructions of the 8051Microcontroller Instruction Set are:
ADD
ADDC
SUBB
INC
DEC
MUL
DIV
DA A
The arithmetic instructions has no knowledge about the data format i.e. signed,unsigned, ASCII, BCD, etc. Also, the operations performed by the arithmeticinstructions affect flags like carry, overflow, zero, etc. in the PSW Register.
Arithmetic Instructions
1/7/2021Mr. V. P. Tayade, Government Polyechnic, Nashik
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DA A
DECIMAL ADJUST ACCUMULATOR AFTER ADDITION
IT CONVERTS INVALID BCD NUMBER IN TO THE VALID BCD NUMBER.
ADD A,R1
DA A
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Mr. V. P. Tayade, Government Polyechnic, Nashik
Arithmetic Instructions
1/7/2021Mr. V. P. Tayade, Government Polyechnic, Nashik
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Program: Write Assembly language program to perform addition of two 8-bit numbers, which are stored in 40H and 41H of internal memory. Store result in 42H.
ORG 0000H
MOV R0,#40H ;R0=40H
MOV A,@R0 ;A = 05H
INC R0 ; R0=41H
ADD A,@R0 ;A = 0CH
INC R0 ; R0 =42H
MOV @R0,A ;42H = 0CH
END
40h – 05h
41h – 07h
42h – 0Ch
43h – 00h
44h – 00h
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Mr. V. P. Tayade, Government Polyechnic, Nashik
Program: Write Assembly language program to perform subtraction of two 8-bit numbers, which are stored in 50H and 51H of internal memory. Store result in 52H.
ORG 0000H
MOV R0,#50H ;R0=50H
MOV A,@R0 ; A = 15H
INC R0 ; R0=51H
SUBB A,@R0 ;A= 15-09-0
INC R0 ; R0 = 52H
MOV @R0,A ; 52H=A
END
50h – 15h
51h – 09h
52h – 00h
53h – 00h
54h – 00h
1/7/2021
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Mr. V. P. Tayade, Government Polyechnic, Nashik
Program: Write Assembly language program to perform multiplication of two 8-bit numbers, which are stored in 60H and 61H of external memory. Store result in 62H-LSB and 63H-MSB
ORG 0000H
MOV R0,#60H ;R0=60H
MOV A,@R0 ; A = 15H
MOV B,A ; B = 15H
INC R0 ; R0 =61H
MOV A,@R0 ; A = 09H
MUL AB ;A = LSB, B=MSB OV=?
INC R0 ;R0 = 62H
MOV @R0,A ; 62H = LSB OF RES
INC R0 ; R0 =63H
MOV A,B ; A = MSB OF RES
MOV @R0,A ; 64H = MSB OF RES
END
60h – 15h
61h – 09h
62h – 00h
63h – 00h
64h – 00h
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Mr. V. P. Tayade, Government Polyechnic, Nashik
Program: Write Assembly language program to perform Division of two 8-bit numbers, which are stored in 0200H-(Divisor) and 0201H(Dividend) of external memory. Store result in 0202H-
Quotient and 0203H-Remainder
ORG 0000H
MOV DPTR,#0200H ; DPTR=0200H
MOVX A,@DPTR ;A = 02H
MOV B,A ;B = 02H
INC DPTR ;DPTR=0201H
MOVX A,@DPTR ;A=0BH
DIV AB ;A/B=A-Q, B=R,
INC DPTR ;DPTR=0202H
MOVX @DPTR,A ;0202H=Q
INC DPTR ;DPTR=0203H
MOV A,B ;A =REM
MOVX @DPTR,A ;0203=R
END
0200h – 02h
0201h – 0Bh
0202h – 00h
0203h – 00h
0204h – 00h
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Mr. V. P. Tayade, Government Polyechnic, Nashik
Logical Instructions
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The next group of instructions are the Logical Instructions, which performlogical operations like AND, OR, XOR, NOT, Rotate, Clear and Swap.Logical Instruction are performed on Bytes of data on a bit-by-bit basis.
Mnemonics associated with Logical Instructions are as follows:
ANL
ORL
XRL
CLR
CPL
RL
RLC
RR
RRC
SWAP
Logical Instructions
1/7/2021Mr. V. P. Tayade, Government Polyechnic, Nashik
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Logical Instructions
1/7/2021Mr. V. P. Tayade, Government Polyechnic, Nashik
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Boolean or Bit Manipulation Instructions
1/7/2021Mr. V. P. Tayade, Government Polyechnic, Nashik
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As the name suggests, Boolean or Bit Manipulation Instructions will deal with bitvariables. We know that there is a special bit-addressable area in the RAM andsome of the Special Function Registers (SFRs) are also bit addressable.
The Mnemonics corresponding to the Boolean or Bit Manipulation instructions are:
CLR
SETB
MOV
JC
JNC
JB
JNB
JBC
ANL
ORL
CPL
Boolean or Bit Manipulation Instructions
1/7/2021Mr. V. P. Tayade, Government Polyechnic, Nashik
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Program Branching Instructions
1/7/2021Mr. V. P. Tayade, Government Polyechnic, Nashik
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The last group of instructions in the 8051 Microcontroller Instruction Set are the Program Branching Instructions. These
instructions control the flow of program logic. The mnemonics of the Program Branching Instructions are as follows.
LJMP
AJMP
SJMP
JZ
JNZ
CJNE
DJNZ
NOP
LCALL
ACALL
RET
RETI
JMP
All these instructions, except the NOP (No Operation) affect the Program Counter (PC) in one way or other. Some of these
instructions has decision making capability before transferring control to other part of the program.
Program Branching Instructions
1/7/2021Mr. V. P. Tayade, Government Polyechnic, Nashik
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Program Branching Instructions
1/7/2021Mr. V. P. Tayade, Government Polyechnic, Nashik
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Instruction format
1/7/2021Mr. V. P. Tayade, Government Polyechnic, Nashik
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Label(Optional) : Mnemonic destination,source
For example
L1 : MOV A,R1
Before execution / after
A = 22H / A = 44H
R1 = 44H / R1 = 44H