MPC 5500- the New Generation - eecs.umich.edu€¦ · 1... • • … …... • •

10/27/2004

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Freescale Semiconductor Confidential Proprietary. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2004

October 28, 2004

MPC5500 -The New Generation

Slide 2Freescale Semiconductor Proprietary. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2004

MPC5554Core• 40-132 MHz PowerPC ISA e200z6 Core

• Integer binary user mode compatible with MPC500• New SIMD module for DSP and floating point features

Memory• 2M byte Flash with ECC• 115k byte SRAM

• 64k Data RAM with ECC (including 32K with standby)• 32k unified-cache (with line locking)• 19k for eTPU (16k code & 3k parameters)

I/O• 88 Timed I/O Channels

• 2 x 32 channel eTPU• 24 channel EMIOS with unified channels

• 3 x FlexCAN (64 buffers each) (compatible with TouCAN)• 2 x SCI

• Supports DMA and LIN protocol• 4 x DSPI 16 bits wide up to 6 chip selects each

• Standard SPI with continuous mode and DMA support• Pin serialization (similar to PPM)

• 40 channel Dual ADC - up to 12 bit and up to 1.25µs conversions, 6 queues with triggering and DMA support.

System• Frequency Modulated PLL• 64 Channel DMA Controller• 300 Source Interrupt Controller• Nexus IEEE-ISTO 5001-2001 Class 3+• MPC500 compatible External Bus Interface supporting

‘classic’ and burst external flash.

Boot Assist Module

Interrupt Controller

DMA

External B

us Interface

ExternalMaster

Interface

3 x 5 Crossbar Switch

I/OBridge SIU

I/OBridge2M

FLASH

64KSRAM

(16 S/B)

DSPI

DSPI

DSPI

DSPI

SCI

SCI

FlexC

AN

FlexC

AN

FlexC

AN

AD

C

ADCiAD

C

3k DataRAM

12k CodeRAM

eTPU32

Channel

eTPU32

Channel

EMIOS24

Channel

NexusIEEE-ISTO 5001-2001

AMux

JTAGPowerPC

e200z6

32k CacheMMU

SIMD(DSP &

floating point)

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rArB

rDop op

0 31 32 63

evfs*

r3r4

0 31 32 63

85 4613 21

77 34

Register File

rArB

rD

op op

0 31 32 63

evfs*

r3r4

r5

add

0 31 32 63

85 4613 21

77 67

add r5, r3, r4

Classic PowerPC: add r5, r3, r4

rArB

rD

op op

0 31 32 63

evfs*

r3r4

r5

add

0 31 32 63

85 4613 21

98 67

evadd r5, r3, r4

add

SPE: evadd r5, r3, r4

r5

MPC5500: Single Instruction Multiple Data (SIMD)

SPE extends the ordinary Book E 32 bit registers to be 64 bits in size

Ordinary PowerPC instructions operate as usual just on the bottom 32 bits, leaving the top 32 bits untouched

SPE instructions do the specified operation on the bottom 32 bits and, in parallel, on the top 32 bits. So two independent operations are executed by the one instruction


Compiler vendors support Intrinsics for Vector Operations (Integer and Float)• Freescale Semiconductor has defined a syntax (per Freescale Semiconductor’s

“SPE PIM” document).• Run time Double Precision Libraries also provided.

Example • Greenhills compiler output

for (j = 0; j < IR_SIZE/2; j++)out[i+j] = __ev_fsadd(out[i+j], __ev_fsmul(ins, fir[j]));

Inner loop:.L95: // top of loop

evldd r8, 0(r10) // load out[i+j]evldd r9, 0(r11) // load fir[j]evfsmul r9, r7, r9 // multiply FIR coefficient by input sampleevfsadd r9, r8, r9 // add to output arrayaddi r11, r11, 8 // update fir pointer for next iterationevstdd r9, 0(r10) // store out[i+j]addi r10, r10, 8// update out pointer for next iterationbdnz .L95 // PowerPC “decrement and branch if zero” instruction

MPC5500: Compiler Support for Vectors (SIMD)

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MPC5500: Memory Management Unit and Pages

TLBTLB Entry 0TLB Entry 1TLB Entry 2TLB Entry 3

…TLB Entry 23

Effective Address(32-bits)

Real Address(32-bits)

Page

Page

Page

Page

PhysicalMemory

MMU

Core

Memory space is divided into up to pages, each having:• SIZE (4K, 16K, 64K, 256K, 1M, 4M, 16M, 64M, 256M)• Address base, Effective Page Number (EPN), which is translated to a

different base, Real Page Number (RPN)• Permission control• Memory and cache attributes

Each page is created by an entry in the Translation Lookaside Buffer (TLB)

…

…

…


System Memory

• Cache is faster than system memories.• Cache contains copies of a subset of system memories (flash and

system RAM).• Because it’s smaller than system memory, the contents are normally

moved in and out as required by the program using a hardware algorithm that decides what part of cache gets replaced.

Physical(Real)

Address

Cache

MPC5500: How Cache Works

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Core Platform

MPC5500: Calibration Using Cache

No changes needed to application software. Same ld & st address operands to access cached variables

Data space allocated in 32 byte blocksData points can be scattered in memory mapDoes not require external memoryData values can be viewed and changed

through JTAG/OnCE or softwareCode must execute special instructions to

allocate variables in cacheAllows limited calibration of full production

module in the vehicle

e200z6 Core

JTAG/Once

Flash

Cache

Calibration Tool


MPC5500: DMA Flexibility & Features

Allows building queues for peripherals whose size is only limited by the total memory.

Moves data anywhere in memory map without CPU intervention• Enhanced for autonomous I/O control as well

as data movement

Supports Ping Pong Mechanism• to process large queues such as knock and

misfire data.

64 independent channels with link capability• Allows sophisticated data transfers and

control without CPU intervention.

DMA

CPUDMA

CPUDMA

CPUDMA

CPUDMA

CPUDMA

CPUDMA

CPUDMA

CPUDMA

CPUDMA

CPU

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MPC5500: Crossbar - Parallel Memory Architecture

DMA

AHB Multilayer Switch

SRAM

Flash

Local RAM /cachee200z6

I/O

Concurrent Multi-Port:Up to 8 master and 8 slave ports.32 bit address and 64 bit dataFully-concurrent transfers between

independent master and slave ports.

Programmable master priorities on a per-slave port basis.• Fixed and Round-Robin

arbitration priorities.Parking on slave ports.

• Explicit, park on last master to access that slave and none (low power parking).


MPC5500: eTPUNew arithmetic, logical & control

instructions enable more sophisticated timing functions and use of C compiler

Angle clock hardware simplifies angle domain scheduling

Shared time or angle counter bus for all eTPU and eMIOS blocks

DMA support provides inter-module interaction independent of CPU

24 bit timer resolution

Nexus Class 3 Debug support

Host-Interface

IP Interface

µEngine

Scheduler

32 Double Action Channels

MUX

Pins

TCR1TCR2

Angle Clock

Shar

ed T

ime/

Ang

le B

us

Shared Parameter RAM (3K)Shared Code (16K) Memory

To/From Pin Serializer

Nexus 3

Debug Port

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MPC5500: Angle Clock in Acceleration and Deceleration

When a tooth arrives before Tick count is complete (acceleration), the Tick counter is fast counted to the end of the tooth.

When a tooth does not arrive one tick after the end of the tick count, the TCR2 count is held until a tooth arrives.

P1 P2 P3 P4

P1 / n P2 / n P3 / n

Angle tick

High speed pulses due to acceleration

P2

Stop due to deceleration

Tooth signal


MPC5500: eMIOS

24 Unified Channels each with:• 2 24-bit double buffered registers for captured/match values• 2 equality comparators• 24-bit internal counter• Internal prescaler• Dedicated output pin • Selectable time base• Can generate its own time base

Four 24-bit wide counter buses:• Counter bus A – driven by channel 23 or from eTPU

- Can be shared among all unifiedchannels

• Counter buses B, C, D - driven by channels 0, 8, 16 respectively

- Can be shared by UC 0-7, 8-15, and 16-23 respectively

Supports pin serialization

IP b

us

Bus interface

UnitUnified

channel_0

Unified channel_1

Red C

Unified channel_2

ClockPrescaler

SysClock

A

B

Chan 0 outChan 0 in

Chan 1 outChan 1 in

Chan 2 outChan 2 in

Unified channel_23

Chan 23 outChan 23 in

output disable [0:3]

Each channel is programmed for its own mode

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MPC5500: eQADC

MPC5500 EQADC + DMA emulates QADC64E

0 – 5V conversion range40 single ended inputs4 pairs of differential inputs

• uses 2 pins differential input12 bit A/D resolution

• 10 bit accuracy at 400 KHz• 8 bit accuracy at 800 KHz

6 queue pairs, each with own FIFO and own triggering

Right justified signed and unsigned results

Time stamp supportMigration plan for future external ADCs

using SSI interface

MUX

A/D Converter

Queue Control

CCW Table

Result Table

ETRIG

Result Alignment

MUX

A/D Converter

DMA

CCW Table

ETRIG

CFIFORFIFO

SSI

MPC500 QADC64E

MPC5500 EQADC Sys Mem

Result Alignment

Result Table


DM

A

6

6

On-chip ADCs2:2 or40x1 Mux

2:2 or40x1 Mux

40

+

-ADC1

+_ ADC0

Commanddecode, comms& ADC control

Pins

eTPU

MIO

S

S/W

Triggers

Command FIFO

CFIFO 0CFIFO 1CFIFO 2CFIFO 3CFIFO 4CFIFO 5

Prio

rity 6

ADCi

Results FIFO

RFIFO 0RFIFO 1RFIFO 2RFIFO 3RFIFO 4RFIFO 5

MPC5500: eQADC System

Off-chip deviceMux +

-

Commanddecode, comms

& control Serial port

6

Nextcommand

Lastresult

System RAM

DIFF

Single Ended

etc.etc.

Res 2Cmd 2

Res 1Cmd 1

Result Q 5

Cmd Q 5

•••

etc.etc.

Res 2Cmd 2

Res 1Cmd 1

Result Q 1

Cmd Q 1

etc.etc.

Res 2Cmd 2

Res 1Cmd 1

Result Q 0

Cmd Q 0

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MPC5500: DSPIMPC5500 DSPI + DMA emulates

QSPI

Command options per transfer• Clock Rate• CPOL, CPHA• PCS to SCK delay• SCK to PCS delay• Delay between frames• 4 to 16 bit size• 6 Chip Selects

Continuous CSDeglitched decode

• LSB or MSB first

Supports pin reduction with serialization• Pads of signals which get

serialized can be used for GPIO

MPC5500 Rx Queue Tx Queue Cmd Queue

DMA Controller

Flash or SRAM

DSPI

SRAM

Txfifo

Rx fifo

DMAReq

DMAReq

Shift Reg

SOUT

SIN

Flash or SRAM

MPC555 Rx Queue Tx Queue Cmd Queue

Queue Control Block

Tx/Rx Data Register

Shift Register

MISO

MOSI

Rx TxCtrl

TXRAM

RX RAM

CMD RAM


MPC5500: Simple SPI TransmissionTask: Use DSPI_A to send a single command of 0x00FE to the MC33394

power supply chip which turns off Vref1 output (default is on).

Crystal8 MHz

PLLwith 10xmultiplier

DSPI AMasterMode

80 MHz sysclk

SPISlaveMode

LEDVref1

SOUTSCKSINPCS5

MPC5554 MC33394

MPC5554 Evaluation Board

CTAR0 of DSPI A:configure forMC33394 Hard-

wired on EVB

Must beconnectedon EVB. Use any LED.

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MPC5500: DSPI Serialization Example

PA

Chan 15SIU GPIO

eTPU B SIU

Ser. Data Reg. (SDR) - RO Alt. Ser. Data Reg. (ASDR)

Shift Register

TxSS

Deser. Data Reg. (DDR) - RO

MPC5554

DSPI A

PA

Chan 14SIU GPIO

PA

Chan 13SIU GPIO

PA

Chan 12SIU GPIO

Shift Register SOUT

SCKSCK

PCS

Solenoid 0Solenoid 1Solenoid 2Solenoid 3

SMOS

• 4 eTPU B output channels are “serialized” and sent over DSPI A to a SMOS driver

• The 4 pads normally controlled by eTPU channels 12 – 15 can be used as for some other function such as GPIO

• SMOS could return serial data back to DSPI which could be read in the Deser. Data Reg. (DSR)


MPC5500: Interrupt Structure

Interrupt Controller286 Interrupt Request Sources

CPU Interrupt

8 Software1 Watchdog1 ECC Error66 DMA2 PLL6 IRQ Pins

65 eTPU31 eQADC20 DSPI2 eSCI

24 eMIOS

Machine CheckData Storage

Instruction StorageExternal Input

AlignmentProgram

Float. Point UnavailableSystem Call

AP UnavailableDecrementer

Fixed Interval TimerWatchdog Timer

Data TLB ErrorInstruction TLB Error

DebugSPE Unavailable

SPE Data SPE Round

CPU Core

Interrupt Request SourcesException Sources

60 FlexCAN

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MPC5500: INTC Software & Hardware Vector Modes

b handler_307IVPR + 0x1330

…

b handler_nIVPR + n(0x10)

…


…


…

b handler_0IVPR + 0x00Instructions1Address

prologhandler_307

ISRprologhandler_n

epilog

epilog

ISR

handler_0

epilog

ISRprolog

INTC’sIRQ ntaken

.

.

.

epilog

(including using IACKR to get vector

then bl ISR_n)

prologIVPR + IVOR4InstructionsAddressINTC’s

IRQ ntaken

SoftwareVector Mode

HardwareVector Mode

ISRISR_n

•

ISRISR_307•

ISRISR_0

Notes: 1. “b handler_n” instruction is

technically part of the handlers.2. ISR Vector Table alignment in

software vector mode assumes INTC_MCR[VTES]=0.

ISR_1 address

ISR_n address

ISR_307 address…

…

ISR_0 addressVTBA

ISR Vector Table2Address

IACKR

.

.

.

Handler Branch Table


MPC5500: INTC Preemption

Interrupt sources are assigned one of sixteen priority levels• 15 is highest priority, 0 is lowest• Each interrupt source’s priority is specified in its Priority Select

Register (8 bits wide), INTC_PSRx

Higher priority ISRs can preempt lower priority ISRs

Preempted priorities are automatically pushed/popped to/from a LIFO in the interrupt controller.

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MPC5500: INTC Priority Ceiling Protocol

Coherent accesses are allowed by temporarily elevating the Current Priority of an interrupt.

Example:• Three ISRs all share the same resource• ISR1 has priority 1

ISR2 has priority 2ISR3 has priority 3 (higher priority)

• ISR1 wants access to the shared resource• ISR1 elevates the Current Priority, INTC_CPR[PRI], to 3

prevents ISR2 and ISR3 from accessing the resource while ISR1 is using it3 is the “ceiling” of the priorities of ISRs that may want access to the shared resource

• After ISR1 is done with the shared resource, it lowers the Current Priority back to 1


DMANXDM

Auxiliary Port

MDO (4 or 12)TDOTDI EVTOMCKO

JTAG ControllerJTAG Port

TMSTCKRDY§ MSEO[0:1]EVTI

eDMAC On-chip Mem & I/O

Off-chip Mem & I/O

Data,

WatchpointTrace

Buffere200z6NZ6C3

Read/Write Access

e200z6 MMU Cache

Program, Data, Ownership, Watchpoint

Trace

Buffer

R/W Reg, R/W Data, Halt, step, cont

§ RDY used only for R/W Access

eTPUNDEDI

eTPUEngine

1Engine

2

Program, Data,

Ownership, Watchpoint

Trace

Buffer

R/W Reg, Halt, step, cont

CDC

XBAR

JCOMP

MPC5500: Debug - Nexus Interfaces

NPC- NexusPort Conn.

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Freescale Semiconductor Inc. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2004


MMU Example Use: A/B Calibration with MMU

• Use the MMU to switch between any number of calibration banks.• MMU solution requires a very small amount of core intervention

when switching banks.

Internal FLASH Calibration #1

External SRAMCalibration #3

MMU selects which of many calibrations the

software sees at a fixed address

External Memory Emulator

Calibrations #5&6

External SRAMCalibration #4

Calibration

Effective Address

Physical Address

Internal FLASH Calibration #2

MMU

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MPC 5500- the New Generation - eecs.umich.edu€¦ · 1... • • … …... • •