Monte Carlo Study Distribution Gate Current of LDD MOSFET’s · 2018. 11. 13. · 302 A. HARKARet al. Degradation processes due to hot electrons in silicon devices and circuits have

VLSI DESIGN2001, Vol. 13, Nos. 1-4, pp. 301-304Reprints available directly from the publisherPhotocopying permitted by license only

(C) 2001 OPA (Overseas Publishers Association) N.V.Published by license under

the Gordon and Breach Science Publishers imprint,member of the Taylor & Francis Group.

Monte Carlo Study of the Lateral Distributionof Gate Current Density Along the Channel

of Submicron LDD MOSFET’sA. HARKARa, R. W. KELSALLa’* and J. N. ELLISb

alnstitute of Microwaves and Photonics, School of Electronic and Electrical Engineering,The University of Leeds, Leeds LS2 9JT, UK;

bMITEL Semiconductors, Plymouth, Devon, PL6 7BQ, UK

This paper presents the spatial distribution of hot electrons along the channel of a0.35 micron MOSFET using the full band pseudopotential Monte Carlo simulatorDAMOCLES. The important aspect of this investigation is the implementation of arigorous statistical enhancement technique along the channel of the device, to probe thehot electrons generated along the channel. Simulations have been carried out for differentbias points. The results clearly show that the probability of generating electrons withenergies sufficient for injection into the oxide layer is significant only at the drain side ofthe device. It is also observed that the peak gate current occurs exactly just inside theLDD region coincident with the position of maximum lateral electric field.

Keywords: Monte Carlo; MOSFET; Statistical enhancement

1. INTRODUCTION

With the advancement of microfabrication, chipdensity goes on increasing and individual transistorsize shrinks. Among the various factors thatcontribute to this remarkable evolution is thedevelopment of innovative device structures thatminimize the device area and interelemental sepera-tion. This decrease in the critical device dimensionsto the 0.1 micron range, accompained by increasedsubstrate doping densities, results in a significantincrease in the lateral and vertical electrical fields inthe channel region. Under the influence of high

lateral fields in submicron MOSFET’s, electrons inthe channel and pinch-offregions can gain sufficientenergy to surmount the Si/SiO2 energy barrier ortunnel into the oxide. Injection ofhot electrons intothe gate oxide may result in carrier trapping ondefect sites in the oxide, or generation of interfacestates at the silicon oxide interface, or both. Thisdamage caused by hot carrier injection affects thetransistor characteristics, causing a shift in thresh-old voltage, degradation in transconductance, anda general decrease in the drain current capabilities[1,2]. Thus these phenomena constitute a majorpotential problem for long-term device reliability.

*Corresponding author. Tel." +44 113 2332068, Fax: +44 113 2332032, e-mail: [email protected]

301

302 A. HARKAR et al.

Degradation processes due to hot electronsin silicon devices and circuits have been studiedextensively during the past decade and severalexperimental and simulation studies have beencarried out to analyse, understand and model thedegradation due to interface state and carriertrapping in the oxide [3, 4]. So far, however it hasnot been simple to form a definite picture of thelateral distribution of interface traps or trappedcharges in the oxide along the channel [5]. To gainbetter insight for analysis and modeling of thedamage mechanism, as well as associated reliabilityproblems, it is highly desirable to have informationabout the lateral distribution of interface traps andhot electrons above the damage threshold. How-ever due to limitations of the probing techniquesand theoretical models used, the picture is stillelusive.With this motivation the present study was

undertaken, involving an investigation of the dis-tribution of electrons with energy greater than3.3 eV along the channel of the simulated struc-ture, and calculation of the gate current densityprofile along the channel. Here we present a de-tailed simulation study of the spatial and energydistributions of hot electrons and their applicationin modeling gate current density profiles along thechannel of 0.35 micron LDD MOSFET’s.

2. DEVICE SIMULATOR

One of the most powerful methods for investigat-ing hot electron related degradation is an ensembleMonte Carlo simulation including a full band de-scription and a self-consistent calculation of theinternal electric field. For this reason we have usedthe IBM DAMOCLES [6] simulator. DAMO-CLES incorporates a pseudopotential bandstruc-ture model which gives accurate information onthe high energy electronic states and electronenergy distributions. Spatial resolution of theenergy distribution places extremely high demandson the sampling capability of the simulation at thehigh electron energies. The DAMOCLES code

address this issue by providing a sampling en-hancement (or statistical enhancement) algorithm,and for this work it was essential to define anextensive sampling enhancement scheme.Thus as a part of this investigation, an extensive

sampling enhancement scheme was formulated andimplemented in DAMOCLES, which helped toresolve the distribution function over 40 orders ofmagnitude. In order to incorporate this enhance-ment technique in DAMOCLES, for the presentset of simulations the channel has been spatially di-vided into distinct regions, and within each spatialregion, kinetic energy is partitioned into intervals.Thus the entire span of position, from the sourceto the drain junction, and kinetic energy space(up to typically 3.8 eV) in the device is divided intostatistical boxes. In each box a different super-particle charge may be assigned. During the simu-lation, as particles move from common to rareregions in real and energy space, they are sub-divided according to these superparticle chargefactors, thus increasing the sampling capability inthe sparsely populated regions of space.The spatially localised energy distributions

obtained in these boxes were used in conjunctionwith the spatial distributions of carrier density andnormal velocity component to obtain the spatiallydistributed gate current density profile. The gatecurrent was then modeled as a post processing ofthe DAMOCLES results as

JG qnvy(E)f(E)dE (1)

where q is the electronic charge, n is the electronconcentration, E is electron kinetic energy and ffrepresents the Si/SiO2 potential barrier height.vy(E) andf(E) are the normal velocity and energydistribution functions respectively.

3. RESULTS AND DISCUSSION

The device structure simulated in this work isbased on 0.35 micron conventional LDD CMOS

MONTE CARLO STUDY 303

technology developed by MITEL semiconductors.The device structure simulated has an LDDjunction doping density of 4. 1018cm -3 and anoxide thickness of 7 nm. The device has channelthreshold and punchthrough implants and an n-type polysilicon gate.

Simulations were carried out for two biasconditions. Figure shows the lateral (c) electricfield profiles obtained for Vd=Vg=3.5V and5.0 V whilst Figure 2 shows the vertical (9) electricfield distribution along the channel of the de-vice. Figures 3 and 4 show the electron energy

-0.8

LU -1.6

u,.. -2.40

-4.0Vg=Vd 5.0 V

0 0.08 0.16 0.24 0.32 0.40 0.48

X-AXIS DISTANCE (lm)

FIGURE Lateral electric field component along the channel.

-0.2

-0.4

oa -0.6zO

< -0.8

-1.0

0,08 0.16 0.24 0.32 0.40 0.48

DISTANCE (lxm)

FIGURE 2 Vertical (y directed) component of electric fieldalong the channel.

10.5

10-1o

z 10-15O

0.20__.0.25

+-IU

0.45- 0.47 micron .H.0,42-0,43 micron0.39-0.41 micron

10"35 .2 8o o’.’ . .+ENERGY

FIGURE 3 Electron energy distribution at different positionsalong the channel for Vg Vd 3.5 V.

10.5

10-10

10"15

10.20

10.25

10-30

10-35

10.40

0.43-0.45 micron0.41-0.43 micron

0.39-0.41 micron0,37,.0+39

0.35-0.37 micron0.31-.033 micron0,29+0,31 micron0.11-0.13 micron

0 0.6 1.2 1.8 2.4

ENERGY (eV)

3.0 3.6

FIGURE 4 Electron energy distribution at different positionsalong the channel for Vg Vd 5.0 V.

distribution function at different positions alongthe channel. From this study the following resultsare observed: the probability of generating elec-trons with energies sufficient for injection into theoxide layer (>_ 3.3eV) is significant only at thedrain side of the device. This can be attributeddirectly to the high lateral electric field in thisregion. On the other hand, the vertical electric fieldhas little influence on electron heating, since,despite the high vertical field at the source side,no significant hot electron population is observedin this region. It can also be seen that spatial extentof the hot electron region extending from the

304 A. HARKAR et al.

0.2 0.25

Vg=Vd =5.0V

0.3 0.35 0.4 0.45 0.5

Vg=Vd=3.5 V

0.2 0.25 0.3 0.50.35 0 4 0.45

Distance in micron

FIGURE 5 Gate current density along the channel.

electron-included interface state generation. Thusit may be concluded that the maximum density ofhot electron induced interface states occurs justinside the LDD junction, as has been indicated bysome recent experimental work [5].

Acknowledgments

AH and RWK would like to thank EPSRC forfinancial assistance and S. Laux and M. V.Fischetti for useful discussions during the courseof this work.

References

drain side is greater in case of the higher drainvoltage.The hot electron distribution dominates the

form of the gate current density profile along thechannel. The peak gate current occurs just insidethe LDD region, Figure 5, coincident with theposition of maximum lateral electric field. Beyondthis point the gate current decreases abruptly cor-responding to abrupt falls in both the lateralelectric field and hot electron population.Given the extremely small thickness of the oxide

layer (7 nm) it is reasonable to assume a strongspatial correlation between gate current and hot

[1] Wang, C. T., Hot Carrier Design Consideration for MOSDevices and Circuits London: Chapman and Hall, 1992.

[2] Ancona, M. G., Saks, N. S. and McCarthy, D., LateralDistribution of Hot-Carrier Induced Interface Traps inMOSFET’s, IEEE Trans on Electron Devices, 35(12), 2221,Dec., 1988.

[3] Wang, T., Huang, C., Chou, P. C., Chung, S. and Tse-EnChang, Effects of Hot Carrier Induced Interface StateGeneration in Submicron LDD MOSFET’s, IEEE Trans.on Electron Devices, 41(9), 1618, Sept., 1994.

[4] Mahapatra, S., Parikh, C. D., Rao, V. R., Viswanathan,C. R. and Vasi, J., A Comprehensive Study of Hot-Carrier Induced Interface and Oxide Trap Distribution inMOSFET’s Using a Novel Charge Pumping Technique,IEEE Trans. Electron Devices, 47, 171, Jan., 2000.

[5] Chung, S. S. and Jiuun-Jer Yang, A New Approach forCharacterizing Structure-Dependent Hot-Carrier Effects inDrain Engineered MOSFET’s, IEEE Trans. on ElectronDevices, 46(7), 1371, July, 1999.

[6] DAMOCLES (2.99) Manual.

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Monte Carlo Study Distribution Gate Current of LDD MOSFET’s · 2018. 11. 13. · 302 A. HARKARet al. Degradation processes due to hot electrons in silicon devices and circuits have