Modulo (2n+1) arithmetic logic

Dharma P. Agrawal and T.R.N. Rao

Indexing Terms: Adders, Digital arithmetic

Abstract: A novel format for representing modulo (2 + 1) numbers is shown to be helpful in achievingmodular addition and complementation. Logic for fast addition using carry-look-ahead and modular com-plementation is also presented.

1 Introduction

Application of modular arithmetic in error diagnosis andresidue computers is well established.1-s The residuenumber systems modulo 2" and (2"—1) are beneficialif they are prime pairwise. The additions modulo 2" or(2" — 1) can be accomplished by w-bit binary adders. Thecarry overflow is thrown away in the first case whereasend-around-carry is used for mod (2n — 1). Recentlyincreased interest has been shown in moduli of the form(2n + 1) (References 6, 7). The logic implementation ofmodulo (2" + 1) addition is not that simple and in thepast the necessity of a more complex design approachhas discouraged its use. The inclusion of mod (2n + 1)provides more flexibility to the system designer. Thispaper introduces a novel way of representing mod (2" + 1)numbers and of reducing the design complexity consider-ably thereby making (2" + 1) a serious candidate formodular operations.

2 Number representation

Let Zm denote the set of integers {0, 1, 2 , . . .m — 1}called here the number system of modulus m. For m =2" + 1 numbers in Zm cannot be represented as binary^-tuples. Therefore each XEZm is represented by a binary(n + l)-tuple X of the form

X = ( * „ _ ! ...Xi...X0,Ix) (la)

Where JC,- has the usual weight of 2' and Ix has a weight of1, the same as JC0 , Ix is called the zero indicator and equalszero iff X=0.

Hence

x =Setting

n - l

>=o

i=O

for 0 < x < m — 2 = 2" — 1 we have

This representation is utilised throughout this paper.

(\c)

(2)

Paper T253E, first received 4th May and in revised form 22ndAugust 1978Dr. Agrawal is with the Department of Electrical & ComputerEngineering, Wayne State University, Detroit, Michigan 48202,USA. Dr. Rao is with the Computer Science Department, SouthernMethodist University, Dallas, Texas 7527S, USA

3 Modular addition

Let S be the addition modulo m of two numbers X andY E Zm. To find S let us define Q and Cn as

Q = 1 iff x+y>m-\

and

Cn = liffx+y + IxIy>m-l

(3a)

(3b)

It is worth mentioning that Q can be obtained as an over-flow when x and y are added by an «-bit parallel adder.'Similarity Cn is detectable by the overflow of an n-bitadder with a 'hot input' IxIy added to x and y as a carry-in to the lowest-significant bit (l.s.b.) position.

At this point s and /s for different numerical rangesof X and Y can be computed as is illustrated in Table 1.The arithmetic expressions for (Ix+Iy) and S can beeasily obtained as

Ix+Iy = (4a)

and

S = /.(s + l) = \X+Y\m

= \x+y+Ix+Iy\m

= (Ix vIy)\x+y+IxIy (4b)

It may be noted that v represents a logical OR operationwhile + denotes an arithmetic addition and \a\m representsthe smallest nonnegative integer congruent to a modulo m.

The expression in eqn. 4b can be utilised to formulate sand 7S for the different cases shown in Table 1 and can begiven as:

Cases 1,2: s = \x+y+IxIy\m^

= x+y+IxIy (5a)

and

4 = '*v/y

Case 3: s = \x +y + IxIy lm_i = 0

and

Is = Cn = 0 (5b)

Case 4: s = \x +y\m_l = x +y + I —m

and

Is = 4 v Iy (5c)

It can be readily seen that eqns. 5 can be represented by the

186 ELECTRONIC CIRCUITS AND SYSTEMS, NOVEMBER 1978, Vol. 2, No. 6

0308-6984/78/060186 + 03 $01-50/0

Table 1: s and la for different range of X and Y

Case Value ofX+ Y

I x. x + y Identification

1,2m-2]

0,0 0 Q = 0,Cn = 0,not both zero [0,m-2] Q = 0,Cn=01,1 m-2 Q = (},€„ = •]1,1 [m - 1,2m - 4 ] Q = 1,Cn = 1

0101

0x +0(x +

V

y

+

+

'* '

D

y

—m

The square bracket [ ] indicates the range

flow diagram shown in Fig. 1. In this diagram [a] representsthe integer part of a. Fig. 2 illustrates a straightforwardscheme utilising an n-bit fast carry-look-ahead binary adder.Initially the carry-in to l.s.b. (least significant bit) is keptzero by setting the D flip flop. Once the carry-overflow isavailable its value is stored in the D flip flop and a secondADD cycle time is allowed. We obtain a logical expressionfor/c as follows:

4 = (Q v Cn)(lx v Iy (6)

where Q and Cn have been defined by eqns. 4a and 4b.They are also indicated in Figs. 1 and 2.

It may be noted that the scheme of Fig. 2 is muchsimpler than those given in the literature.6'7 Moreover itcan be implemented by off-the-shelf integrated circuits.

4 Carry-look-ahead (c.l.a.) adder

As already pointed out the scheme of Fig. 2 requires twocycles of addition operations plus a D flip flop and aproperly delayed clock pulse. One way to perform additionin one step is to compute two conditional sums; the firstone as the addition of x and y and second as the sum ofx, y and the 'hot bit' IxIy as carry-in at the l.s.b. position.Then the signals Q and Cn can be utilised to dictate a

truecase 4

s •*

Q -*

x+

'xV

$

t

S-1

/

y'm-i

!y

fj

\ false/ cases 1-3

s*|s*

r

Ikjyj

false

cases 1,2

proper choice between them. Such an arrangement requirestwo sets of n-bit adders and n multiplexers. Anotheralternative is to design carry-look-ahead circuits for directmodular arithmetic. The design procedure for such adirect addition scheme is given below.

To achieve look-ahead first of all generate and propagateterms have to be computed. For a binary adder let Gt andPi denote the carry generate and propagate terms, respect-ively, at the /th bit position when two numbers a and b areadded.

Then

Gi - «« - I

so that

Q = GtV

tGt-! v

and

St=PM*Ct

(7c)

(Id)

where V and © are logical OR and exclusive-OR operations,respectively, and Co is the carry-in at the l.s.b. position.

As clear from the discussions in the previous Sections,modular cl.a. logical relations can be obtained by first com-puting Cn with Co = 0 and then evaluating Co =IxIyCn.This substitution and a little manipulation gives

as

Ct = Gt v Pft_x v PA-i

P2Gi V ^ . , ..•P

-, v . . . v

(8a)

v . . . v

V GnGn

Gi+3Gi+2Pi+2

' « . ,'y

— n-bit cl.a. binary adder

Fig. 1 Flow diagram for mod (2n + 1) addition Fig. 2 Logic diagram for mod (2n + 1) addition

ELECTRONIC CIRCUITS AND SYSTEMS, NOVEMBER 1978, Vol. 2, No. 6 187

and

= GnGn-iGn* • • • G2G,PnPn_x . . .P2PJxIy (8b)

Logical implementation of these relations give the modularcarry-look-ahead unit.

5 Modular complementation

Let Y be the modulo m complement of X. Then, by de-finition,

Y = Ix\m-x-\\m =Ix\2n-x\m =Iy(y

(9a)

(9b)

Iy = IX (9C)

When Ix = 1 the eqn. 9b is nothing but the 1 s complementof x and can be obtained simply by complementing in-

Hence

y =

and

Yn-2 Yn-3

Fig. 3 Modulo (2n + 1) complementation

dividual bits of x. This leads to an obvious simple circuitimplementation of eqns. 9b and 9c and is given in Fig. 3.

6 Concluding remarks

The specific way of representing numbers presented heremakes modulo (2n + 1) addition and complementationmuch simpler than available in the literature.6'7 An addedadvantage is that available binary adders can be effectivelyutilised.

7 Acknowledgement

This work was supported by NSF research grant ENG76-11237 and US Office of Naval Research ContractN00014-77-C-0455

8 References

1 GARNER, H.L.: 'The residue number system', IRE Trans.,1959, EC-8,pp. 140-147

2 SZABO, N.S., and TANAKA, R.I.: 'Residue arithmetic and itsapplications to computer technology' (McGraw-Hill, NewYork, 1967)

3 MASSEY, J.L., and GARCIA, O.N. in TOU, J.L. (Ed.):'Error correcting codes in computer arithmetic', 'Advancesin information systems science' (Plenum Press, New York,1971), Vol. 4, Chap. 5, pp. 273-326

4 RAO, T.R.N.: 'Error coding for arithmetic processors'(Academic Press, New York, 1974)

5 SELLERS, F.F. Jun., HSIAO, M.Y., and BEARNSON, L.W.:'Error detecing logic for digital computers' (McGraw-Hill,New York, 1968)

6 RAO, T.R.N., and TREHAN, A.K.: 'A redundant code formodulo 2 + 1 arithmetic'. Paper presented at the first south-eastern symposium on system theory, Virginia PolytechnicInstitute, May 1970

7 CHINAL, J.P.: 'The logic of modulo 2 + 1 adders'. Proceedingsof the 3rd symposium on computer arithmetic, SMU, Dallas,Nov. 1975, IEEECS 75Chl017-3C, pp. 126-135

Dharma P. Agrawal was born in Balod,M.P., India in 1945. He received a B.E.in electrical engineering from theRavishankar University, Raipur, M.P.,India in 1966; an M.E. (Hons) inelectronics and communicationengineering from the University ofRoorkee, Roorkee, U.P., India in 1968and a D.Sc. Tech. in electricalengineering from the Federal Instituteof Technology, Lausanne, Switzerland

in 1975. He has been a member of faculty in the M.N.R.Engineering College, Allahabad, India, the University ofRoorkee, Roorkee, India, the Federal Institute ofTechnology, Lausanne, Switzerland, the University ofTechnology, Baghdad, Iraq and the Southern MethodistUniversity, Dallas, Texas, USA. Presently, he is serving theWayne State University, Detroit, Michigan, USA, as anassistant professor in the Electrical and Computer Engineer-ing Department. He has taught many courses in the area ofcomputer engineering. He has several publications in bothEuropean and American journals. His current fields ofinterest are microprocessors and microcomputer systems,computer architecture, fault-tolerant computing, parallelprocessing and systems programming.

Thammavaram R.N. Rao was born inAndhra Pradesh, India, on 5th June1933. He received the B.Sc. degree inphysics from Andhra University,Andhra, India, in 1952, the D.I.I.Sc.degree from the Indian Institute ofScience, Bangalore, in 1955, and theM.S. and Ph.D. degrees in electricalengineering from the University ofMichigan, Ann Arbor, in 1961 and1964, respectively. He was a member

of the Technical Staff of the Bell Laboratories, Holmdel,NJ, from January 1964 to August 1966 and worked in thedevelopment of Electronic Switching System 1. He waswith the Department of Electrical Engineering, Universityof Maryland, College Park, during 1966-1975. Since 1975,he has been a Professor of Computer Science and ElectricalEngineering in the School of Engineering and AppliedScience of Southern Methodist University, Dallas, Texas. Hisprimary interests are in computer architecture, computerarithmetic, fault-tolerant computing, and coding theory.He is the author of 'Error coding for arithmetic processors'(Academic Press, 1974).

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