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Module 6: VHSIC Hardware Description Language

VHDL stands for VHSIC (very high-speed integrated circuit) hardware description language.

Process of bringing number of circuits into single chip.

It is a programming language used to design or simulate a digital system. This language was first

introduced in 1981 for the department of Defense (DoD) under the VHSIC program.

Do we really need VHDL? There are other conventional options to describe or design system. They are

1. Boolean Equations

By creating Boolean equations & using different minimization techniques e.g. K map, Quine

MC Cluskey, for required digital system, one can design system.

But if system is very big which contains millions of gates, then this method is

impractical.

If we know how system behaves but don‟t know it‟s equation then also we can not

design digital system using this method.

2. Schematic based design method

It uses CAD tools. This method also have drawbacks. It is time consuming to design large

systems which contains millions of gates. This method can not built system by only

describing functional behavior of system.

All above drawbacks are get overcome by using VHDL.

Why VHDL is most Universal?/ What are advantages of VHDL? 1. VHDL is most popular HDL language wordwide. In North America and Europe more than 50%

design engineers use VHDL.

2. Flexible:- Simply by editing source code easy modification possible in circuit.

3. No limit on size of circuit for implementation.

4. Less time to market:- Once coding is ready, system can be built on FPGA/CPLD in no time.

Hence prototyping is possible.

5. System can be specified in structural and/or behavioral ways at different levels. It does not

restrict user for one type of description only. Even VHDL can used at different complexity

levels, i.e. from single transistors to complete systems.

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6. VHDL is not only restricted to electronics system. It has been used for modeling & simulation of

electromechanical, hydraulic, chemical and other systems.

7. VHDL based simulation tools are available easily. Simulation means applying inputs to system

through software and checking output again on software. Simulation is used to check whether

system is working asper desire. Output is in form of timing waveforms. No hardware come into

picture. Modelsim and Synplify Pro are the most popularly used simulation tools.

8. Many vendors offer synthesis tools. Synthesis means conversion of design at gate level circuit.

Commonly Used VHDL tools

Vendor Simulator Synthesizer

Altera Modelsim- Altera Edition Altera Quartus

Xilinx ISE Simulator XST

Actel Modelsim-Actel Edition Synplify

Mentor Modelsim PE Leonardo Spectrum

Some terms in VHDL:-

Netlist:- It is textual representation of circuit in terms of components and nets that are connecting the

components.

RTL:- It is level of description of a digital circuit in which operation is spread over several clock cycles

describes circuit behavior as a flow of data between registers.

History of VHDL:- DoD need VHSIC chips. At that time, most of companies were using different HDL to describe or

develop VHSIC, because of that different vendors could not exchange designs to one another. Each

Vendor provide its design to DoD in different HDL. Hence it is difficult to combine this all. Therefore

need of standardization come forward. In 1981, DoD has given responsibility to 3 companies, IBM,

Texas Instruments & Intermetrics of developing common standard language for design. These

companies were developed VHDL version 7.2 in 1985. Joint efforts by universities, Industry & DoDs

make language standardize by IEEE in 1987. After 5 years IEEE standard need to be rebooted.

Features of VHDL/ Capabilities of VHDL:- 1. It supports hierarchy – Digital system can be modeled as set of interconnected components.

Again each component can be modeled as set of interconnected subcomponets.

Consider example of a Full-adder which is the top-level module, being composed of

three lower level modules i.e. Half-Adder and OR gate.

Example:

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2. VHDL is not case sensitive language

3. VHDL is not restricted to electronics only. It has been used for modeling & simulation of

electromechanical, hydraulic, chemical and other systems.

4. It is synthesizable language.

5. Along with functionality, area and speed can be identified.

6. Large designs can be modeled using VHDL. There is no limitation on size of design.

7. It contains elements which makes Large Scale design easy. e.g. components, procedures,

functions, packages.

8. Language is not technology specific:- As technology independent same model can be

synthesized into different vendor libraries. E.g. same design can be synthesized on 65 nm

technology, 90 nm technology, 45 nm technology,

9. Support for Test & simulation:- To ensure that design is correct as per the specifications, the

designer has to write another program known as “TEST BENCH”. It generates a set of test

vectors and sends them to the design under test(DUT). Also gives the responses made by the

DUT against a specifications for correct results to ensure the functionality. Test benches can be

written using same language to test other VHDL modules.

10. System can be explained in VHDL by three different ways. They are called as modeling styles.

E.g. Dataflow modeling, Behavioral modeling and structural modeling.

11. It supports flexible design methodologies: Top down, Bottom-up, Mixed.

12. Concurrency:- VHDL is a concurrent language. It supports concurrent statements, means

statements executing in parallel. HDL differs with Software languages with respect to

Concurrency only. VHDL executes statements at the same time in parallel (concurrently), as in

Hardware.

13. VHDL supports sequential statements also, it executes one statement at a time in sequence

only. As the case with any conventional languages.

example:

if a=„1‟ then

y<=„0‟;

else

y<=„1‟;

end if ;

14. Strongly typed language:-

VHDL allows LHS & RHS operators of same type. Different types in LHS & RHS is illegal in

VHDL. Allows different type assignment by conversion.

example:

A : in std_logic_vector(3 downto 0).

B : out std_logic_vector(3 downto 0).

C : in bit_vector(3 downto 0).

B <= A; --perfect.

B <= C; --type miss match, syntax error

Basic Elements in VHDL file:- Identifiers

Data objects

Data Types

Operators

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Basic Structure of VHDL file/ VHDL code:- Library

Package

Configuration

Entity

Functions

Procedures

Architecture

VHDL code for full adder:- Step1:

Draw IC layout for full adder. Full adder adds 3 bit

of data and gives output in form of sum & Carry.

Decide name of IC.

Decide input and output pins.

Name each pin.

Fulladder

Step2:

Decide in which modeling style program to be

written.

Here dataflow modeling style is selected.

Before writing program using dataflow modeling

programmer should know either logic equations of

digital system or Truth table of system.

For full adder equations of system are:

Sum = A B Cin

Cout = AB + ACin + BCin

These equations are represented in architecture body of VHDL code using VHDL operators.

_ _Full adder VHDL Program

library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Fulladder is Port ( A : in STD_LOGIC; B : in STD_LOGIC; Cin : in STD_LOGIC; Sum : out STD_LOGIC; Cout : out STD_LOGIC); end Fulladder;

architecture dataflow of Fulladder is begin Sum <= A XOR B XOR Cin; Cout <= (A AND B) or (A AND Cin) or (B AND Cin);

end dataflow;

………………………………………………..

In above program words written in bold

are called „keywords‟. (Keywords are

reserved words in language. They have

specific meaning & task assigned

which is known by language. They can

not be used as basic identifiers.)

Remaining words are called

„Identifiers‟. These are names given by

programmer.

Description of VHDL program:

VHDL source code(program) has two main parts: „Entity‟, which describes input ,output pins of

system and „Architecture‟ which gives entire function of circuit. Refer above VHDL code while

reading following description.

Comment:- comment in VHDL is denoted by “--”( Two consecutive dashes). Everything after the

“--” to the end of the line is considered as comment. Whatever typed after -- in same line is not

considered for compilation.

Optional

Called as subprograms and they are optional

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Library:- Library statements usually located at the top of a file. Library contains number of

packages. IEEE is name of library. It contains standard modules, all inbuilt defined constructs like

all basic gates, operators, packages etc. In most vhdl programs you have already seen examples of

packages and libraries. Here are two:

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_signed.all;

The packages are "std_logic_1164" and "std_logic_signed" and the library is "ieee". Since the

"scope" of the library statement extends over the entire file, it is not necessary to repeat that. The

VHDL datatype „std_logic‟ is declared in „ieee.std_logic_1164‟, and so a use word at the top of the

file makes the datatype visible for later reuse. Above the „use’ word, we need a „library’ word so

that the compile would know that the word ieee is a library name.

There are two types of libraries in VHDL: System library and User library. User library is not

needed. If required we can include it. But system library is compulsory to use in any vhdl code.

Syntax of system Library:-

library library_name; use library_name.Package_name.ALL;

Example of system library:-

library IEEE; use IEEE.STD_LOGIC_1164.ALL;

Syntax of work Library:-

library work; use work.user_Package_name.ALL;

A signal declared in a package can be used by any design entity that access the package. Such

signals are similar in concept to global variables used in computer programming languages.

Entity:-

Entity specify external view of system. Entity does not specify circuit functionality. It only explains

input ,output pins of system, names of that pins and their data type. „port‟ means pins of system.

Direction of port means direction of pins. It is also called „modes‟ for signals. Datatype informs

about type of data, the pin can accept or give out e.g. binary, decimal etc.

Syntax of entity:-

entity entity_name is

port(port_name:direction_of_port_pin datatype;

port_name: direction_of_port_pin datatype;

………..);

end entity_name;

Example of entity:-

Fulladder

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entity Fulladder is Port ( A : in STD_LOGIC; B : in STD_LOGIC; Cin : in STD_LOGIC; Sum : out STD_LOGIC; Cout : out STD_LOGIC); end Fulladder;

Mode/Direction Purpose Diagrammatic View

IN Used for signal that is an input to a system

OUT Used for signal that is an output to a system.

INOUT Used for signal that is both input & output to a

system.

BUFFER Used for a signal that is output from system.

But signal can go in both directions, either in

or out inside the components. The value of

signal can be read by component.

Identifiers:- Identifiers are used as names for VHDL entities, architectures, objects, procedures,

functions, processes etc., and as reserved words. There are two classes of identifiers: basic

identifiers and extended identifiers.

I. Basic Identifier (naming) rules:

Can consist of alphabet characters [an upper-case letter (A... Z), or a lower-case letter (a. ..

z)), numbers(digits (0 . . . 9)], and underscore ( _ ) character.

First character must be a letter (alphabet). It should not start with digit (0 to 9) or by „-„.

Last character cannot be an underscore.

Space is not allowed with the alphabets or numbers.

Consecutive underscores are not allowed.

Upper and lower case are equivalent (case insensitive). Eg., Count, COUNT, and CouNT, all

refer to the same identifier.

VHDL keywords cannot be used as identifiers.

Any special character other than underscore is not allowed.

Two underscore characters cannot appear consecutively.

-- legal identifiers:-

Decoder_1 FFT Sig_N

Not_Ack R2d2

-- illegal identifiers:- _Decoder_1 2FFT Sig_#N Not-Ack

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II. Extended Identifiers:-

Sequence of characters written between two back slashes is called extended identifier. They may

contain any graphic character (including spaces and non-ASCII characters), as well as reserved words.

Upper- and lower-case letters are distinguished.

Examples:-

\signal\ \C:\ \Cads\ \Signal @#\

\.$25\ \2FFT\ \entity\ \end\

Objects in VHDL:-

Objects are things that hold values. Means they are working like container to store values.

Four types of objects in VHDL

1. Constants

2. Variables

3. Signals

4. Files

a) Constant: An object of constant class can hold a single value of a given type. This value is

assigned to the object before simulation starts and the value cannot be changed during the

course of the simulation.

b) Variable: An object of variable class can also hold a single value of a given type. However

in this case, different values can be assigned to the object at different times using a variable

assignment statement.

c) Signal: Signal objects are used to represent wires in a circuit .Signal objects are typically

used to model wires and flip-flops while variable and constant objects are typically used to

model the behavior of the circuit. There are three places in which signals can be declared in

VHDL code: in entity, in architecture and in packages. Future values can be assigned to a

signal object using a signal assignment statement. Syntax to define signal is as follows:

Signal signal_name: Datatype;

d) File: Note that files are defined a fourth data type initially, but were reclassified as objects in

VHDL Files can be opened for reading and writing. The package STANDARD defines basic

file I/O routines for VHDL types. The package TEXTIO defines more powerful routines

handling I/O of text files

Differnce between Signal and Variable in VHDL:-

Signal Variable

Value of the signal is assigned using „<=‟

symbol

Value of the variable is assigned using „ : = „

symbol

Signals can be used globally.(Seen by entire

code i.e. can be used outside of process).

Variable can be used only locally.(Visible only

inside the process box)

Signals can not be declared inside the process Variables are declared only in process

Signals can not assigned values immediately Values to variables are assigned immediately

Signals can be written in package, entity or

architecture.(In sequential as well as

concurrent code)

Variable can be written only in sequential code

i.e. process, function or procedure.

The scope of an object is as follows : –

i. Objects declared in a package are available to all VHDL descriptions that use that package

ii. Objects declared in an entity are available to all architectures associated with that entity

iii. Objects declared in an architecture are available to all statements in that architecture

iv. Objects declared in a process are available only within that process

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Datatypes in VHDL:

All declarations of VHDL ports, signals, and variables must specify their corresponding datatype or

subtype. By reading datatype software decides which type of value that currosponding port/signal can

take or give out. Same data types may be assigned to different object types. For example, a constant, a

variable and a signal can all have values which are of data type BIT.

1) Predefined:-

Scalar:- Values belonging to this type appear in sequential order. Hence relational operators can

be used on these values.

There are four different kinds of scalar types. They are

1. enumeration,

2. integer,

3. physical,

4. floating point/Real.

Integer:- INTEGER is a predefined type with the set of values which are only integers, in a

specific range provided by the VHDL system i.e., from -(231

- 1) to +(231

- 1).

E,g, „a‟ signal is declared as of type integer by following statement

Signal a: integer;

Then following statements tell which values would be correct assigned values

a <= 1; -- correct

a <= -1; -- correct

a <= 1.0; -- error

Some of the allowable and frequently used predefined operators on these values are +, for addition, -,

for subtraction, /, for division, and *, for multiplication.

Real:- They are used to represent numbers out of range of integer values as well as fractional

values.

The range of REAL is again implementation dependent but it must at least cover the range -I.OE38 to

+I.OE38 and it must allow for at least six decimal digits of precision.

Floating point literals can also be expressed in an exponential form. The exponent represents a power of

ten and the exponent value must be an integer.

E,g, „a‟ signal is declared as of type real by following statement

Signal a: real;

Then following statements tell which values would be correct assigned values

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a <= -1.5E10; -- correct

a <= 1.0; -- correct

a <= 1; -- error

Physical:-

A physical type contains values that represent measurement of some physical quantity, like time, length,

voltage, and current. Values of this type are expressed as integer multiples of a base unit. Only

predefined physical type in VHDL is TIME. Type TIME include positive as well as negative values.

type time is range 0 to . . .

units

fs;

ps = 1000 fs;

ns = 1000 ps;

us = 1000 ns;

ms = 1000 us;

sec = 1000 ms;

min = 60 sec;

hr = 60 min;

end units time;

The user may define other physical types as required.

Enumeration:-

• Boolean type:- Object of type Boolean can have the values True or False, where true is

equivalent to 1 and false is equivalent to 0.

• Character type:- It can constitute any of characters out of 191 characters. These are called as

character literals.

Always character literals are written between two single quotes.( „ „ ) . e.g. „m‟ , „?‟ , „3‟

• Bit:- It can take value either 0 or 1.

• Bit_vector :- An object of bit_vector type is array of data objects whose type is bit.

Example1: let us consider the declaration

Signal c : bit_vector ( 1 to 4 );

By observing above declaration software reserves total 4 rooms with names c(1) c(2) c(3) c(4)

In this first written room c(1) is always used to hold MSB bit, while last written room name c(4) always

used to hold LSB bit.

In architecture when c<= “1100” ; statement is written then following values are get assigned to

signals automatically: c(1) <= 1; c(2) <= 1; c(3) <= 0; c(4) <= 0;

Example2: let us consider the declaration

Signal y : bit_vector ( 2 downto 0 );

By observing above declaration software reserves total 3 rooms with names y(2) y(1) y(0)

In this first written room y(2) is always used to hold MSB bit, while last written room name y(0) always

used to hold LSB bit.

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In architecture when y<= “110” ; statement is written then following values are get assigned to signals

automatically: y(2) <= 1; y(1) <= 1; y(0) <= 0;

• Std_logic :- In real life, a digital system may need more values than just '0' an d'1' to represent

the signal value. In this section we will look at a standard called "Standard Logic" to allow us to

represent logic systems with more than just values of '0' and '1'. This is a multi-valued logic

system. You may have noticed that the type BIT we have been using has some limitation. It can

only used to represent '0' and '1'. In simulation it can be useful to represent other values such as

unknown, un-initialized, high impedance and different drive strengths. It provides more

flexibility than „bit‟ type. With „bit‟ type, we can not handle many practical situations like

unknown state, high impedance state, don‟t care state, multiple driver strength. To solve these

difficulties, IEEE later released the STD_LOGIC_1164 package, which declares a data type

STD_ULOGIC. Std_logic contains different 8 values. While std_ulogic contains 9 values. It is

an enumerated type and is defined as type std_logic is („U‟, „X‟, „0‟, „1‟, „Z‟, „W‟, „L‟, „H‟,‟-‟)

where

'U' means uninitialized

'X' means unknown

'0' means low

'1' means high

'Z' means high impedance

'W' means weak unknown

'L' means weak low

'H' means weak high

'-' means don't care

In std_logic only „U‟ is absent remaining values are present. Std_logic is data type which allows signals

driven by more than one source to be used, that is, multiple driver signal.

Std_logic_vector:- Consider like bit_vector type

Composite datatype:-

Composite data types are collections of scalar types. VHDL recognizes records and arrays as

composite data types. Records are like structures in C. Arrays may be one-dimensional or multi

dimensional.

• Arrays :- It represents collection of values all belonging to same type.

e.g. type byte is array (7 downto 0) of bit;

• Record:- It represents collection of values which belong to different types.

E.g. type resource is record (P reg, Q reg : bit vector(7 downto 0); Enable: bit)

end record resource;

Acess Type:- It is similar to pointer in C. It points to address particular type of object. It is

useful in accessing dynamically allocated objects.

File type:- It is used for files in host environment. They provide mechanism for reading and

writing data to hard disk files.

2) Userdefined:- User can define their own data type. Also, we can define all predefined type

as userdefined type by simply modifying it‟s range and putting user defined range. That means

user has flexibility to define a range of data types according to circuit requirements. Any new

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type can be introduced by using the type declaration, which names the type and specifies its

value range.

Sytax is as follows:

Type identifier Is Type_defination

and any data object of above defined type can be created as below:

signal X : identifier;

userdefined datatypes are mostly used to write VHDL code of moore and mealy FSM. Userdefined

Enumerated type can be used to create state & their names in state machine design.

E.g. Type states Is (A,B,C,D);

signal X: states;

Operators in VHDL :- VHDL provides many operators for writing logic equations in „architecture‟, for performing many

mathematical operations, for simulation, for synthesis. Operators belonging to same class have same

priority. NOT operator has highest priority than other logical operators like AND, OR.

e.g. Let us consider

1) y <= x1 AND x2 OR x3 AND x4;

then first x1x2 is calculated. Secondly x1x2 value is ORed with x3. At last this result is ANDed with

x4.

2) y <= (x1 AND x2) OR (x3 AND x4); In this first x1x2 , along with x3x4 is calculated. Then both

results are ORed.

Concatenation operator:- This is the process of combining two signals into a single set which

can be individually addressed. The concatenation operator is „&‟. A concatenated signal‟s value is

written in double quotes(“”), whereas the value of a single bit signal is written in single quotes(„‟).

Architecture:- Architecture explains functionality of circuit, While entity does not deal with

functionality. ARCHITECTURE is always associated with an ENTITY. There can be multiple

ARCHITECTURES associated with an ENTITY. There are different ways to describe circuit within

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architecture body. They are called as modeling styles. These modeling styles are dataflow style,

structural style, behavioural style or mixed style.

Syntax to write architecture: −

architecture architecture_name of entity_name is

architecture_declarative_part;(It is optional)

begin

Statements;

end architecture_name;

e.g. Consider architecture of full adder VHDL code

architecture dataflow of Fulladder is begin Sum <= A XOR B XOR Cin; Cout <= (A AND B) or (A AND Cin) or (B AND Cin); end dataflow;

Here, we should specify the entity name for which we are writing the architecture body. The

architecture statements should be inside the „begin‟ and „énd‟ keyword. Architecture declarative part

may contain variables, constants, or component declaration.

Modeling Styles in VHDL:-

To construct digital system, it is required to explain it in „architecture‟ field of program. There are

different ways to describe system.

If system is explained in „architecture‟ by using logic equation or using truth table, then this style of

explanation is called dataflow modeling. To explain truth table, one can use „with-select‟ statement or

„when-else‟ statement. Dataflow modeling always uses concurrent statements.

Second type of modeling is behavioural style of modeling. If equation of system or truth table of

system is not known, only behavior of system is known, then this type of modeling is used.

„If-else‟ or „case‟ statements are used in this type of modeling. Along with this „Process‟ statement

should be present in program.

Next modeling style is structural modeling. The term structural modeling is the terminology that

VHDL uses for the modular design. if you are designing a complex project, you should split in two or

more simple designs in order to easy handle the complexity. The benefits of modular design in VHDL

are similar to the benefits that modular design or object-oriented design provides for higher-level

computer languages.

When system is complex, we need to take help of Mixed type of modeling styles which includes all

above ways of representations.

Books to refer for VHDL: -

1] VHDL: Basics to Prgramming by Gaganpreet Kaur

2] Fundamentals of Digital Logic with VHDL Design by

Stephen Brown, Zvonko Vranesic

3] VHDL primer by Jayaram Bhasker