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MODULE II

Monolithic ComponentsIntroduction:

In monolithic technique all components are formed by a series of simultaneous identical diffusion processes. It is usual for the diffusion profiles and surface concentrations of the various layers of ICs to be chosen so as to optimize the performance of the active devices. All passive components such as diffused resistors or capacitors are designed so as to be fabricated from these layers, accepting the sheet resistances, doping levels, and profiles that exist for active components. Monolithic components are fabricated using planar technology or epitaxial growth. If the variety of manufacturing processes by which IC components are fabricated through a single plane then it is termed as planar technology. If the various components are fabricated on epitaxial layer then the process is called as epitaxial devices.ISOLATION OF COMPONENTS:Once all components are fabricated on a single crystal wafer, they must be electrically isolated from each other. The problem is not encountered in discrete circuits, because physically all components are isolated. There are two methods of isolation in integrated circuits pn junction isolation and dielectric isolation.

PN Junction Isolation The method of isolation is most compatible with the IC processing, i.e., one extra processing step, other than required to fabricate IC, is required in isolation. Basically the method involves producing islands of n-type material surrounded by p-type material. Components are then fabricated in different n-type islands. The p-type material surrounding the islands is given the most negative potential with respect to all parts of the wafer, thus each island and hence component is electrically isolated from the others by back-to-back diodes. The process step for pn junction isolation are explained below :

(i) One begins with the p-type substrate on which n-epitaxial layer is grown. If the component to be fabricated is transistor, then buried layer have to be formed before growing epi-layer. Fig.11 (a) shows epi-layer growth over substrate without buried layer. The epi-layer is then covered with SiO2 layer.

(ii) A p-type diffusion is now performed from the surface of the wafer. Since this is to be performed in selected areas, an isolation mask is prepared prior to this diffusion. A long drive- in time is required for p-type diffusion so that the acceptor concentration is greater than the epi-layer donor concentration throughout the region of epi-layer. Thus the portion of wafer at the location of isolation diffusion is changed to p-type from surface of wafer to the substrate. This is shown in Fig. 11 (b). In other words, the substrate is extended and the surface and acts as an isolation wall. This isolation wall causes the formation of pn junction where around the n-type islands except at the surface. If the substrate is connected to a voltage which is more negative than any of the n-region voltages, the diodes shown will be reversed biased and negligible current will flow. Thus isolation is achieved since any reverse biased pn junction is associated with a depletion capacitance; this will have parasitic effect associated with junction, particularly, at high frequencies.

The main disadvantage of pn junction isolations are as below :

1. The time required for such isolation technique is considerably longer due to diffusion time taken, which longer than any of other diffusions.

2. Lateral diffusion is significant due to longer time taken by isolation diffusion, hence considerable clearance must be used for isolation regions.

3. Isolation diffusion takes an area of the wafer surface which is significant portion of the chip area. From component density consideration, this area is wasted.

4. pn junction isolation method introduces significant parasitic capacitance which degrades circuit performance. The parasitic capacitance is introduced by isolation sidewall and bottom epitaxial substrate junction. Several methods have been developed by manufacturers to avoid above problems. All of these methods circumvent the problems of large area and sidewall capacitance, but they suffer from the parasitic capacitance introduced by bottom epi-substrate junction. Dielectric isolation avoids this problem too.DIELECTRIC ISOLATION

Dielectric isolation in which the various components on the IC chip are electrically isolated from the substrate and from each other by an insulating or dielectric layer. In certain applications, the parasitic junction capacitances or leakage currents associated with the junction isolation methods may not be acceptable. In such cases dielectric isolation is advantageous. Following paragraphs describe various methods of dielectric isolation.

1. V Groove Isolation

Fig. 22 shows V-groove isolation method for producing a dielectrically isolated IC. (i) Starting with an n-type substrate, an n+ diffusion is performed. This is followed by the growth of an SiO2 layer, which is then patterned to form a grid of intersecting lines opening in the oxide. This is shown in Fig.22 (a).(ii) The wafer is then subjected to an orientation-dependent etching (ODE) process using the patterned layer as the etching mask. This results in the V-shaped "grooves" or "moats" as shown in Fig. 22 (b), in which the plane sidewalls are at an angle of 54.74 with respect to the top surface of the silicon wafer. In dielectric isolation, the starting material is oriented silicon. The etchant used in the above step etches away the exposed silicon anisotropically, i.e., the etch rate is much faster along the planes than along the crystal planes. Such preferential etching results in the formation of V groove as mentioned above. The depth D of the isolation groove can be determined by the initial oxide cut width was D= W/(2(iii) The wafer now undergoes a thermal oxidation process to cover the sidewalls of the V-groove with an oxide layer. This is followed by the deposition of a very thick layer of polycrystalline silicon, as shown in Fig. 22(c). This CVD silicon layer will not be single-crystal because it is not deposited directly on the silicon substrate, but on the SiO2 film, which has an amorphous structure, so that a polycrystalline silicon layer results.

(iv) The silicon wafers are mounted on a lapping plate with the polycrystalline side of the wafer down, and the n-type silicon substrate is then carefully lapped down to the level at which the vertices of the V-grooves become exposed, producing the result shown in the figure Fig. 22 (d) shows. Thus we get an array of n-type single-crystal silicon regions that are isolated from the polycrystalline silicon substrate and from each other by the thermally grown oxide layer. The polycrystalline silicon now becomes the substrate and serves to provide the mechanical support for the IC. Also, it serves no electrical function, and is very suitable material for this application because its thermal expansion coefficient is a very good match to that of single-crystal silicon. Furthermore, it can withstand the high processing temperatures.

The lapping operation removes the n-type silicon all of the way down to the vertices of the V-grooves. The n+ diffused layer serves as a buried layer to reduce the collector series resistance of the npn transistors. The rest of the processing sequence for the dielectrically isolated ICs follows along the same line as for the conventional junction isolated IC.Advantages:

(i) The dielectric isolation is useful for such applications as high-voltage and radiation resistant.

(ii) High-voltage transistors and diodes are possible. As the dielectric strength of SiO2 is about 600 V/m, so that a 5000 A0 layer of oxide will result in an n-type isolated region to substrate breakdown voltage in the region of 300 V . In comparison, the n-region-to-substrate breakdown voltage of the junction isolated IC is only about 50 V. (iii) The dielectrically isolated IC is more resistant to the effects of ionizing radiation because of the presence of the insulating oxide layer between the n-type isolated regions and the polycrystalline silicon substrate.(iv) The dielectric isolation offers reduced parasitic capacitance because of the following reasons :(a) Oxide is thicker than the depletion region of the substrate junction as in conventional pn junction isolation and capacitance is inversely proportional to the thickness of oxide.

(b) The permittivity of the SiO2 is one-third that of silicon and capacitance is also reduced.Disadvantage:

This isolation technique is much more expensive than junction isolation technique because it requires extra processing steps.2. Silicon-on-Insulator TechnologyThe silicon-on-insulator (SOI) process produces dielectrically isolated devices. In this process, a thin layer of single-crystal silicon can be produced on top of a thermal SiO2 layer on a silicon wafer. The oxide layer is photolithographically patterned to produce islands or strips of oxide. A thin CVD layer of silicon is then deposited on the wafer. In the regions where the deposited silicon layer overlays the oxide, it will be polycrystalline, but it will be single-crystal in the regions where it is in direct contact with the silicon substrate. The silicon layer is then directionally recrystallized using a scanned laser, electron beam, or resistance-heated strip heater. The silicon film that is in direct contact with the substrate, recrystallizes with the silicon substrate serving as the nucleation centre. As the heated zone is scanned across the wafer the crystal growth propagates from these nucleation regions to the regions of the silicon film on top of the oxide islands or strips. The result will be a complete single-crystal layer of silicon.

3. Another type of dielectrically isolated IC is the silicon-on- sapphire structureTRANSISTOR FABRICATIONEpitaxial Structures

Requirements of Epitaxial Structures are :

For low junction capacitance Cj low doping, i.e. lightly doped substrate, is required.

For high breakdown voltage, low doping, i.e., lightly doped substrate, is required.

For low series resistance, R heavy doping, i.e., low resistivity substrate is required.

We see that the series resistance requirement is conflicting with the capacitance and breakdown voltage requirements. The epitaxial structure shown in Fig. 2 (b), offers a good way of resolving this conflict and simultaneously satisfying the capacitance, breakdown voltage and series resistance requirements. As long as the depletion region remains entirely within the lightly doped epitaxial layer and does not reach the heavily doped n+ substrate, the capacitance and breakdown voltage will be a function only of the epitaxial layer doping and will be independent of the substrate doping. The series resistance will, however, be determined to a major extent by the n+ substrate doping since the epitaxial layer is very thin (~10 m) compared to the substrate thickness of some 250 to 400 m. The series resistance of the epitaxial diode is given by

Rs=(Repi+Rsubstrate+epi(tepi - xj- W))/A+ subt sub /A

where (tepi xi W) is the thickness of the undepleted portion of the epitaxial layer, which is the distance from the edge of the depletion region to the substrate. The heavily doped low-resistivity substrate that constitutes the major part of the overall device thickness can lead to a very substantial reduction in the series resistance.

FIG 1Planar / Epitaxial Diode Fabrication Steps

The processing steps for the epitaxial planar diode, starting with a planar p+ n/n+ diode are as follows :

1. The starting material is n/n+ epitaxial wafer with a 0.005-ohm-cm (Sb-doped) substrate and an epitaxial layer of anywhere from 5 to 25 m thick and phosphorus doped to resistivity in the range 5 to 50-ohm-cm.

2. An oxide layer about 5000 to 8000 A0 thick is grown.

3. Using first photolithography windows are opened in the oxide layer for the p+ diffusion.

4. A p+ diffused layer about 1 to 3 m thick is produced to be the anode region of the diode.

5. Using second photolithography anode contact windows are produced.

6. Anode contacts are produced using aluminium deposition (~1 m) carried out by metallization process.

7. Using third photolithography the metallization is patterned for anode contacts.

8. The metallization film is sintered or alloyed to form a good mechanical bond to the silicon and to produce a low- resistance, non rectifying (ohmic) contact. Sintering or alloying is a heat treatment at about 500 to 600C.

9. A back-side metallization is carried out. In this, a thin film of gold is evaporated on to the lapped back side of the wafers. This is for the eutectic die (chip) bonding of the chips to gold-plated headers or substrates at temperatures in the range 400 to 420C, the gold/silicon eutectic temperature being 370C.

FIG 2Planar Epitaxial Transistor : Fig. 2 (a), shows a cross-sectional view of a typical npn planar epitaxial transistor. Fig.2 (b) shows the impurity profiles for the device. The processing steps are as follows :

1. The starting material is n/n+ epitaxial wafer with 0.005 ohm-cm Sb-doped substrate and n-type epitaxial layer of about 6 to 12 m thickness and 0.3 to 3 ohm-cm resistivity.

2. An oxide layer of about 5000 to 8000 A0 thickness is grown.

3. Using first photolithography, oxide windows are etched for the base diffusion.

4. A two-step deposition-drive in boron diffusion is performed for base region. The junction depth is about 2 to 3m. Surface concentration is around 3 x 1018 cm -3. Sheet resistance is of about 200 ohm per square. The drive-in diffusion is performed in an oxidizing ambient (02) so that oxide is regrown in the windows that were produced in the preceding step.

5. Using second photolithography, oxide windows are etched for the emitter diffusion.

6. A high surface concentration phosphorus diffusion is performed to produce an n+ diffused layer emitter region with a junction depth of about 2 to 2.5 m. A surface concentration in the range 1 x 1021 cm-1and a sheet resistance of about 2 to 2.5 ohm per square are used.

7. Using third photolithography, oxide windows are etched for emitter and base contacts.

8. An aluminium thin film of about 0.5 to 1m separate thickness is deposited on the front surface of the surface using metallization process.

9. Using fourth photolithography, windows are etched for emitter and base contact areas,

10. Heat treatment at 500 to 600C for sintering or alloying the metallization film is carried out.

11. A gold thin film is deposited on the back side of the wafers.

FIG 3Triple Diffused Planar Transistor.

Early planar transistors and ICs used only photolithography and diffusion steps in the fabrication process. However, all diffused planar devices had severe limitations compared with discrete devices. In a triple diffused transistor as shown in Fig. 3 (a), the collector region is formed by n-type diffusion into the p-type wafer. The drawbacks of this structure are that the series collector resistance high and the collector-to-emitter breakdown voltage is low. The former occurs because the impurity concentration in the portion of the collector diffusion below the collector-to-base junction is low, giving the region high resistivity. The latter occurs because near the surface of the collector the concentration of impurities is relatively high, relating in a low break down voltage between the collector and base diffusion at the surface as described earlier. Thus the concentration profile provided by the diffused collector is very disadvantageous; what is require is a low impurity concentration of the collector-base junction for high breakdown voltage and a high concentration below the junction for low collector resistance. Such a concentration profile cannot be realized with diffusion alone, and hence the epitaxial growth was adopted. Epitaxial layer is thus a suitable starting material for the fabrication of bipolar transistors. Channel JEET Fabrication Steps

Fig. 4 shows an n-channel epitaxial JEET structure. The n-type channel is formed by the n type epitaxial layer region between the p+ diffused layer (gate) and the p-type substrate. The processing sequence for the device follows closely to that of the double-diffused transistor and is summarized below.

1. The starting material is n/p epitaxial wafer.2. Thermal oxidation is carried out

3. Using first photolithography, windows are opened for p+ boron top gate diffusion4. Boron diffusion for gate region is carried out.

5. Using second photolithography windows are opened for n+ source and drain diffusion.

6. n+ phosphorus diffusion is carried out to produce the source and drain regions of the JFET.

7. Using third photolithography, contact windows are opened.

8. Metallization is carried out.

9. Using fourth photolithography metallization patterning for source, drain, and gate contact areas is carried out.

10. Contact sintering or alloying is done.

11. Back-side metallization is carried out.

MESFET

Fig. 5 shows a diagram of gallium arsenide (GaAs) MESFET (metal semiconductor field effect transistor). MESFET is nothing but a JFET fabricated in GaAs which employs a metal semiconductor gate region (a Schottky diode). The device operates in essentially the same way as does a junction gate FET, except that instead of a gate channel pn junction there is a gate channel Schottky diode. The depletion region associated with this barrier will control the effective height of the conducting channel and can there by control the drain to source voltage. The width of this depletion region will increase with increasing gate voltage so that we see again that the gate will be the control electrode and as long as the Schottky barrier is reverse biased, the gate current will be very small. Electron mobility in GaAs (8500 cm2 /v-s) is much higher than that of silicon and allows MESFET operation at frequencies higher than can be achieved with silicon devices. The MESFET also possesses very short channel length (~1 m). This results in very short channel transit times for electrons. As a result, MFSFET can operate well into the range of 1 to 10 gigahertz (GHz). Thus, applications of MESFETs were initially in microwave circuits for high frequency performance.However, since 1984, high-speed logic circuits employing MESFETs have been produced commercially. These logic circuits are made compatible with the high-speed bipolar logic family called emitter-coupled to (ECL).

BIPOLAR IC PROCESS The major steps in the IC bipolar process are listed in Fig. 6

1. The starting material is a p-type single crystal silicon wafer, 5 to 20 -cm resistivity and thickness of approximately several hundred micrometers. The diameter can be 50, 75,100,125, or 150 mm. most standard size is 100 mm or about 4 inches.

2. A thin layer of SiO2 is formed on all surfaces of a p-type silicon wafer by exposing it to oxygen or water vapour in an electric furnace. The first masking step defines the area for n+buried layers, (also called subcollector). The function of this layer is to reduce the collector resistance of the transistor. The SiO2 is removed in these areas by chemical etching. Thermal diffusion or ion implantation forms the desired heavily doped n-type i.e. n+ buried layer region. The resulting structure is shown in Fig. 7. (a).

3. The SiO2 masking layer is removed, exposing the entire silicon wafer surface. By epitaxial deposition, an n-type layer is grown, over the entire surface. It is n-type single-crystal silicon 2 to 5 m thick with its resistivity in the range of 0.1 to 1 -cm. During the epitaxial process, the n-type dopant previously introduced in the buried layer areas diffuses in all directions. This is shown in Fig. 7 (b).

4. The wafer with the epitaxial layer is then oxidized at an elevated temperature in an H2O ambient. This forms a layer of SiO2, approximately 0.5 m thick over the entire surface of silicon. A second masking step defines a border completely enclosing n-type islands of silicon that are to be electrically isolated collectors of transistors. A p-type diffusion into the border areas is continued until the entire epitaxial layer has been penetrated, as shown in Fig. 7 (c). Thus, islands of n-type silicon are bounded on all sides by p-type Si. Isolation is achieved by applying voltages such that this pn junction is always reverse- biased. The p-type diffusion uses boron as impurity. A new layer of thermal oxide is grown over the isolation areas.

5. The third masking step defines base regions of npn transistors. Patterns of resistors are formed simultaneously in separate isolated n-type regions. Boron is again diffused (but this time not as deeply) or implanted to forms bases and resistors. The n-type collector is converted to p-type when the density of p-type impurities exceed that of n-type impurities. The resulting structure is shown in Fig. 7 (d).

6. The fourth photolithographic step defines n-type transistor emitters and n-type regions for low resistance contacts to collector regions as in Fig. 7 (e). Again conversion of p-type base to n-type requires impurity compensation.7. An oxide is again thermally grown over the entire wafer and via photolithography, (5th mask) those regions where contact is to be made to the silicon are defined. Metal (Al) is then deposited by vacuum evaporation. The photolithographic process (6th mask) is then used to define the appropriate metallization inter-connection pattern, and the remaining metal is removed. Fig. 7(f) shows the contact areas (defined by 5th mask) to collector, base, and emitter. The 6th masking step is not shown in figure.

At this point, the ICs are in finished state. However before finished form, a protective passivating layer using glass is deposited over the entire wafer. This is known as die passivation or scratch protection, or glassivation. This protects the surface of the wafer from contamination. Glassivation is done using chemical vapour deposition. This added step pays off in protection before and after packaging; in higher yields and in better reliability. A final masking step removes the above insulating layer over the pads where contacts will be made.

Testing the ChipNow the IC chip undergoes a probe test. This is necessary because there are many faulty chips after such highly complicated fabrication steps. Contacting the pads of every chip with microelectrode probes automatically carries out the probe test. Registration of each chip with respect to the probes is done automatically by final mechanical adjustment.

The chip is then tested using a set of test vectors, which consist of a sequence of input voltages, stimuli (to chip input pads) and expected output voltage responses (from chip output pads) that have been previously generated by the design engineer. If the chip passes all test vectors, namely all outputs provide the correct results for all input stimuli then the probes are automatically stepped to the next chip position and all test vectors are applied to that chip. This process is repeated until all chips have been tested. Chips that failed to pass all test vectors are marked with an ink dot. Due to computer controlled operation of wafer probe equipment, upto 16000 test vectors are tested for each chip of a wafer in some minutes. Faulty chips will be thrown away later. Now, the entire wafer is broken into individual chips.Chip Separation.

The entire wafer is divided up into individual chips by "scribe-and-break" operation using any one of the following ways.

1. Diamond-tipped scribe,

2. High-intensity laser beam (laser scribing), or

3. High-speed circular saw.

Since this process is similar to glass cutting it is called scribing and breaking. In the case (1) as above, the grooves are very shallow. In case (2), the grooves are somewhat deeper, and may extend more than halfway through the wafer. In the case (3) the wafer will have a pattern of orthogonally oriented "scribing streets" which are kept clear of oxide and metal and are aligned along certain crystallographic directions to promote the easy and smooth cleavage of the wafer.

A popular process for chip seperation is to use a wafer saw to cut entirely through the wafer. The wafer is mounted on adhesive-coated tape prior to the sawing operation so that after sawing the chips will remain in matrix form for convenience in further operations.

Faulty chips are identified using probe test mentioned above. Hence, only good chips are mounted in containers. The chips are bonded to either metal headers or ceramic substrate. The metal headers are usually Gold plated Kovar. Kovar is an iron-nickel-cobalt alloy whose thermal expansion coefficient is a close matches to that of silicon. The headers are heated to temperatures in the range of 400 to 420C in an inert-gas atmosphere or a mixture of about 90% N2 and 10% H2). The chips are then bonded to the headers by means of the formation of a gold-silicon alloy that results in a good mechanical bond and a low-resistance electrical contact. This contact will be the substrate of the IC chip. The same process is used for discrete components, such as transistor. In that case the contact will be the collector of the transistor.Lead Bonding and Encapsulation. FIG 9Connecting the pads (metallized contact areas) to the terminal (i.e.pins) of container with gold (or aluminium) wires is referred to as bonding. For this purpose small-diameter ~20 to 40 m) gold wires are used. Aluminium wire is used especially for high-current-power devices, where large diameter round or flat ribbon leads may be used. Refer Fig.9.The IC chip is now encapsulated in a metal, ceramic or plastic package. The plastic package is lowest in cost, but the metal and ceramic package offer the advantage of providing a hermetic seal and a higher operating range.

Some times chips are mounted on ceramic sheets without containers. IC prepared in this way is called IC Modules. Each IC packages is finally tested with its external terminals by feeding electric signals to its input pins and analyzing those at its output pins by a computer. This is a package test.

Each wafer may have 100 to 8000 rectangular chips having side 1 to 10 mm. Fig 10 If we process, twenty-five (say) 10-cm wafers in a single batch production, 200,000 ICs are manufactured at a time. If the average component count per IC were only 800, a batch would contain more than 100 million components. If the yield, i.e., the percentage of fault free chips, is 10% (say) 20,000 good chips are mass-produced in a single batch of production. This shows a significant advantage of IC technology.A variety of IC packages are available. The most commonly used are dual in-line pack (DIP), flat pack, leadless chip carriers (LCC), and pin grid arrays (PGA). The PGA provides a very high pin count in a minimum of area.

It should be emphasized that when circuits are implemented on a single chip and encased into a single package, as above it is called a monolithic integrated circuit. When a package contains more than one chip or a mixture of chips and discrete components (one component per container, i.e., one transistor, per container, for example), all of which are put on a large substrate (such as ceramic substrate), it is called a hybrid integrated circuit.

IC packages are usually placed on a PC board. The pins of IC packages and the holes on the pc board are soldered. Then the pc boards are inserted into mother boards which are placed in cabinets along with back planes.

Another approach to assemble IC chips is to place chips on a ceramic carrier and then the ceramic carriers on a ceramic mother carrier. The ceramic mother carriers are placed on a pc board. This approach has the advantage of smaller space than IC packages are assembled on a pc board and a lower cost than hybrid ICs.

MONOLITHIC BIPOLAR TRANSISTOR CONSTRUCTIONS

The monolithic bipolar transistor is most important component of ICs. Because the planar process was used in beginning, for the fabrication of discrete transistors, the same process was extended to ICs. In discrete circuits, passive components are not fabricated by planar process but in ICs these are fabricated by such process. Since planar process is designed for transistor from beginning, the fabrication of passive components is constrained by the design requirements of transistor. This results in limited values of integrated resistors and capacitors obtainable from IC technology.

npn Bipolar Transistor

Although the integrated transistor is almost identical in performance with a discrete transistor, there are some differences.

1. The contact to the collector of an integrated transistor is made through the top surface, while in discrete transistor collector is accessible from substrate.

2. The fact that an integrated transistor is isolated from the other components by a pn junction not found in discrete transistor; therefore, the discrete transistor is free from the parasitics introduced to pn junction isolation.

3. In integrated transistors a very close matching VBE (base-emitter forward voltage) between transistors in close proximity, is found. The VBE of a transistor is typically 700 mV yet the VBE of two identical transistors in close proximity will not differ by more than 2 mV or so. The thermal tracking of VBE of transistor is also good.

The cross section of integrated transistor is shown in Fig.12. In this figure, dark portion is aluminium contact. To have ohmic contact, n+ regions are provided. The transistor is npn type i.e., emitter is n+ diffused, base p-type diffused and collector n-type diffused. The transistor is fabricated in an island of n-type which is grown epitaxially. The island is surrounded by p-type isolation wall by pn junction isolation method. The substrate is p-type. From Fig.12 it is noted that the current path between the collector contact and the actual collector base junction is through a narrow region of high resistivity n-type epi-layer. Thus collector series resistance is significantly large. This may be disadvantageous when low saturation voltages (as in transistor switch) are required. To reduce the series collector resistance, a low resistivity path is provided by n+ layer which is diffused in substrate. This n+ diffusion is called buried layer diffusion and should be carried out prior to epitaxial growth. Additional advantage of buried layer is that it reduces the gain of parasitic pnp transistor formed by p-type substrate, n-type epitaxial layer and p-type base when collector base region of the integrated transistor were to become forward biased. One more point to be noted from the structure shown in Fig.12 is the importance of epitaxy in IC's which is as follows.

In a transistor without a buried layer, the breakdown voltage is proportional to the inverse of collector donor concentration, i.e., ND-1 while the collector resistance is approximately propotional to ND-1 Thus it is clear that there is no way to achieve simultaneously high breakdown and low series collector resistance without modifying the collector region. The buried layer is a region of high donor concentration, providing a low resistance path for collector current. The thin epitaxial layer between base-collector junction and buried layer has low enough donor concentration to provide reasonable high breakdown voltage, yet it is sufficiently thin that it contributes very little series collector resistance.

Impurity profile. Fig. 13 shows a typical impurity profile in integrated transistor.

Profile (A) n+ buried layer. This profile is due to out diffusion of the n+ layer during subsequent epitaxy and diffusion steps. The typical out diffusion is 3 to 4 microns measured from epi-substrate interface. To minimise excessive out diffusion As or Sb are used which are slow diffusants.

Profile (B) n-type epi-layer. This is obtained by epitaxial growth. This is grown to form island in which transistor is fabricated. This profile shows a uniform concentration which is a distinct property of epi-layer Typical resistivity of this layer ranges from 0.5 -cm to5 -cm (No = 1016 atoms/cm3 to = 1015 atoms/cm). The resistivity of this layer is determined from base-collector breakdown considerations.

Profile (C) p-type base diffusion. Since the base, region should be thin (base width = 0.8 to 0.6 micron the diffusion is of Gaussian distribution type and hence the profile. Typical sheet resistivity ranges from 120 to 200 ohms per square.

Profile (D) n+ emitter diffusion. Because of high concentration requirements for emitter doping this profile corresponds to erfc distribution. Phosphorus is used as a dopant for npn transistor to form emitter. The impurity concentration for emitter diffusion reaches the solid solubility limit.As successive diffusion cycles are carried out base-emitter and base collector junctions are formed (shown as X and Y) by impurity compensation. The surface dimension of the transistor are limited by masking and mask alignment tolerances and side diffusion effects.

Note that n+ region is diffused into collector region of transistor. The aluminium collector contact is made here, and the n+ areas help in forming good ohmic contacts. Commercial IC processes often employ ion-implantation of the emitter and base areas. These regions are shallow, and their depths can be more accurately controlled by implantation. Furthermore, as ion implantation is performed at lower temperatures than diffusion, the disadvantage of lateral spreading of the base and emitter is minimized.

The lateral dimensions of the transistor are limited by masking and mask alignment tolerances, and the side-diffusion effects. Normally, a clearance of about 5 m is left around an oxide contact cut, and the edge of the corresponding diffusion. The tolerance is provided to account for any possible misalignment of the mask during the masking operation, or the over-etching of the oxide window during the subsequent etching step to be carried out. This is a common feature in photolithography.

As the Fig.12 shows, the transistor action takes place directly below the emitter region. Therefore, to be able to supply the collector current with a minimum amount of series voltage drop, the collector contact is located as close to the emitter as possible. The distance between the base region and the collector contact is chosen to be significantly more than the respective side diffusion of the p-base and the n+ collector contact areas. The distance between the p-type isolation wall and the inner transistor structure is again set by the side diffusion effects. Since the isolation diffusion is deep one, it also tends to side-diffuse significantly more than the base.

Parasitic Effects in Monolithic Transistor

If we refer to Fig.12, we find that the only electrically active portion of the structure that provides current gain (in forward active mode) is that portion of the base immediately under the emitter diffusion. The rest of the structure provides a top contact to the three transistor terminals and electrical isolation of the component from the rest of the components on the same chip. The principal effect of these regions is to contribute parasitic resistances and capacitances that must be included in the small-signal model of the transistor for high-frequency behaviour. The parasitic elements for the monolithic transistor structure are briefly discussed below.

Series base resistance rb. The base contact is physically away from the active base region. Hence a significant series ohmic resistance is observed between the contact and the active base. The resistance is shown in Fig. 14 and consists of two parts.

rb1 : resistance of the path between the base contact and the edge of the emitter diffusion.

rb2 : resistance between the edge of the emitter and the site within the base region at which the current is actually flowing.

rb1 can be easily estimated. However, calculation of rb2is complex because of the following reasons :

The current flow in the region of rb2 is not well modelled by a single resistor because the base resistance is distributed throughout the base region and two dimensional effects are important.

At even moderate current levels, the effect of current crowding in the base causes most of the carrier injection from the emitter into the base to occur near the periphery of the emitter diffusion. At higher current levels, essentially all of the injection takes place at the periphery and the effective value of rb approaches rb1. In this condition the portion of the base directly beneath the emitter is not involved in transistor action.

The series base resistance rb has a significant effect on the high-frequency gain and the noise performance. For low-noise and for high-frequency applications rb must be low. To achieve low rb, we should maximize the periphery of the emitter which is adjacent to the base contact. At the same time, the emitter-base junction and collector-base junction areas must be kept small to minimize capacitance. In the case of high-frequency transistors, this usually dictates the use of an emitter geometry that consists of many narrow stripes with base contacts between them.

Series collector resistance rc. The series collector resistance is important both in high-frequency circuits as well as in low frequency applications requiring low VCE (sat). The resistance consists of three parts as shown in Fig.15.

rc1: resistance from the collector base junction under the emitter down to the buried layer rc1rc2: resistance of the buried layer from the region under the emitter over to the region under the collector contact r rc2

rc3: resistance of portion from the buried layer up to the collector contact.

The small-signal series collector resistance in the forward- active region can be estimated by adding the resistance of these three paths. The value of r is smaller in saturation than in the forward active region because of holes injected into the epitaxial layer under the emitter by the forward-biased collector-base junction, which modulate the conductivity of the region even at moderate current levels.

Collector-base capacitance. This junction capacitance includes both the flat bottom portion of the junction as well as the side walls. The collector-base junction is formed by the diffusion of boron into an n-type epitaxial layer. The uniformly doped epitaxial layer is much more lightly doped than the p-diffused region, and, as a result this junction is well approximated by a step junction-in which the depletion region lies almost entirely in the epitaxial layer.

Collector-substrate capacitance. This capacitance consists of three portions :

1. Junction between the buried layer and the substrate.

2. Sidewall of the isolation diffusion, and

3. Junction between the epitaxial layer and the substrate.

Since the substrate has an impurity concentration, typically, of 1016 cm -3 it is more heavily doped than the epitaxial layer. We can analyze both the sidewall and epi-substrate capacitance under the assumption that the junction is one-sided step junction with the epitaxial layer as the lightly doped side.

Emitter-base capacitance. The emitter-base junction of the transistor has a doping profile that is not well approximated by a step junction as the impurity concentration on both sides of the junction varies with distance in a rather complicated way. Furthermore, the sidewall capacitance per unit area is not constant but varies with distance from the surface because the base impurity concentration varies with distance.

Monolithic pnp Transistors

The npn transistor is mostly preferable due to two reasons :

1. The electron mobility in Si is about 2.5 times higher than the hole mobility. This means shorter base transit time in npn device than in pnp device. This will lead to a somewhat higher current gain and to improved high-frequency performance for the npn transistor.

2. The solid-solubility limit of the donors (P and As) is substantially larger than that of the acceptor, boron. It is desirable to make the emitter region much more heavily doped than the base region so that when the emitter-base junction is forward biased most of the current flow across the junction will be due to charge carriers emitted by the emitter into the base rather than the flow of charge carriers from base to emitter. It is only the charge carriers that are emitted by the emitter into the base that can contribute to the collector current. The opposite flow of carriers from base to emitter only adds to the base current. As a result of the higher solubility of the donor dopants compared to boron, a more efficient emitter-base structure can be obtained in the case of an npn transistor than in the pnp case, thus leading to a higher current gain.

The applications which require pnp devices are complementary device for use in baising, level shifting, and as output class B stage and emitter coupled pair.

The pnp transistors of performance comparable to npn devices are not easily produced in the same process. The reason is that IC bipolar fabrication process was basically developed for npn devices of high performance. Therefore pnp device structures are developed so that they are compatible with the standard IC fabrication process. Because these devices utilize the lightly doped n-type epitaxial layer as the base of the transistor, they are generally inferior to the npn devices in frequency response and high-current behaviour, but are very useful nevertheless. Various pnp structures are as follows.Lateral pnp Transistor. It is the simplest pnp transistor which can be fabricated simultaneously with the npn bipolars. Fig.16 shows the cross-section view of a lateral pnp transistor. It is made by implanting or diffusing the p-type emitter and collector regions at the same time that the bases of the npn devices are fabricated. Similarly the n+ base contact of this pnp transistor and the n+ emitters of the npn bipolar are formed simultaneously. This simultaneous fabrication means no additional masking or diffusion steps. Thus, both npn and pnp devices can be fabricated by using same sequence of process. However, additional windows in the masking steps are required for lateral pnp.

In lateral pnp, the transistor action takes place in the lateral direction, i.e, parallel to the device surface. The minority carrier transport across the base region is most efficient at or near the surface of the device, where the separation between the collector and the emitter is minimal. This minimum spacing is the effective base width, WB. Due to masking tolerances and voltage breakdown requirements, WB is constrained to be of the order of 6 to 12 m. The lateral pnp transistor has a considerably lower current gain F than does a npn device due to following reasons.

(i) The value of base width of lateral pnp as above is much larger than that of a vertical npn transistor (WB.= 0.8 ).(ii) The emitter efficiency (ratio of current of injected holes to total emitter current across emitter junction for pnp device) of the lateral pnp is poor. This is due to (a) low impurity concentration in the p-type emitter region and (b) small effective area of the emitter. The small effective area of emitter results due to the fact that only the lateral emitter edge facing the collector is active, the holes injected from the rest of the emitter have a much lower probability of reaching the collector.(iii) The lateral pnp current gain is very strongly effected by surface recombination effect.Substrate pnp Transistor. The substrate or vertical pnp transistor is used in high current high power applications. The cross-section view of the transistor is shown in Fig. 18. This device can also be fabricated simultaneously and by the same processes as are used with the npn transistors. These are :(i) The fabrication of the p emitter region of pnp and the base of the npn device (ii) The fabrication of the n+ base region of substrate pnp and the emitter of the npn transistors.

Characteristics:(i) Since the epitaxial layer thickness is now directly related to the effective base width, WB, of the pnp, a tighter control of the epitaxial layer thickness is necessary, typically to 1 m. (ii) Since collector is made of p-type substrate (which is common to rest of the circuit), it is all times ac grounded. Therefore, the substrate pnp is only available in this grounded collector configuration.

(iii) Can not be used for level shifting or voltage amplification. It can provide current amplification, and can be used in class-B complementary output stages. (iv) This transistor also has limitations of current gain and the frequency response due to large base width WB, typically 6 to 8 m, and relatively poor emitter efficiency. The typical F for the device are in the range of 5 to 30. (v) The substrate pnp can handle a high amount of current than the lateral pnp of comparable geometry. MONOLITHIC DIODES

Monolithic Planar Diode ConfigurationsThe diodes are generally transistor adopted. There are basic five configurations of transistor for diode operation as shown in Fig. 27.

1. A base-collector diode is shown in Fig. 27 (a). The emitter is floating and can be omitted. This diode "has a high breakdown voltage of around 50 V. However it has a relatively long switching time of about 100 n sec due to the collector access resistance Rcc, which is nothing but the resistance between the collector terminal and the effective active region to which it is connected. (This resistance is reduced by buried layer diffusion).

2. Base Collector diode with Emitter shorted to Base: The switching time can be improved to about 70 nsec by shorting the emitter and base to remove charge stored at that junction, while retaining the high breakdown voltage, as shown in Fig. 27(b).

3 Base-Emitter junction diode with Collector open .Fig. 27 (c) shows the base-emitter junction diode with collector open. The turn-off time is about 80 nsec and it has a low breakdown voltage (associated with the high doped emitter of around 5 V.

4. Base-Emitter Junction Diode With Collector Shorted To Base The switching time can be reduced to as low as 20 nsec., by shorting base and collector, to remove minority stored charge as shown in Fig. 27 (d). The low breakdown voltage is not affected in this diode.

5. Base-Emitter junction diode with Collector shorted with emitter Fig. 27(e) shows the diode connection where both emitter-bale and base-collector junctions are in parallel. It is obtained by shorting emitter and collector. This diode is not much used due to high junction capacitance which causes low switching speed of around 150 nsec, together with a poor breakdown voltage of about 5 V associated with the base-emitter junction.

The diodes shown in Fig. 27 (b) and (d) are most useful, the former for higher voltage applications, and the latter where switching speed is of paramount importance. Supply voltage encountered in digital ICs rarely exceed 5 or 6 V, hence the limitation of low breakdown voltage of diode shown in Fig. 27 (d) is not a serious disadvantage. Further it has the lowest series resistance and no parasitic pnp action to the substrate (which occurs between the substrate and the p-type base, if the collector-base region of the npn were to become forward biased). Also it has generally the lowest forward voltage drop for a given forward current, lowest storage time and lowest reverse-bias capacitance. These all favourable factors make the diode of Fig. 27(d ) an ideal choice for digital ICs.Avalanche Diode

The avalanche breakdown in a reverse biased diode characteristic can be used for voltage reference or the dc level-shift purposes in IC circuits. The base-emitter breakdown voltage which falls within the 6 to 9 V range is the most commonly used avalanche diode since its breakdown voltage is compatible with the voltage levels available in analog circuits.The breakdown voltage of base-emitter junction of above diode exhibits a positive temperature coefficient, typically in the range of +2 mV/C to +5 mV/C. By connecting a forward-biased diode in series with avalanche diode, it is possible to partially compensate the thermal drift of avalanche diode because the thermal drift of forward voltage of the series connected diode is negative. The composite avalanche diode connection is shown in Fig.28 which has breakdown voltage of (VD + BVEB) with significantly reduced temperature coefficient. Here VD is forward drop of series diode and BVEB is the breakdown voltage (BE junction) of avalanche diode. As the figure shows, the composite connection consists of two transistors back-to-back in diode connection. Since both transistors have their collector and base regions in common, they can be designed as a single transistor with two separate emitters.

Schottky Diode and TransistorWhen a metal is placed in close contact with an n-type semiconductor, a voltage barrier is created, which is known as Schottky barrier. In such contact, there are many free electrons in the metal, whereas the semiconductor contains relatively low. With a positive voltage applied to the metal, this barrier is overcome and the diode begins conducting. A negative bias enlarges the barrier, thus the diode blocks conduction. Such diode differs from an ordinary pn junction as follows :

(i) The barrier is only half as large as that of a junction diode, at low current, a Schottky diode has a forward voltage drop of only about 0.3 V to 0.5 V.(ii) Only majority carriers are involved in the conduction mechanism, which make the Schottky diode a very high speed device with a recovery time less than 1 nsec.

The Schottky effect only takes place in relatively high resistivity semiconductor material. When the semiconductor is heavily doped, a tunneling effect occurs which provides a direct ohmic contact. Fig.29 shows the cross-section view of a typical Schottky diode. It is formed between the epitaxial layer and Al deposited for interconnections. The cathode connections to the epitaxial layer is via a conventional n+ collector contact diffusion, to ensure a good ohmic contact but at the anode connection the n+ diffusion is omitted due to direct ohmic contact provided by Schottky junction.The Schottky barrier is formed betweenaluminium and the n-type epitaxial silicon. The advantage of Schottky diode is that it can be made with existing IC processes. No additional manufacturing steps are required. Schottky Transistor: Fig.30 (a) shows circuit symbol and Fig. 30 (b) shows the cross-sectional view of Schottky transistor. The Schottky transistor provides very fast speed operation. This is possible because the Schottky clamp prevents the transistor from going into saturation. If an attempt is made to saturate this transistor by increasing the base current, the collector voltage drops, diode, D, conducts, and the base-to-collector voltage is limited to about less than 0.5 V. Note that in Fig.30 (b), the aluminium metallization for base lead is allowed to make contact also with the n-type collector region, but without an intervening n+ layer. This results in formation of metal semiconductor diode between base and collector. Since the Schottky junction is formed during the metallization process, the Schottky transistor requires the same number of process steps as does an npn transistor.

For practical Schottky diodes, the dominant reverse current component is the edge leakage current which is caused by the sharp edge around the periphery of the metal plate. To eliminate this effect, metal semiconductor diodes are fabricated with a diffused guard ring as shown in Fig.30 (b). The guard ring is a deep p -type diffusion and the doping profile is tailored to give the pn junction a higher breakdown voltage than the metal semiconductor contact, thus preventing premature breakdown and surface leakage.MONOLITHIC JUNCTION FETs Fig.31 shows some IC JFET structures. The n-channel JFET structure of Fig. 5.31(a) is compatiblewith npn transistor fabrication sequence. Another view of this n-channel JFET is shown in Fig. 32(a), where we note that the top p+ gate region extends beyond the n-type epitaxial layer region to make contact with the p-type substrate bottom gate. The n-type channel is thus completely encircled by the gate structure and the application of a suitably large negative voltage to the gate can pinch the channel off and reduce the drain source current to essentially zero. If the p+ top gate did not extend out to overlap the p-type substrate, n type channel would not be completely encircled by the gate structure and it would not be possible to cut off the drain-to-source current. The major drawback of the JFET structure of Fig.32 (a) is that the gate is connected to the p-type substrate, which is at ac ground potential. This restricts the use of this structure to only the common-gate configuration.

Fig. 5.32 (b) shows another n-channel JFET. Its fabrication is similar to the one just considered, the principal difference being in the top surface geometry. In this JFET the p+ top gate is in the form of an annual ring that completely encloses the drain region of the JFET. The only current path from source to drain will be underneath the p+ top gate. Therefore, the application of a suitably large negative voltage to the top gate can pinch off the channel and reduce the drain-to-source current to essentially zero.

Fig.31 (b) shows a p-channel JFET. The n+ gate region of this device extends out beyond the p+ source/drain/channel region to overlap the n-type epitaxial layer so that the gate completely encircles the channel. The same processing sequence can be used for this JFET as for the npn transistor. But, if this is done, the gate-to-channel breakdown voltage (corresponding to BVebo) will he down in the range 6 to 8 V and the full pinch-off of the channel may not be possible. As a result, specially tailored low concentration boron diffusion will be required to produce a higher gate channel breakdown voltage and lower channel doping, so that the channel can he pinched off at a voltage that is conveniently less than the breakdown voltage. This, however, requires some extra processing steps making the device more expensive.

A p-channel JFET employing boron-ion-implanted channel is shown in Fig.31 (c). Since the ion implantation dosage can be very precisely controlled, the JFET parameters, such as VP and IDSS, can be closely set to the values desired. This JFET uses the same processing steps as the npn transistor, with the addition of a photolithography, boron ion implantation and annealing step.

MOSFET TECHNOLOGY

MOS technology is the basis for most of the (LSI/VLSI) digital memory and microprocessor circuits. The most important advantage of MOS circuits over bipolar circuits for (LSI/VLSI) is that more transistors and more circuit functions can be obtained on a single chip with MOS technology. This is due to following reasons: (i) An individual MOS transistor occupies less chip area. (ii) The MOS fabrication process involves fewer steps. (iii)The dynamic circuit techniques that require fewer transistors to realize a given circuit function are practical in MOS technology but not in bipolar technology. (iv) One important feature of MOS circuits is that reduction in the internal dimensions of individual devices result in very sharp improvements in circuit speed.Comparison of Various MOS Techniques.p- Channel MOS (PMOS) Technology. This was the first MOS process which required special supply voltages such as -9 V, -12 V, etc., and operated only at very low digital data rate, i.e., 200 Kilo bits/sec to 1 Mega bits/sec.

n-channel MOS (NMOS) Technology. This technology and other improvements have resulted the LSI circuits that require only a single standard +5 V supply and operate at digital data rates up to 20 Megabits/sec.

A commonly used version of MOS technology is self-aligned silicon gate NMOS. Modem versions of this process employ a technique known as local oxidation to increase circuit density and performance. When such a process employs gate dielectric thinner than 1000 A and surface dimensions smaller than 5 m, designations such as HMOS (High-Speed MOS), SMOS (Scaled MOS), or XMOS are used by various manufacturers. A frequent addition to the process, particularly for important memory applications, is a second layer of polysilicon. Metal gate PMOS and NMOS are older versions of the MOS process that are not used much for new designs.

Complementary MOS Technology. The technique which provides both n-channel and p-channel devices in one chip, is complementary MOS (CMOS) which requires some increase in fabrication complexity and chip area compared to basic NMOS. The great advantage of CMOS digital circuits is that, it may be designed for essentially zero power consumption in steady-state condition for both logic states. Power is consumed only when circuits switch between logic states; average power consumption is usually much smaller than for NMOS circuits. CMOS is widely used for digital wrist watches and other battery operated equipment, and also used in computers and communication equipments.

CMOS employing silicon gate is more complex to manufacture but it offers significantly higher circuit density and better high-speed performance when used in VLSI. CMOS memories and microprocessors usually employ a silicon-gate process.

Among the additional variations of MOS technology are DMOS (double-diffused MOS) and its equivalent, DSA (diffusion-self aligned), VMOS (V-groove MOS), and SOS (silicon-on-sapphire) MOS. All of these claim performance and/or density advantages over standard processes. In all cases, the advantages gained from a change in device structure have proven to be relatively small compared to the improvements achieved by reducing internal device dimensions in standard processes.

Simple MOSFET Structures

Many device structures have been developed to improve MOSFET performance with higher response speed, lower consumption, more reliable operation, and higher power handling capability. MOS technology consists of three basic processes : p-channel, n-channel, and CMOS processes.PMOS Structure. The PMOS is the first device made in metal gate p-channel technology. Fig. 33 shows the cross-sectional view of PMOS structure. The starting material is a single crystal Si that is doped n-type with phosphorus or antimony with a doping level on the order of 1015 atoms/cm3. The first step is to grow a relatively thick oxide layer (1.5m). Then windows are etched for the source to drain diffusion. The source and drain regions are boron doped and are from 2 to 4m deep. The next step is to form the gate oxide, the one serving as the dielectric used for turning on and off the MOS device. Next, the entire circuit is metallized and etched so that there is metal over the gate, drain, and the source. For this Al is used. The meal layer is 1 to 2 m thick, and deposited using an electron- beam evaporator.

NMOS structure would follow a similar sequence. A NMOS structure is shown in Fig.34 and is similar to the device shown in Fig.33 except the n+ regions are diffused into the p-type silicon substrate.

PMOS vs. NMOS. n-channel MOSFETs have some inherent performance advantages over p-channel MOSFETs.(i) The mobility of electrons, which are carriers in the case of an n-channel device, is about two times greater than that of holes, which are the carriers in the p-channel device. Thus an n-channel device is faster than a p channel device. (ii) Since electron mobility is twice (say) that of hole mobility, an n-channel device will have one-half the on resistance or impedance of an equivalent p-channel device with the same geometry and under the same rating conditions. Thus n-channel transistors need only half the size of p-channel devices to achieve the same impedance. Therefore, n-channel ICs can be smaller for the same complexity.(iii) An n-channel junction can have smaller capacitance. This, in turn, improves its speed.

The n-channel device has following problems in the device processing. (i) Most of the mobile contaminants are positively charged. Since NMOS operates with the gate positively biased with respect to the substrate, these ions collect along the oxide-silicon interface. This charge causes a shift in Vth. Also, there is fixed positive charge at the SiSiO2 interface resulting from various steps of the manufacturing process. This also shifts the threshold voltage. Both these charges have tendency to make the device normally on. These two charges exist in PMOS device too, but the positive ions are pulled to the AlSiO2 interface by the negative bias applied to gate. There, they cannot affect the device threshold severely.(ii) It is difficult to make an n-channel device that is off at zero gate voltage. PMOS circuits have following advantages:

1. PMOS technology is highly controllable,

2. It is low cost process3. It has good yield and high noise immunity.

NMOS IC Process

There are a large number and variety of basic fabrication steps used in the production of modern MOS ICs. The process could be designed for NMOS or PMOS or CMOS devices. The gate could use metal (as discussed in previous section) or polysilicon (as described in this section for NMOS device). The substrate could be bulk silicon or silicon-on-sapphire (SOS). Finally, there are variations in the techniques to isolate the devices in the wafer to avoid parasitic transistors. We have already described briefly the metal gate (i.e., Al-gate) MOS structure in previous section. We now describe the silicon-gate process that is most popular. The fabrication sequence of n-channel MOS IC is shown in Fig. 35(i) A thin layer of Si3N4 is deposited on entire wafer surface by chemical vapour deposition (CVD).The first photolithographic step defines area where transistors are to be fabricated. The Si3N4 is removed outside the transistor areas by chemical etching. The impurity, boron, is implanted in the exposed regions to suppress unwanted conduction between transistor sites. Next, SiO2 layer of about 1m thickness is grown in these inactive or field regions by exposing the wafer to oxygen in an electric furnace. This is known as selective or local oxidation process. The Si3N4 is impervious to oxygen and thus inhibits growth of the thick oxide in the transistor regions.(ii) Next, the Si3N4 is removed by an etchant that does not attack Si02. A layer of oxide about 0.1 m thick is grown in the transistor areas. Then a layer of poly-Si is grown over entire wafer by CVD process. The second photolithographic step defines the desired patterns for gate electrodes. Undesired poly-Si is removed by chemical or plasma etching. An n-type dopant, such as phosphorus or arsenic, is introduced into the regions that will become the source and drain of MOS device. For this, diffusion or ion implantation is used. The thick field oxide and the poly silicon gate are barriers to the dopant, but in this process, the poly-Si becomes heavily n-type.(iii) Again, an insulating layer, SiO2, is deposited by CVD process. The third photolithographic step defines the areas in which contacts to the transistors are to be made, as shown in Fig. 35 (c). Chemical or plasma etching selectively exposes bare silicon or poly-Si in the contact areas.(iv) For interconnection, Al is used. The fourth masking step patterns the Al as desired for circuit connections as indicated in Fig. 35 (d).

The final steps of the process are identical to those described for bipolar transistor ICs. Above process is the simplest possible. For advanced processing of NMOS and CMOS, 7 to 12 masking steps are required.

Control of Threshold Voltage

It is very important to have adjusting facility for the value of Vth because it determines the requirements for turning the switch on or off. Some applications require not only a low value of Vth, but also a precisely controlled value to match other devices in the circuit. A low Vth offers following benefits :(i) Low Vth means operation with lower power supply voltages. This means lower cost power supplies, and lower system cost.(ii) Low Vth is directly compatible with bipolar ICs, it requires and produces the same input and output signal swings. This provides design flexibility. Also one need not worry about level shifting or interfacing.(iii) Low signal voltages possible due to low Vth, also imply higher operating frequencies. If a voltage only has to swing between 0 and 5 V, it can change state faster than a voltage swinging between 0 and 10 V can.(iv) Low voltage swing also results in low power consumption, thus improving the speed-power product, a figure of merit for digital logic gates.

Low threshold voltage is obtained not only by using thin gate oxide,Threshold voltage of NMOS device depends on VTh=ms + 2F+Qb/Cox Qss/Cox...(.9)

The different methods of threshold voltage control is as bellow:

1.By controlling all the terms in the above equations.All of the terms in this equation can be controlled to some extent. The ms, work function difference existing between the gate metal and silicon is determined by the choice of gate material; F, equilibrium electrostatic potential in a semiconductor (Fermi level) depends on the substrate doping; Qss, the charge density in the oxide at the silicon interface, can be reduced by proper oxidation methods and by using Si grown in the orientation. For most NMOS technologies, the silicon will be lightly doped p-type (~ 1015 atoms/cm3). The charge Qb in Eq. (9) can be adjusted by doping the substrate. The gate oxide capacitance Cox depends on the thickness and the dielectric constant of the oxide material. To obtain a low value of VTh a thin layer of oxide is used in the gate region of MOSFET to increase Cox = ox/tox. Referring to Fig.35 (d), although a low value of VTh is desirable in the gate region, a large value of VTh is needed between devices. For this a thick field oxide region is provided which together with channel stops serves to isolate the active region (i.e. transistor region) from neighbouring active region. The value of Cox, can also be controlled by varying ox.

2.By Ion Implantation. Ion implantation is very useful technique to control threshold voltage. This technique provides precise control over impurities to be introduced. Thus, control of Vth is possible by controlling the term Qb appearing in Eq. (9). A typical VTh adjustment requires only about 10 sec of implantation for each wafer, and therefore this procedure is compatible with large-scale production. If the implantation is continued to higher doses, VTh, can be moved past zero to the depletion mode. This capability provides considerable flexibility, by allowing enhancement and depletion mode devices to be fabricated on the same chip. For example a depletion mode transistor can be used instead of a resistor as a load element for the enhancement device. The substrate bias effect given by the term (Qb/Cox) in the Eq. (9) is also called body effect. This effect increases VTh for either type of devices.

3. Channel Doping. For a given gate material and oxide thickness; the channel doping can be chosen to give the desired Vth .The channel doping should, however, be carefully controlled. If it is too high, it can cause a reduction of carrier mobility at the surface and if it is too low (depending on the drain junction depth and channel length), the drain electric field may punch through to the source, i.e., the depletion regions of the source and drain may nearly touch each other.

4.A shallow implant is sometimes used to adjust the threshold voltage. Boron implant may be used to raise VTh or phosphorus (or As) implant to reduce the Vth. The phosphorus or arsenic implant will compensate the surface and, depending on the dose, can actually create a junction beneath the gate oxide. This would be the case if a depletion-mode MOSFET is fabricated.

Silicon-Gate Technology

The fabrication process is as described in Fig.35 (d) is redrawn as in Fig. 5.36 for convenience. In the structure shown in Fig.36, silicon gate is used in place of Al metal gate used in conventional MOS structures. The silicon gate is made of heavily doped poly-crystalline silicon (polysilicon), either p or n type depending on PMOS or NMOS device (n-type in present case).The polysilicon gate MOS structure, or commonly referred to as silicon gate MOS structure, has following advantages :(i) The silicon gate made of polysilicon has a work function which is less than that of the aluminium used in conventional MOS structure. The difference between the work functions of the gate and the semiconductor is less, and this reduces VTh directly.

(ii) Polysilicon gate can withstand the high temperatures used in the diffusion process, so that the gate can now serve as a diffusion mask (self-alignment feature). This results in the reduction of overlap capacitances (Cgs and Cgd)(iii) Silicon gate MOS technology is very useful for VLSI fabrication, because it provides three layers of interconnection: metal, polysilicon, and diffusion.(iv) It is a stable process and provides possibility of mixing both bipolar and MOS circuits on the same substrate.(v) It provides about 50% increase in the speed over silicon nitride structure which was developed before silicon gate structure.

Though the silicon gate technology is more complex than metal gate technology, its unique advantages over metal gate outweigh this limitation. The major disadvantage of polysilicon gate is that the resistance of the gate may contribute to the RC delay of signals that are routed along it.

Source/Drain Formation. The n+source/drain regions of the NMOS device should have as low resistance as possible. For VLSI applications device dimensions should be as small as possible. This is achieved by providing shallow junctions. Hence As is used as a dopant for source/drain formation because of its high solubility and low diffusion rate. Source/drain implants are in the high dose range (typically 1015 to 1016 atoms/cm2) to produce low resistance source/drain regions.

Features of Silicon Gate MOS Structure. The distinguishing features of silicon gate MOS structure process are that it is self-aligning, creates depletion MOSFET (used as load in place of passive resistor), has two layers of interconnect and a special structure called buried contact to connect between polysilicon and diffusion wire, produces high-functional density chips. The device also has good power and speed performance. It has been one of the most widely used processes and is a step toward the evolution of bulk CMOS process which is dominating the other MOS processes.

One important characteristic of the enhancement mode NMOS structure is use of silicon nitride in place of silicon dioxide. This is used for two reasons as follows (i) It is more impervious to the dopants used than silicon dioxide, thus making it better mask.(ii) It also acts as a shield to prevent oxidation of the active or transistor regions (regions where MOS devices are produced) during field oxide growth. Thus, it permits local or selective oxidation.

Self-Aligned Gate Feature.Fig. 37 shows the part of a conventional metal gate MOS structure. For the device to be turned on, a conducting channel (inversion layer) must be produced over the entire distance between the source and drain areas. Therefore, the gate electrode must extend all the way between the source and drain areas. To allow for possible mask registration errors, the gate is designed to overlap the edge of the source and drain regions by a small amount. This overlap is similar in nature for both regions ; hence only a part of the structure is shown in the figure to clearly show the overlap. If the overlap is made too small, no overlap may result by a misalignment of masks, and no conducting channel is formed even after application of appropriate voltage to the MOSFET gate. If the overlap is made too large as a precaution against possible misalignment, parasitic capacitances or overlap capacitances between the gate and source (Cgs) and the source and drain (Cga) become too large, slowing down the speed of the MOSFET. The overlap is thus unavoidable and its value is often in the range of about 5 m. This makes small overlap capacitance of the order of 1 to 3 pF. The Cga is of particular interest since it represents a feedback capacitance from output (drain) to input (gale) and its effect on the input capacitance of the MOSFET is increased by the Miller effect.

The self-aligned gate feature of silicon gate structure of Fig.36 solves this problem by making the desired overlap accurately without using a mask, because the silicon gate (using polysilicon) itself acts as a mask during the diffusion of the dopants into the source and drain areas. Thus, silicon gate mask determines the overlap between the silicon gate and the diffusion regions accurately. Hence we have a self-aligned gate structure. This feature provides accurate control of overlap thus minimizing the overlap capacitance. The n+ source and drain region in Fig.36 are usually obtained by ion implantation (instead of diffusion). This further reduces the overlap capacitances. The n+ dopants are able to penetrate the thin gate oxide, but are blocked by the thick field oxide and polysilicon gate. The gate material thus serves as an implantation mask such that source and drain regions effectively terminate right under the edges of the gate so that the overlap capacitance is thereby minimized. The annealing of the ion implantation takes place at a relatively low temperature in the range 400 to 500C such that the lateral diffusion of the implanted dopant ions underneath the gate is negligible.

Isolation Between MOS Devices

In a MOS IC structure, isolation between MOSFET devices is accomplished by limiting the conduction of the parasitic transistor that occurs between two neighbouring transistors. Referring to Fig.38, we find that some p-channel MOSFETs share a common n-type silicon substrate. The transistors (or active regions) are isolated from neighbouring transistors by field or passive regions. In the field regions the gate oxide, usually called field oxide is much thicker than the gate oxide of transistor. Typically field oxide is 10 times thicker than gate oxide. When a negative voltage applied to the gate (Fig. 38) exceeds VTh, a p-type surface inversion layer underneath the gate oxide is produced. This acts as a conducting channel between p+ source and drain. The voltage required to invert the n-type silicon under the thick field oxide will be very much greater than the gate threshold voltage, which is generally in the range -2 to-10V. The voltage required to invert the n-type silicon underneath the field oxide will be in excess of maximum negative voltage in the circuit, so that the metallization on top of the field oxide will not be able to produce an inversion layer. There will thus not be any p-type conducting channels formed between adjacent MOSFETs (i.e., active regions). Therefore the MOSEEIs or active regions are self-isolating and no special isolation diffusion or isolated regions are necessary as in the case of bipolar IC fabrication. There is usually no problem with device isolation in PMOS structure, but NMOS structure offers some problems, especially on the more lightly doped substrate. Positive ions, such as Na+ and K+, trapped in the oxide can act to reduce the threshold voltage such that conducting channels may be formed between the various NMOS devices. To prevent this, p+ guard rings or "channel stoppers" may be used around the NMOS devices. The channel stops provide alternative means to field doping. In this, bars of heavy dopings are diffused or implanted between the devices. They prevent accidental formation of inverted channels between devices. Some guard ring structures for NMOS devices are shown in Fig.39. The masking and diffusion used in forming channel stops with sufficient distance allowed between the stops and the nearest transistor, increase the area required between devices. Thus, MOS structure with channel stopper occupies more silicon surface real estate as compared to structures employing field doping. However, field doping has its limitation in that the breakdown voltage of the source and drain junction is reduced by the more heavily doped field region. Therefore it is necessary to control the field doping carefully to increase Vth appropriately without significant lowering of the junction breakdown voltage. Ion implantation, therefore, is employed for such close control.

Typical MOSFET Structures for Isolation in VLSI Chips

Fig.40 shows three structures which provide isolation in VLSI chips. These structures, in fact, employ three possible approaches to growing the isolation field oxide. Fig..40 (a) shows the local oxidation technique. The structure in Fig. 40 (b) uses a simpler technique, consisting of growing a thick oxide everywhere, then cutting windows where the active MOSFET devices will be formed. In the structure of Fig. 40 (c) the silicon is partially etched before the local oxidation is performed to recess the field oxide. The goal in all these isolation schemes is to make the parasitic transistor have as high a threshold voltage as is practical without adversely affecting the transistor characteristics of the active device.

MONOLITHIC RESISTORSMonolithic resistors can be classified into five types namely (i) Diffused resistors (ii) Bulk or epitaxial resistors (iii) Pinched resistors

(iv) Ion implanted resistors, and (v) MOS resistors.The monolithic resistors suffer from loose tolerances and have poor temperature and frequency characteristics compared to thin film resistors. Furthermore, the permissible range of resistance value is somewhat limited by the requirement imposed on resistivity by the bipolar transistor. In MOS technology, the polysilicon layer is sometimes used. The n-type substrate of the PMOS transistor in CMOS fabrication is also employed for realizing resistors.Diffused Resistors

Diffused resistors are formed by the bulk resistance of a diffused region. Generally one diffusion layer is used. In some cases a combination of two diffused layers is used. The layers available for use as resistors include the base diffusion and the emitter diffusion. The choice of layer generally depends on the value, tolerance, and temperature coefficient of the resistor required. Base Diffused Resistor. The structure of a typical base diffused resistor is shown in Fig. 60. The resistor is formed from the p-type base diffusion for the npn transistors and is situated in a separate isolation region The epitaxial region into which the resistor structure is diffused must be biased in such a way that the pn junction between the resistor and the epi-layer is always reverse biased. For this reason a contact is made to the n-type epi- region as shown in Fig. 60 and this is connected either to that end of the resistor that is most positive, or to a potential that is more positive than either end of the resistor. The sheet resistance is very convenient for specifying thin semiconductor layers used to form resistors. In Fig. 61, if the width W equals the length L, we have a square L x L of material with resistivity , thickness t, and cross-sectional area A = Lt. The resistance of this conductor (in ohms per square, often indicated as /), is Rs= L/Lt = /t

We note that Rs is independent of the size of the square. The resistance of the structure as shown in Fig.60 can be written as R=(L/W) Rs...(15) where L is the resistor length and W is the width. The base sheet resistance, Rs, lies in the range 100 to 300 ohm per square and thus resistances in the range 50 ohms to 50 k-ohm are practical using the base diffusion. The resistance contributed by the "club heads" at each end of the resistor can be significant, particularly for small values of L/W. The club heads are required to allow space for ohmic contact to be made at the ends of the resistor.

Emitter-Diffused Resistors

Emitter-diffused resistors are designed in the same manner as base diffused resistor. The cross- sectional view of the emitter resistor is shown in Fig.62. Here n+ diffusion forms the body of the resistor isolated by base region. The impurity distribution is of erfc type, hence the calculation of average resistivity should follow erfc profile. Since the sheet resistance of this diffusion is in the 2 to 10 ohms/square range, the emitter-diffused resistors are useful where small value resistors are required. Typical values are in the range 10 to l K. These resistors are widely used to provide a cross under beneath an Al-metallization interconnection..

Characteristics of Diffused Resistors. Since the sheet resistance of the base and emitter regions is fixed by the fabrication process, the value of these resistors can be controlled only by L and W. The minimum practical width, W, is limited to about 5 m. This limit is put by photolithographic considerations. The smaller width is also necessary to minimize chip area. The tolerance which results from profile variations and surface geometry errors is as high as 20 percent of the nominal value with ratio tolerance of 2 percent for minimum width geometry. For resistor widths in the order of 50 m, matching tolerance is about 0.2 percent. Therefore, in the design of IC, resistor ratios are utilized rather than their absolute values. Length of resistor can also be controlled to control the resistor value. To increase the resistor value, we can increase its length. By folding the resistor path back on itself, the length can be increased appreciably without utilizing excessive chip area. The temperature coefficient of resistance TCR is TCR = (1/R) dR/ dT...(16)

For base-diffused resistors, TCR is in the order of 2000 ppm/C (parts per million per degree Celsius) = 2x 10-3/C = 0.2 percent/C. TCR for emitter-diffused resistors is, typically, 600 ppm/C.

Large-value resistors will generally take the form of a mendering pattern as shown in Fig. 63.

Epitaxial Resistors

The epitaxial or bulk resistor is fabricated using epitaxial layer of the bipolar npn transistor. It is also referred as collector resistor for obvious reasons. The epitaxial resistor of Fig. 66 offers a high sheet resistance in the range of 1000 to 10000 ohms/square. Hence it is possible to obtain higher value resistors by using the epitaxial layer. The resistor values obtainable are much higher than those obtainable with base diffusion layer because the latter has smaller sheet resistance. Also, epitaxial layer resistivity calculations are easy because of uniformly doped epi-layer. Epitaxial resistor is defined by the isolation diffusion which surrounds the resistor. These sidewall effects become important, and, to maintain accuracy of resistance values, the isolation diffusion must be carefully controlled. The temperature coefficient of epitaxial resistor is considerably larger than the diffused resistor due to strong temperature dependence of mobility for low impurity doping. The temperature coefficient of resistance is in the range 3500 to 5000 ppm/C. The epitaxial layer also exhibits large tolerance range or standard deviation. This is due to the variations in the epitaxial layer thickness and doping level. The tolerance of the resistor is also poor.

Pinched Resistors

Base Pinched Resistor. The sheet resistant obtainable from collector diffusion is more than that obtainable from base diffusion. To fabricate large value resistors in small area one must decrease the impurity concentration and make thinner regions so that conductance will be lower.In Fig. 67 (a), the base diffusion profile is shown. We observe that concentration of impurities is very large near the impurities from the surface and much smaller near the surface. If one tries to remove impurities from the surface down to point A shown, it is possible to satisfy requirements (i) and (ii) as above. One can also prevent mobile carriers to participate in the current flow, which are present upto point A. This can be done easily by forming a junction at A. Thus the current path is confined between junction A and B. It is also to be noted that to form additional junction such as A, no extra process step is necessary because the diffusion carried out for forming emitter can also be used to form this junction (A). The material between the origin (0) and A will be then n-type, between A and B it will be p-type, such a resistor is called a pinched resistor. It is shown in Fig.67(b). It is to be noted that the n+ emitter diffusion-must everywhere overlap the body of the resistor in order that the resistor current path be confined to the narrow channel between A and B. Application of dc reverse bias voltage between the p-type resistor body and the surrounding n-type island causes the junction depletion layer to extend into the resistor, and `pinch' the effective resistor cross-section. This phenomenon is quite similar to junction gate FET.

The pinched resistor is isolated by reverse biasing the emitter-base and collector-base junctions, which is done by connecting the n-type regions to the most positive end of the resistor.

The pinching effect can also be interpreted in another way. When n-type emitter diffusion is introduced in the base diffused resistor, the n-type material does not contribute to the conduction because to do so, the current from contact 1 to contact 2 in Fig. 67 (b) would have to flow through np diode at contact 2 in the reverse direction, i.e., only the very the small diode reverse saturation current passes through the n-emitter material. This has the effect of reducing the conduction path cross-section of the p-material, i.e., pinching which results in increase in resistance. The sheet resistance because of pinching is in the 5 to 10 K-ohm per square range. Hence very large value (> 50 K-ohm) resistors can be fabricated. However, their exact values are not highly controllable (about 50% with a 10 percent matching tolerance). The TCR is in the range 3000 to 5000 ppm/C due to lightly doped resistor material. Pinched base diffused resistors are nonlinear since the resistance depends on the impressed voltage, as it happens to the channel resistance of JFET. One more significant drawback is that the maximum voltage that can be applied across the resistor is limited to around 6 V because of the breakdown voltage between the emitter-diffused top layer and the base diffusion. Nevertheless, this type of resistor is widely used in applications where the large tolerance and low breakdown voltage are not significant drawbacks.

Pinched Epitaxial Resistor. The low operating voltage of pinched base diffused resistor permits its use in low-voltage biasing applications across a forward-biased base-emitter junction. However, such a resistor cannot be used in circuits where a small bias current is to be derived directly from the power supply voltage using a large-value resistor. Though epitaxial resistor can be used but it displays large TCR due to light doping in the resistor body.

A still-larger sheet resistance can be obtained by putting a p-type base diffusion over the top of an epitaxial resistor as shown in Fig. 68. The p-type base constricts the conduction path in the epitaxial layer, thereby increasing the resistance. The structure is similar to a JFET, in which the p-type base is tied to the substrate and the pinch-off voltage varies depending on epi-thickness and doping. The junction between the p-base and the epitaxial layer is essentially the collector-base junction of a transistor. This junction has a higher reverse breakdown voltage than does the emitter-base junction

Pinched epitaxial resistors have following characteristics: sheet resistance : 220 K ; TCR: 4000 ppm/C ; absolute tolerance : 50%, and ratio tolerance : 10%,

Ion Implanted Resistors

Ion implantation is very often used to form base and emitter. Hence this process is also used to form resistors having similar structures as discussed earlier. A typical structure is shown in Fig.69. Implanted n-type resistors can be fabricated by using a MOS process similar to that used to form the channel in an NMOS depletion device. Ion-implanted resistors are fabricated having resistance values comparable to those achieved with base diffusion. However, tolerance and temperature variation are well below those obtained for diffused resi