Modeling, Simulation, and Analysis of Novel Threshold

Research ArticleModeling, Simulation, and Analysis of Novel Threshold VoltageDefinition for Nano-MOSFET

Yashu Swami and Sanjeev Rai

Department of ECE, MNNIT Allahabad, Allahabad 211004, India

Correspondence should be addressed to Yashu Swami; [email protected]

Received 13 July 2017; Revised 20 August 2017; Accepted 9 October 2017; Published 26 November 2017

Academic Editor: Paresh Chandra Ray

Copyright © 2017 Yashu Swami and Sanjeev Rai.+is is an open access article distributed under the Creative Commons AttributionLicense, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

+reshold voltage (VTH) is the indispensable vital parameter in MOSFETdesigning, modeling, and operation. Diverse expoundsand extraction methods exist to model the on-o8 transition characteristics of the device. +e governing gauge for e:cientthreshold voltage de;nition and extraction method can be itemized as clarity, simplicity, precision, and stability throughout theoperating conditions and technology node. +e outcomes of extraction methods diverge from the exact values due to variousshort-channel e8ects (SCEs) and nonidealities present in the device. A new approach to de;ne and extract the real value of VTH ofMOSFET is proposed in the manuscript. +e subsequent novel enhanced SCE-independent VTH extraction method named“hybrid extrapolation VTH extraction method” (HEEM) is elaborated, modeled, and compared with few prevalent MOSFETthreshold voltage extraction methods for validation of the results. All the results are veri;ed by extensive 2D TCAD simulationand con;rmed analytically at various technology nodes.

1. Introduction

Ceaseless curtailing of integrated circuit technology alongwith the accuracy of threshold voltage managementmethods and depletion in short-channel e8ects (SCEs) areemphasizing the threshold voltage to exceptionally lowvalues. It is necessary to extract the precise thresholdvoltage (VTH) for appropriate performance of the device.Flawlessly evaluated threshold voltage is mandatory todeliver correct and genuine gate control in channel con-ductivity and output characteristics of the device [1, 2].Minor millivolt inaccuracy cannot be shirked because itmay trigger grievous faults in the circuit practicality.Precisely for high-speed sturdy analog circuit nanoscaledesign, accurate threshold voltage evaluation is vital andcrucial for accurate device behavior [3–5]. +e extractedthreshold voltage assists the process of device matchingtoo. +reshold voltage is often exerted in evaluation andanticipation of device operation. +e value of VTH isoften utilized in examining the discrepancy because ofmanufacturing process technological parameter Ductua-tions. Additional utilizations of threshold voltage value are

compiled as to appraise reliability elements like radiationdamage, hot carrier, stress, temperature instability, andageing degradation.

Generally, the VTH value is extracted speci;cally from thedevice transfer characteristics [6, 7]. +e functional drainvoltage (VDS) exaggerates several SCEs like DIBL, VTH roll-o8,punchthrough, surface scattering, velocity saturation, impactionization, and hot electron e8ect. No particular evaluativeanalytic locus can be acknowledged as VTH in the devicetransfer characteristic curve due to subthreshold leakagephenomenon, hence causing ambiguity in the VTH extractionprocess. In the curve, weak inversion section demonstratesexponential divergence, whereas strong inversion section in-dicates linear/quadratic divergence. Conversely, the VTH isdistinguished in the midst of weak and strong inversiontransition sections. +reshold voltage likewise hinge on nu-merous device parameters (gate width, gate overlap, gatelength, biased bulk, temperature, etc.) and process technologylimitations (Cox, Tox, doping concentration, etc.), making thede;nition and extraction extrastrenuous [8].

In consideration of the above, the manuscript presentsa new simple approach to de;ne and extract the VTH

HindawiJournal of NanotechnologyVolume 2017, Article ID 4678571, 9 pageshttps://doi.org/10.1155/2017/4678571

mailto:[email protected]

https://doi.org/10.1155/2017/4678571

of MOSFET. �e corresponding novel enhanced SCE-independent VTH extraction method named “hybrid extrap-olation extraction method” (HEEM) is further illustrated andcompared with few prevalent customary MOSFET VTH ex-traction methods for validation of the results and claim thepredominance of the HEEM over other extraction methodswith minimum in�uence of short-channel e�ects (SCEs) andother second-order e�ects like DIBL, VTH roll-o�, punch-through, surface scattering, velocity saturation, impact ioni-zation, and hot electron e�ect. Rest of the paper is organized asfollows. Section 2 presents the conventional threshold voltagede�nitions of MOSFET. Section 3 expounds the HEEM.Section 4 implements the HEEM concept on the test deviceand conventional MOSFET models. Furthermore, Section 5presents the simulation results and validation of the proposedmethod and evaluation and analysis of discrete sub 45 nmtechnology nodes. Finally, concluding remarks and en-hancement in the �eld are presented in Section 6.

2. Conventional Threshold Voltage Definitionsof MOSFET

�e conventional de�nition of the threshold voltage ofdoped semiconductor devices states that the gate voltageproduces a surface potential equal to twice the fermi po-tential (∅B) in the bulk of the semiconductor [9]. Mathe-matically, the threshold surface potential (ΨTH) can bearticulated as

ΨTH � 2∅B � 1βln

p0

n0( ) � 2

βln

NA

ni( ), (1)

where β represents the inverse of thermal voltage and p0 andn0 are the equilibrium hole and electron densities, re-spectively [10, 11].NA and ni are the substrate doping densityand intrinsic free-carrier concentration, respectively.

Experimentally, it is observed that the modeled con-ventional de�nition does not agree well with the VTH valueextracted from the transfer characteristic curve. Conse-quently, the enhanced de�nition was proposed for hotchannel devices by including the MOSFET second-ordere�ects. �e proposed empirical term (6/β) was added to (1)for a typical range of MOSFET substrate doping concen-trations and oxide thickness. �e improved empirical def-inition is modeled as

ΨTH ≈ 2∅B +6β. (2)

�e conventional de�nition was also modi�ed for long-channel devices by adding the corresponding empiricalparameters to (1). �e improved expression was developedby comparing the inversion and depletion charge terms ofthe device. Hence, the modi�ed long-channel empiricalde�nition is modeled as

ΨTH ≈ 2∅B + 1β

( )ln 2β∅Bτ

( ), (3)

where the empirical parameter τ � 10 is valued for thetypical range of substrate doping concentrations and oxide

thickness analogous to long-channel devices. We can easilyextract the subsequent threshold voltage (VTH) from thethreshold surface potential (ΨTH) of n-channel MOSFETusing the standard basic threshold voltage MOSFET modelexpression.

�e modi�ed conventional de�nitions proposed in[10, 11] are based on the concept of intersection of the twoasymptotes of the surface potential for the depletion andstrong inversion region surface potential, whereas theenhanced HEEM concept is a current-based approachfor evaluating VTH (elaborated in the Section 3). Hence,it is easier to model and simulate at nanolevel andmore accurate to de�ne even for upcoming slim ballistictransistors.

�e concept proposed in [10, 11] works well for long-channel devices but deviates to give accurate results inextracting VTH for nano-MOSFETs with thin oxide layersand high doping densities. It also fails to generate sharpsurface potential curves for nanodevices, hence asymptoticVTH point for nanodevices. �e model equations of [10, 11]are approximate asymptotic VTH de�nition. It does not havean explicit expression for threshold voltage and gives con-siderable errors in predicting the VTH value at nanoleveltechnologies. Furthermore [10, 11], study includes only theclassical e�ects with lot of approximations. �e enhancedHEEM logic is applicable for both short-channel and long-channel devices and gives more accurate results. �e HEEMlogic generates sharp curves even working at nanotech-nology node; hence, more accurate well-de�ned values areobtained. Simulation results validate the results shown inupcoming sections.

3. ANovel Approach: Hybrid ExtrapolationVTH

Extraction Method

�e new simple straightforward approach of extracting thethreshold voltage of nano-MOSFETs is based on globallyaccepted drift-di�usion model (DDM) and latterly de-veloped ballistic, quasi-ballistic model. �e transfer char-acteristics of MOSFET exemplify that the di�usion currentgoverns the subthreshold region, while the drift currentdominates in the linear-saturation region. �e net entirecurrent is equal to the summation of drift current anddi�usion current. However, if potential across the drain tosource terminals (VDS) is zero, the net current �ow is also nilas no current streams across the equipotential terminalseven after biasing the gate terminal [12–14].

�e constant current threshold voltage extractionmethod has an unclear description of critical drain current(IDCRITICAL) liable on the technology employed. Linearextrapolation method, quadratic extrapolation method, andtransition method results are highly in�uenced by manysecond-order e�ects like mobility degradation, short-channel e�ects, and extrinsic resistance e�ects [6, 7, 15].Second derivative method, third derivative method, Ghi-baudo method, reciprocal H-function method, and trans-conductance to current ratio method are extensivelyexaggerated by noise. �e VTH de�nitions are also not basedon ideal VTH de�nition condition [16]. �e match point

2 Journal of Nanotechnology

method is seldom used as it is more laborious and moretime-consuming. 5% deviation value is also an ambiguousdenition of threshold voltage calculation in match pointmethod [17]. In normalized mutual integral di�erencemethod and normalized reciprocal H-function method, theaccurate evaluation of maxima in wide ranges makesthe VTH extraction process tough and problematic [18, 19].�e HEEM has the competence to accurately determine thethreshold voltage (VTH) of MOSFET and totally remove ornullify the abovementioned �aws of the predened existingextraction methods.

For simplicity, we have only considered the n-channelMOSFET to illustrate this unique HEEM approach. Similaranalysis can be extended for p-channel MOSFET. Followingassumptions are made purposely: the device is considered tobe laterally symmetrical and the source, drain, and bulkterminals are considered to be grounded; hence, no potentialexists amongst the corresponding terminals, the gate is madeof n+ polysilicon with work function q∅M � 4.24eV, theimmobile charge in the oxide near the oxide-semiconductorinterface has the same dispersal over both p and n regions,and the interface traps or interface states have the samedistribution for both the p and n parts of the device close tometallurgical junction.

With the drain and source terminals grounded, the gateterminal governs the charge in the channel. When a smallpositive-biased voltage is applied to the gate of n-channelMOSFET, the state within the channel will alter. �e freeholes present in p-type silicon are deterred, thus forminga depletion region in the channel. �is depletion region isformed over both lateral and vertical directions, that is,across the length and width of the channel. Increasingthe positive gate voltage further will eventually lead to thesaturation of the depletion depth. Once the saturation of thedepletion region is reached, additional gate voltage willentice negative mobile electrons to the channel surface [20].When adequate electrons have accrued in the channel area,the surface of the channel alters from the hole-dominated tothe electron-dominated silicon material and is said to haveinverted. Under this condition, a steering n-channel orinversion layer is formed under the gate between the two n+silicon materials, namely, source and drain regions. Addi-tional upsurge in gate voltage will only increase the surfacepotential of the channel gradually beyond 2ϕB, whereby theincreased gate voltage drops across the gate oxide. �eminimum gate voltage required to form the conductingchannel or an inversion layer underneath the surface iscalled as threshold voltage (VTH). Figure 1 represents the10 nm test device simulation results of drift current anddi�usion current components versus gate voltage (VGS) forVDS� 0.1 V. We can further classify the four MOSFET op-eration states as depletion region, weak inversion, moderateinversion, and strong inversion in reference.

�e drift-di�usion model (DDM) states that the totalcurrent across the channel is the sum of drift current anddi�usion current as [21] ITOTAL � IDRIFT + IDIFFUSION. �eDDM and even the Landauer approach (Boltzmann trans-port equation) in ballistic, quasi-ballistic nano-MOSFETmodels advocate that with the source and drain terminals

grounded (VDS � 0V), the total current �ow is zero becauseof the zero potential drop across the terminals. However, ifwe plot the discrete components of the total current versusgate voltage, we see nonzero values and are exactly equal butopposite in direction of �ow as both drift and di�usioncurrents balance each other [22]. �e drift and di�usioncurrent components literally equivalent but contrary inpolarity can be termed as junction current 1 (IJNSC) �owingbetween source and channel junction and junction current 2(IJNDC) �owing between drain and channel junction. Boththe junction currents would be equal due to the symmetricalapplied conditions and parameters. Hence, we can collec-tively denote both the junction currents IJNSC and IJNDC byIJNC. Gradually increasing the gate voltage from zero to highbias (VDD), the drift-di�usion current density and drift-di�usion current components (IDRIFT and IDIFFUSION) alsoincrease as shown in Figure 2. Consequently, we can con-clude that IJNC also increases with the increase in gate bias

Log ID

(A)

VGS (V)

IDIFFUSION

VTLIN

1E 4

1E 5

1E 6

1E 7

1E 8

1E 9

1E 10

1E 110.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

IDRIFT

Figure 1: 10 nm test device simulation results of drift current anddi�usion current versus gate voltage (VGS) for VDS� 0.1V.

5.0E7

5.0E7

0.0

0.01 0.02 0.03 0.04Distance along channel length (nm)

VGS = 0.3 V

VGS = 0.5 V

VGS = 0.7 V

VGS = 0.9 V

Curr

ent d

ensit

y (A

/cm

2 )Drift current

Diffusion current

Figure 2: Drift-di�usion current density along the channel lengthfor di�erent gate voltages with VDS� 0V.

Journal of Nanotechnology 3

terminal. However, ITOTAL remains zero because of thecontrary �ow direction of the distinct current components.Figure 2 justies the logic as it can be seen that the driftcurrent density is the same as the di�usion current densitybut opposite in polarity [23].

As per the assumptions and the applied conditions in ourHEEM, the subsequent IJNC value is nearly zero (negligible)in the subthreshold region. A linear/quadratic increase iswitnessed in the IJNC numerical value as the inversion layer isformed. Hence, we are able to e¦ciently extract vital VTH byplotting IJNC versusVGS. Extrapolation of the IJNC versusVGScurve at the in�exion point gives an accurate thresholdvoltage.�e threshold voltage is found at the intercept of thetangent in the in�exion point with the VGS axis.�e linearityof the curve allows an easy extrapolation for better results asseen in Figure 3(a). �e IJNC numerical value required forplotting the extraction curve is modeled in the subsequentsection for reference. However, the IJNC value can beextracted easily from the TCAD simulation tools also. �eIJNC �ow density contour plots along the channel length fordistinct gate potentials (VGS) are simulated and shown inFigure 3(b) of 10 nm n-channel MOSFET test device. We canclearly see no current �ow in the channel at VGS� 0V.However, contour of current �ow is observed at the source-channel junction and drain-channel junction at VGS� 0.5Vand increases with the gate bias (VGS� 1V).�e current �owcontour remains zero even at high gate bias (higher than thethreshold voltage) exactly at the channel length positionx� L/2 representing no current �ow between source anddrain terminals.

�e extraction procedure is autonomous of drain-biasedshort-channel e�ects, extrinsic series resistances, mobilitydegradation, slope factor variations, and channel lengthmodulation, allowing a direct accurate determination of thethreshold voltage. Hence, it is more e�ective and fast inextracting VTH for both short-channel and long-channel

devices. Exhaustive numerical simulations at various tech-nology nodes and analytical results to demonstrate theextraction procedure are used to certify the proposed logicwith conviction.

4. Implementation of Hybrid ExtrapolationExtraction Method

�e new hybrid extrapolation extraction method is imple-mented on test device and statistically evaluated using well-established MOSFET models. Comparison amid variousconventional extraction methods and the new proposedmethod is performed on both technology CAD simulationand measurement in order to endorse the new enhancedextraction technique and related theory [10–12]. As de-scribed, the enhanced extraction method is independent ofdrain-biased short-channel e�ects, extrinsic resistances,channel length modulation, and mobility degradation.Hence, it is more e�ective in extracting VTH for both short-channel and long-channel devices.

4.1. Execution of HEEM on Test Device. A basic square-sizedbulk NMOS structure is contemplated for TCAD execution.�e nanodevice is modeled with channel length (LG)�10 nm, gate oxide thickness (Tox)� 1 nm, bulk dopingconcentration (NBULK) � 1017 cm−3, and junction depth(Xj)� 8 nm. For generalization of the outcomes, uniformdoping is deemed all through the bulk [24, 25]. Gaussiandoping with the maximum limit of 1020 cm−3 is modeled insource and drain regions for realistic results, whereas theextensions are planted and doped with the concentration of1019 cm−3 to reduce the GIDL consequences. Source-drainextensions expand 2 nm underlap, making the channel as anenhanced controlled and conductive path. Various param-eters are considered to be steady in relation with the channel

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.90.8 1.00

5

10

15

20

25

30

35

IJNC

VGS (V)

Extrapolation

Junc

tion

curr

ent (I

JNC)

(uA

)

VTH

(a)(b)

Figure 3: (a) Hybrid extrapolation VTH extraction method (IJNC value versus VGS plot). Extrapolation of the IJNC curve extracts the VTHvalue. (b) �e IJNC �ow density (A/cm2) contour plots along the channel length (L) for distinct gate potentials (VGS� 0V, VGS� 0.5V, andVGS� 1V). Reference isoline represents the current �ow density (A/cm2).


length scaling (EOT�1 nm, NBULK� 1017 cm−3). �e phys-ical models deployed for unblemished outcomes includeballistic, quasi-ballistic, doping-dependent mobility withhigh-�eld saturation and degradation, Shockley-Read-Halland tunneling models, and analytical model for e�cacioustemperature-dependent extractions. �e model MOSFETincorporates the supply voltage of 0.9 V.

As per the set condition, VDS� 0V; hence, the proposedmethod will return a unique threshold value which can beconsidered as VTH of the device. �e extracted thresholdvoltage value is independent of short-channel e�ects likeDIBL and threshold voltage roll-o� and many other second-order e�ects instigated due to drain bias.

�e outcome of the hybrid extrapolation VTH extractionmethod for 10 nm test device and comparison with otherpredominant VTH extraction methods are shown in Table 1(refer Figures 4(a)–4(d)).

VTLIN represents the threshold voltage with MOSFEToperating in the linear region.�e extracted value is found toaccord with other recognized threshold extraction methods.�e minor variation of the outcomes of the other pre-dominant methods may be probably due to neglecting theSCE and second-order e�ects. �e validity of this newproposed HEEM was veri�ed for long-channel devices also.�e test device considered for the long channel is a square-sized uniformly doped bulk-driven n-channel MOSFETwith180 nm channel length. Most common extraction methodswere also applied to extract the threshold voltage in similarconditions. �e extracted values using HEEM were foundto accord with other recognized VTH extraction methods[24, 25]. �e outcomes of various extraction methods for180 nm test device are shown in Table 2.

�e VTH extracted value using HEEM is very close to thefew of the most popular VTH extraction methods. �eoverestimation of the other predominant methods may beprobably due to neglecting the second-order e�ects. Hence,we can conclude that the HEEM is equally e�ective for bothshort-channel devices and long-channel devices [26, 27].

4.2. Execution of HEEM on MOSFET Models. Di�usioncurrent is a type of current in a semiconductor instigated bythe variance of charge carrier concentration (holes and/orelectrons), whereas the drift current is due to the transport ofcharge carriers prompted by an electric �eld force exerted onthem. Di�usion current can be in the same or con�ictingdirection of a drift current. �e sum of di�usion current anddrift current collectively are designated by the drift-di�usionequation [28].

Four autonomous current mechanisms in our n-typeMOSFET test device are possible. �ese components are themajority carriers’ electron drift current and di�usion currentas well as the minority carriers’ hole drift current and dif-fusion current. �e complete current density is the sum-mation of these four components. For one-dimensionalinstance, we can inscribe the concept as [4, 5]

J � nqμnEx( ) + nqμPEx( )[ ] + qDndn

dx( )− qDp

dp

dx( )[ ].

(4)Equation can be generalized to three-dimensional for-

mat as

J � nqμnE( ) + nqμPE( )[ ] + qDn∇n( )− qDp∇p( )[ ], (5)where Dn and Dp are electron and hole di�usion coe�cients,respectively, n is the number of electrons per unit volume,global symbol q represents the electron charge, and μn and μpdenote the electron and hole mobility in the medium, re-spectively. �e electric �eld E � − dϕdx, where ϕ indicates thepotential di�erence. �e logic is expressed as

JTOTAL � JDRIFT + JDIFFUSION � nqμE + qDdn

dx. (6)

We also know D � μϕt as Einstein relationship onelectrical mobility. �ermal voltage (ϕt) � KT/q, with K asthe Boltzmann coe�cient and T representing temperaturein Kelvin. �us, substituting E for potential gradient in (6)and multiplying both sides with e−∅/∅t , we get

Je−∅∅t � qD

−n

∅t

d∅

dx+ dn

dx[ ]e−∅∅t � qD

d ne−∅∅t( )

dx. (7)

Integrating (7) over depletion region of channel-sourceP-N junction assuming xd as the depletion thickness, we get

J � qDne−∅∅t∫ e

−∅∅t( )dx �

qDnNae−∅Β∅t e

VIN∅t( )− 1[ ]∫ e

−∅1∅t( )dx , (8)

where Na and Nd characterize the doping concentrationof n region (source) and p region (channel), respectively.∅B is built-in barrier potential and VIN denotes inputvoltage.

WithØ1�ØB+ (Øi−VIN), the denominator of (8) can besimpli�ed. We know ∅ � −qNd/2εs(x−xd)

2.�erefore, the expression can be expressed as

∅1 �qNdx xd −

x

2( )εs

� ∅i −VIN( ) x

xd, (9)

where ϵs denotes the permittivity of the material.Since x≪ xd, the term (xd −x/2) ≈ xd.Using the above approximation in (9), we get

∫ e−∅∅t( )dx � xd ∅i −VIN( )

∅t, (10)

when (Øi−VIN) >Øt; we obtain the current due to di�usion.

Table 1: Comparison of VTH extraction methods for 10 nm testdevice.

Method VDS VTLIN

Hybrid extrapolation extraction method 0V 0.67VLinear extrapolation method (LEM) 0.1V 0.68VSecond derivative method (SDM) 0.1V 0.675VGhibaudo method (GM) 0.1V 0.6 VMatch point method (MPM) 0.1V 0.65V


�e net total current density can be described as

J � 2qDNa

∅t

��2qεs∅i −VIN( )Nd

√e−∅B∅t e

VIN∅t − 1( )[ ]. (11)

From (11), we can observe that current depends expo-nentially on the input voltage (VIN) and the barrier height (ØB).VIN can be written as a function of electric �eld intensity as

Emax ��2qεs∅i −VIN( )Nd

√. (12)

Manipulation and substitution in (11) gives

J � qμNaEmax e−∅B∅t e

VIN∅t − 1( )[ ]. (13)

From (13), one can observe that when zero input voltage(VIN) is observed, the drift current entirely balances thedi�usion current. Hence the net current �ow density at zero

potentialVIN is always zero as the source and drain terminalsare presumed to be grounded as per the assumptions andapplied conditions in our HEEM.

�e above outcome of HEEM can also be performedthrough the well-established MOSFET charge sheet model(CSM). We represent the CSM complete expression of draincurrent (IDS) valid for all the operating regions and con�rm

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

Dra

in cu

rren

t (I D

) (uA

)1.8E−31.6E−31.4E−31.2E−31.0E−38.0E−46.0E−44.0E−42.0E−40.0

0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1

gm (A

/V)

ID

gm

VGS (V)

Extrapolation

VTLIN

gm_max

(a)

VGS (V)

0.01

0.00

−0.01

−0.02

−0.03

−0.04

d2I D

/dV

GS2

(A/V

2 )

0.3 0.4 0.5 0.6 0.7 0.8 0.9

d2ID/dVGS2

Filtered curve

VTLIN

(b)

VGS (V)

0.008

0.006

0.004

0.002

0.0000.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

I D/g

m1/

2 (A1/

2 V1/

2 )

ID/gm1/2

Extrapolation

VLIN

(c)

−6

−8

−10

−12

−14

Log(I D

) (A

)

0.1 0.2 0.3 0.4 0.5 0.6 0.7VGS (V)

Log (ID)Extrapolation

5% deviation point

VTLIN

(d)

Figure 4: (a) Extraction of VTLIN using LEM for VDS� 0.1 V. (b) Extraction of VTLIN using SDM for VDS� 0.1 V. (c) Extraction of VTLINusing Ghibaudo method for VDS� 0.1V. (d) Extraction of VTLIN using match point method for VDS� 0.1V.

Table 2: Comparison of VTH extraction methods for 180 nm testdevice.

Method VDS VTLIN

Hybrid extrapolation extraction method 0V 0.575VLinear extrapolation method (LEM) 0.1V 0.585VSecond derivative method (SDM) 0.1V 0.585VGhibaudo method (GM) 0.1V 0.58VMatch point method (MPM) 0.1V 0.58V


the HEEM concept using the respective model. �e modeluses the source-end surface potential and drain-end surfacepotential to extract the complete drain current expression.

In the CSM, the channel depletion area is obtained underthe assumption that the substrate is uniformly doped (NB).We presume the source and drain junctions are geo-metrically symmetrical in shape with a radial junction depth(Xj), and the channel depletion area is linearized in terms ofonly source- and drain-end surface potentials. Xdms andXdmd represent the depletion depth across the channel asidethe source and drain regions, respectively. �us, the bulkcharge density can be obtained. Statistically, the CSMmodelequation of the net drain-to-source current can be repre-sented as follows [4, 5].

Let x be the horizontal position in the channel, measuredfrom the source end. If inversion layer current in lateraldirection at any position x is denoted by I(x), then we have

I(x) � IDRIFT(x) + IDIFFUSION(x). (14)IDRIFT(x) as drift current contribution and IDIFFUSION(x)

as the di�usion current contribution at point x.�e intricate CSM drain current can be modeled as

IDS �W

L( )μC′ox ΨsL −Ψs0( )[ VGB −VFB( )− 1

2ΨsL −Ψs0( )

−2c3

ΨsL +��ΨsLΨs0

√ + Ψs0( )Ψ1/2

sL + Ψ1/2s0( )

−ϕt 1 + c

Ψ1/2sL + Ψ1/2

s0( ) Ψ3/2sL −Ψ

3/2s0( )], (15)

with Ψs0 and ΨsL expressing the surface potential at channellength x� 0 and x� L, respectively. c denotes the body e�ectcoe�cient. W indicates the width of the channel. C′ox isoxide capacitance per unit area. VGB and VFB describe thegate-to-bulk voltage and �at band voltage, respectively.

As per the assumptions and the applied conditions inHEEM, ΨsL�Ψs0 (the source terminal and drain terminalare equipotential). �e channel depletion region area issymmetrical across the channel length around the sourceand drain region area due to the assumed balanced dopingand regular geometry. Hence, we can perceive from themodel (15) that the net current is always zero in the describedsituation. Consequently, in this state, we can further conclude

that the drift current totally balances the di�usion current; thatis, the drift current value is exactly equivalent to the di�usioncurrent value but with the contrary direction.

5. Simulation Results and Validation of theProposed Method

�eHEEM logic is explored and executed at 10 nmMOSFETIC technology along with discrete additional existing sub45 nm IC technologies. �e outcomes are corroboratedthrough immense 2D TCAD simulation and analyticallyrea�rmed using industry standard tools. Discrete PTmodelsdeveloped by the Nanoscale Integrations and Modeling(NIMO) Group at Arizona State University (ASU) areemployed to exemplify the outcomes [25]. �e models arecapable of capturing numerous second-order e�ects toforecast the accurate device characteristics [29–32].

�e validation of the new proposed hybrid extrapolationextraction method was accomplished by two-dimensional(2D) numerical simulations, and brief analysis was carriedout on both short-channel NMOS and long-channel NMOSdevices. First, using numerical simulations, IJNC was moni-tored as a function of the gate voltage (Figures 2 and 3(a)).IJNC has an exponential behavior for positive low gate voltagesless than VTH, which corresponds to the weak inversionconferring to the MOS theory. Further increasing the gatevoltage, we observe a linear/quadratic increase in IJNC cor-responding to the transition of the surface from weak tomoderate/strong inversion. �is transition is considered asthe de�nition of the threshold voltage of the device.

In the second phase of validation, the results of VTHextraction using HEEM was compared with other recog-nized threshold extraction methods, namely, CCM, LEM,SDM, GM, and MPM [15–18]. �e HEEM’s extracted VTHvalue was found to accord with the other referred extractionmethods. �e extracted VTH values are presented in Table 3.Compact meshing and larger added checkpoints can im-prove the extraction accuracy.

A number of existing VTH extraction methods were putforward, analyzed, and analytically compared their respectiveoutcomes with the presented HEEM concept.�e comparativeextracted VTH values of presented extraction methods weresimulated and analyzed in the same analogous conditions.Table 3 presents comparative VTH extraction values of HEEMalong with largely applied threshold extraction methods,namely, CCM, LEM, SDM, GM, and MPM for bulk-driven

Table 3: Comparison of the simulation results of VTH extraction methods for various sub 45 nm technologies.

Method10 nm TN 16 nm TN 22 nm TN 32 nm TN 45 nm TN

VTLIN VTSAT VTLIN VTSAT VTLIN VTSAT VTLIN VTSAT VTLIN VTSAT

CCM 0.355V 0.104V 0.463V 0.369V 0.479V 0.425V 0.440V 0.396V 0.433V 0.403VLEM 0.683V N.A 0.719V N.A 0.706V N.A 0.653V N.A 0.634V N.ASDM 0.675V 0.437V 0.7V 0.6V 0.675V 0.6 V 0.649V 0.552V 0.626V 0.578VGM 0.59V 0.51V 0.645V 0.575V 0.645V 0.56V 0.6 V 0.525V 0.6V 0.5VMPM 0.7V 0.55V 0.7V 0.625V 0.7V 0.675V 0.65V 0.675V 0.65V 0.675VHEEM 0.675V N.A 0.675V N.A 0.675V N.A 0.625V N.A 0.625V N.A


nano-MOSFETs at 10 nm IC technology along with discretesub 45nm IC technologies. +e VTH value was also evaluatedapplying PTmodels on test device at various IC technologies,namely, 10nm, 16nm, 22nm, 32nm, and 45nm IC tech-nologies [25, 32]. +e comparative outcome con;rms that theHEEM extracts the accurate threshold voltage results for bothshort-channel and long-channel devices. VTLIN and VTSAT inTable 3 represent the threshold voltage with MOSFET oper-ating in the linear region and saturation region, respectively.

6. Conclusion

+e robust analysis and comparison of various existing VTHextraction methods were employed to determine the VTHvalue test device. HEEM VTH logic was also employed insimilar conditions, manifesting the new extraction approachHEEM as the improved extraction method for direct de-termination of threshold voltage, superior with minimuminDuence of second-order e8ects like DIBL, short-channele8ect, VTH roll-o8, punchthrough, surface scattering, ve-locity saturation, impact ionization, and hot electron e8ect.It is very bene;cial and convenient for accurate extraction ofVTH for both short-channel and long-channel devices as it isbased on the physics of the device. +e other augmentationof this method can be listed as the threshold voltage outcomevalue is exclusive (VTH) for all operating regions unalikeoutcomes of other extraction methods that normally gen-erate VTH in the linear region (VTLIN) and VTH in thesaturation region (VTSAT). +e linearity of the IJNC versusVGS curve allows an easy extrapolation for better results. +eHEEM is independent of drain-biased short-channel e8ects,extrinsic resistances, mobility degradation, channel lengthmodulation, etc. Hence, it gives more precise results for bothshort-channel devices and long-channel devices.

Conflicts of Interest

+e authors declare that they have no conDicts of interest.

References

[1] M. Lundstrom, “Elementary scattering theory of the SiMOSFET,” IEEE Electron Device Letters, vol. 18, no. 7,pp. 361–363, 1997.

[2] J. J. Liou, A. Ortiz-Conde, and F. J. Garcıa-Sanchez, Analysisand Design of MOSFETs: Modelling, Simulation and Param-eter Extraction, Springer, Boston, MA, USASpringer, 1998,ISBN: 978-0-412-14601-5.

[3] Y. Taur, J. Wu, and J. Min, “A short-channel I-V model for 2-D MOSFETs,” IEEE Transactions on Electron Devices, vol. 63,no. 6, pp. 2550–2555, 2016.

[4] Y. Tsividis and C. McAndrew, Operation and Modelling of theMOS Transistor, Oxford University Press, Oxford, UK, 2011,ISBN: 0195170156, 9780195170153.

[5] D. K. Schroder, Semiconductor Material and Device Char-acterization, John Wiley & Sons, Hoboken, NJ, USA, 2006,ISBN: 0471749087, 9780471749080.

[6] Y. Swami and S. Rai, “Comparative methodical assessment ofestablished MOSFET threshold voltage extraction methods at10-nm technology node,” Circuits and Systems, vol. 7, no. 13,32 pages, 2016.

[7] A. Ortiz-Conde, F. J. Garcıa-Sanchez, J. Muci, A. TeranBarrios, J. J. Liou, and C.-S. Ho, “Revisiting MOSFETthreshold voltage extraction methods,” Microelectronics Re-liability, vol. 53, no. 1, pp. 90–104, 2013.

[8] G. Gildenblat, X. Li, W. Wu et al., “PSP: an advanced surface-potential-based MOSFETmodel for circuit simulation,” IEEETransactions on Electron Devices, vol. 53, no. 9, pp. 1979–1993,2006.

[9] F. J. Garcıa Sanchez, A. Ortiz-Conde, and J. Muci, “Un-derstanding threshold voltage in undoped-bodyMOSFETs: anappraisal of various criteria,” Microelectronics Reliability,vol. 46, no. 5-6, pp. 731–742, 2006.

[10] J. A. Salcedo, A. Ortiz-Conde, E. J. G. Sanchez, J. Muci,J. J. Liou, and Y. Yue, “New approach for de;ning thethreshold voltage of MOSFETs,” IEEE Transactions on Elec-tron Devices, vol. 48, no. 4, pp. 809–813, 2001.

[11] A. Ortiz-Conde, J. Rodrgueza, F. J. Garca Sancheza, andJ. J. Lioub, “An improved de;nition for modeling thethreshold voltage of MOSFETs,” Solid-State Electronics,vol. 42, no. 9, pp. 1743–1746, 1998.

[12] J. Lee, Y. Kim, and S. Cho, “Design of poly-Si junctionless ;n-channel FET with quantum-mechanical drift-di8usion modelsfor sub-10-nm technology nodes,” IEEE Transactions onElectron Devices, vol. 63, no. 12, pp. 4610–4616, 2016.

[13] P. Yu, Y. Zhou, L. Sun, and J. Gao, “A simple semi-analyticalparameter extraction method for 40 nm gatelength MOSFET,”in Proceedings of the 2015 IEEE 11th International Conference onASIC (ASICON), Chengdu, China, November 2015.

[14] M.M. Lau, C. Y. T. Chiang, Y. T. Yeow, and Z. Q. Yao, “A newmethod of threshold voltage extraction via MOSFET gate-to-substrate capacitance measurement,” IEEE Transactions onElectron Devices, vol. 48, no. 8, pp. 1742–1744, 2001.

[15] K. Terada, K. Nishiyama, and K.-I. Hatanaka, “Comparison ofMOSFET-threshold-voltage extraction methods,” Solid-StateElectronics, vol. 45, no. 1, pp. 35–40, 2001.

[16] H.-S. Wong, M. H. White, T. J. Krutsick, and R. V. Booth,“Modeling of transconductance degradation and extraction ofthreshold voltage in thin oxide MOSFET’s,” Solid-StateElectronics, vol. 30, no. 9, pp. 953–968, 1987.

[17] B. El-Kareh, W. R. Tonti, and S. L. Titcomb, “A submicronMOSFET parameter extraction technique,” IBM Journal ofResearch and Development, vol. 34, no. 2.3, pp. 243–249, 1990.

[18] J. S. Wong, J. G. Ma, K. S. Yeo, and M. A. Do, “A new ap-proach for the extraction of threshold voltage for MOSFET’s,”in Technical Proceedings of the 2001 International Conferenceon Modeling and Simulation of Microsystems, vol. 1, HiltonHead Island, SC, USA, 2001.

[19] A. K. Dwivedi, S. Tyagi, and A. Islam, “+reshold voltageextraction and its reliance on device parameters @ 16-nmprocess technology,” in Proceedings of the 2015 AirdInternational Conference on Computer, Communication,Control and Information Technology (C3IT), Kolkata, India,February 2015.

[20] H.-G. Lee, S.-Y. Oh, and G. Fuller, “A simple and accuratemethod to measure the threshold voltage of an enhancement-mode MOSFET,” IEEE Transactions on Electron Devices,vol. 29, no. 2, pp. 346–348, 1982.

[21] H. K. Lim and J. G. Fossum, “An analytic characterizationof weak-inversion drift current in long-channel MOSFET,”IEEE Transactions on Electron Devices, vol. 30, no. 6,pp. 713–715, 1983.

[22] Y. Swami and S. Rai, “Modeling and analysis of sub-surfaceleakage current in nano-MOSFET under cuto8 regime,”Superlattices and Microstructures, vol. 102, pp. 259–272, 2017.


[23] L. E. Toledo, P. A. Petrashin, W. J. Lancioni, andC. D. Vazquez, “+reshold voltage extraction circuit for lowvoltage CMOS design using basic long-channel MOSFET,” inProceedings of the 2015 IEEE 6th Latin American Symposiumon Circuits & Systems (LASCAS), Montevideo, Uruguay,February 2015.

[24] V. Mosser, D. Seron, and Y. Haddab, “+reshold voltageextraction method in ;eld-e8ect devices with power-lawdependence of mobility on carrier density,” in Proceedingsof the 2015 International Conference on Microelectronic TestStructures (ICMTS), Phoenix, AZ, USA, March 2015.

[25] UC Berkeley Device Group, Berkeley Predictive TechnologyModel, http://ptm.asu.edu/.

[26] P. Kushwaha, R. Agarwal, H. Agarwal et al., “Modelling ofthreshold voltage for operating point using industry standardBSIM-IMG model,” in Proceedings of the 2016 IEEE In-ternational Conference on Electron Devices and Solid-StateCircuits (EDSSC), Hong Kong, China, August 2016.

[27] R. Goswami and B. Bhowmick, “An algorithm for extractionof threshold voltage in heterojunction TFETs,” IEEE Trans-actions on Nanotechnology, vol. 16, no. 1, pp. 90–93, 2017.

[28] G. Sheu, S.-M. Yang, A. Kumar, S. S. Imam, F. M. Jen, andS. W. Lu, “An experimental and analytical method to observethe polysilicon nanowire MOSFET threshold voltage,” inProceedings of the 2016 IEEE 11th Annual InternationalConference on Nano/Micro Engineered and Molecular Systems(NEMS), Sendai, Japan, April 2016.

[29] G. Gluszko, D. Tomaszewski, J. Malesinska, and K. Kucharski, “Asimple method for extraction of threshold voltage of FD SOIMOSFETs,” in 2013 Proceedings of the 20th International Con-ferenceMixedDesign of IntegratedCircuits and Systems (MIXDES),Gdynia, Poland, January 2013, ISBN: 978-83-63578-02-2.

[30] T. Rudenko, V. Kilchytska, M. K. M. Arshad, J.-P. Raskin,A. Nazarov, and D. Flandre, “On the MOSFET thresholdvoltage extraction by transconductance and transconductance-to-current ratio change methods: part I—e8ect of gate-voltage-dependent mobility,” IEEE Transactions on Electron Devices,vol. 58, no. 12, pp. 4172–4179, 2011.

[31] T. Rudenko, V. Kilchytska, M. K. M. Arshad, J.-P. Raskin,A. Nazarov, and D. Flandre, “On the MOSFET thresholdvoltage extraction by transconductance and transconductance-to-current ratio changemethods: part II—e8ect of drain voltage,”IEEE Transactions on Electron Devices, vol. 58, no. 12,pp. 4180–4188, 2011.

[32] B. Cretu, T. Boutchacha, G. Ghibaudo, and F. Balestra, “Newratio method for e8ective channel length and thresholdvoltage extraction in MOS transistors,” Electronics Letters,vol. 37, no. 11, pp. 717–719, 2001.


http://ptm.asu.edu/

Submit your manuscripts athttps://www.hindawi.com

ScientificaHindawi Publishing Corporationhttp://www.hindawi.com Volume 2014

CorrosionInternational Journal of

Hindawi Publishing Corporationhttp://www.hindawi.com Volume 2014

Polymer ScienceInternational Journal of



CeramicsJournal of


CompositesJournal of

NanoparticlesJournal of



International Journal of

Biomaterials


NanoscienceJournal of

TextilesHindawi Publishing Corporation http://www.hindawi.com Volume 2014

Journal of

NanotechnologyHindawi Publishing Corporationhttp://www.hindawi.com Volume 2014

Journal of

CrystallographyJournal of


The Scientific World JournalHindawi Publishing Corporation http://www.hindawi.com Volume 2014


CoatingsJournal of

Advances in

Materials Science and EngineeringHindawi Publishing Corporationhttp://www.hindawi.com Volume 2014

Smart Materials Research



MetallurgyJournal of


BioMed Research International

MaterialsJournal of


Documents

Modeling, Simulation, and Analysis of Novel Threshold