Modeling On-Die Power Supply DecouplingRandy Wolff – Micron TechnologyLance Wang – IO Methodologyg gy

DesignCon IBIS SummitSanta Clara, CA, USA

February 2, 2012

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©2012 Micron Technology, Inc. | 1February 2, 2012

Outline

• Elements of an IBIS 5.0 model for Power Integrity simulationsimulation

• On-die power supply decoupling models

Parasitic vs. non-parasitic

Optimization of models

• Simulation results - Transistor-level vs. IBIS 3.2, 5.0

• Conclusions

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IBIS 5.0 Power Integrity Modeling

• PI modeling requires [Composite Current], [ISSO PU], [ISSO PD] and a detailed model of decoupling capacitance[ ] p g p

ISSO PU

Decoupling

ISSO PD

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* Image from IBIS 5.1 Draft Specification

Power Supply Decoupling Elements

Bond Pad Layout Floorplan

BBypass Cap

Parasitic

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Parasitic Decoupling

Parasitic Decoupling Capacitance

14.0000

6 0000

8.0000

10.0000

12.0000

12 0000 14 0000

Capacitance

0.0000

2.0000

4.0000

6.0000 12.0000-14.0000

10.0000-12.0000

8.0000-10.0000

6.0000-8.0000

4.0000-6.0000

2.0000-4.0000

0.0000-2.0000

Note:• Strongly frequency dependant

W kl lt

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• Weakly voltage dependant

Optimization of Parasitic Decoupling

~ 13.4pF - not insignificant

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Transistor-level vs. Model

Optimization of All Decoupling

Adds ~450pF!

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Transistor-level vs. Model

Simulation Setup• DDR3 DQ I/O buffer, 1.5V

• PRBS pattern, minimum bit width of 1.25ns

Typical corner

VCCQ

PKG

I_vccq

• Typical corner

• Various On-die decoupling capacitance models included as SPICE models50 ΩZo=50 Ω

PKG

PKG

DQ1

V_load

• DQ1 + DQ2 switching (with different PRBS patterns) with fully coupled SPICE package model

VTT3pF

PKGDQ1

DECAP

VTT

50 ΩZo=50 Ω

3pF

PKGDQ2

DECAP

VSSQ

PKG

DECAP

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VSSQ

No Decoupling Model

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No Decoupling Model

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Parasitic Decoupling Model Included

Good match to ringing behavior

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Parasitic Decoupling Model Included

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All Decoupling Modeled

Ringing behavior no longer matches. Why?y

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All Decoupling Modeled

14February 2, 2012

Conclusions

• A complete model for on-die power supply decoupling must include models for parasitic caps and designed-in caps

• Simple, multi-stage RC circuits accurately model on-die decoupling circuits

• A method is needed for including complex decoupling models along with an IBIS 5.0 model

• More investigation needed to understand circumstances where IBIS 5.0 power-aware models do not match SPICE models

15February 2, 2012

May 31, 2011