MODELING AND SUPPRESSION OF LATCHUP

BY

FARZAN FARBIZ

DISSERTATION

Submitted in partial fulfillment of the requirements

for the degree of Doctor of Philosophy in Electrical and Computer Engineering

in the Graduate College of the

University of Illinois at Urbana-Champaign, 2010

Urbana, Illinois

Doctoral Committee:

Professor Elyse Rosenbaum, Chair

Professor Milton Feng

Professor José E. Schutt-Ainé

Professor Shyh-Jye Jou

ii

ABSTRACT

In this dissertation, an experimental study of latchup is conducted. A semi-

physical analytical model is proposed that estimates the latchup susceptibility of a design

prior to fabrication. The model can easily be implemented in a circuit simulator and be

simulated together with the rest of the design.

We will show that depending on the bias conditions and layout geometry,

electrons or holes can trigger latchup. Latchup hazards caused by holes and electron

injection are studied.

The roles of guard rings are investigated. The impacts of N-type and P-type guard

rings are reported. The guard-ring efficacy under high-level injection conditions and short

injection pulse durations are also reported. We show that N-well guard rings in particular

become less efficient as the amount of injection increases or when the injection-pulse

duration is shortened. The effects of guard rings are incorporated into the model.

We demonstrate that whether electron injection or hole injection is the worst case,

that is, has the lowest latchup susceptibility, depends on the pulse-width of the injection

current. Electron injection is the worst case condition during static latchup testing, i.e.,

when the injection pulse-width is long. This condition is generally used for product

qualification. However, real world stresses, such as cable discharges, are transient, in

which case hole injection is the worst case condition.

iii

Chapters 1 and 2 give background on latchup. They explain the difference

between internal and external latchup and show that latchup can be triggered by static or

transient events. A brief history of previous work on latchup is presented.

Chapter 3 focuses on internal latchup. Latchup triggering modes and

characterization methods are explained.

Chapter 4 is devoted to analysis of external latchup and the standard latchup

tests. The term collection efficiency is defined in this chapter to represent the number of

injected carriers participating in triggering latchup. Circuit-level models are proposed to

understand latchup behavior under various testing conditions. These circuit schematics

provide a base for modeling latchup susceptibility later in Chapter 6.

Measurement results of the collection efficiency and external latchup trigger

current are presented and investigated in Chapter 5. The effects of layout geometry are

studied. Guard ring interactions and their effect on latchup resilience are explained.

A model for the external latchup trigger current is proposed and compared to the

measurement results in Chapter 6. The model can be used in a circuit simulator to

estimate the latchup susceptibility of a layout. The model captures the effects of the guard

rings.

Transient latchup testing is discussed in Chapter 7. The worst-case testing

conditions for static and transient latchup are reported. Guard rings are evaluated under

transient latchup testing. Finally, conclusions are drawn and future work is suggested in

Chapter 8.

iv

To my parents and my brothers

v

ACKNOWLEDGMENTS

First of all, I would like to thank my thesis advisor, Professor Elyse Rosenbaum,

for her guidance and patience during the past years. Her patient help has always

impressed me. I would not have been able to finish this work without her support.

I would also like to thank Robert Gauthier, Kiran Chatty, and Gianluca Boselli for

answering technical questions.

Many former and current students deserve thanks for helpful discussions.

Especially, these include James Di Sarro, Nick Olson, Nathan Jack, Vrashank Shukla,

Arjun Kripanidhi, Adam Faust, Jeff Lee, Karan Bhatia, and Ankit Srivastava.

And special thanks to my friends in Urbana-Champaign who helped me through

these difficult years: Amir H. Sadr, Hamed Okhravi, Navid Okhravi, Javad Ghaderi,

Mohammad Naraghi, Reza Tograei, and many more. In particular, I like to thank

Maryam Karimzadehgan for her unconditional help and support.

vi

TABLE OF CONTENTS

CHAPTER 1 INTRODUCTION ........................................................................................ 1

1.1 Motivation ............................................................................................................ 1 1.2 Dissertation Overview .......................................................................................... 2

CHAPTER 2 LATCHUP BACKGROUND ....................................................................... 4

2.1 Substrate Current Injectors ................................................................................... 6 2.2 Cable Discharge Event ......................................................................................... 7 2.3 Literature Review ................................................................................................. 8 2.4 Figures ................................................................................................................ 10

CHAPTER 3 INTERNAL LATCHUP ............................................................................. 13

3.1 PNPN Triggering Modes .................................................................................... 13

3.1.1 Overshoot and undershoot on PNPN terminals .......................................... 13

3.1.2 Overvoltage/avalanching N-well junction .................................................. 13

3.1.3 Punchthrough .............................................................................................. 14

3.2 Latchup Characterization ................................................................................... 14

3.2.1 Two-terminal characterizations .................................................................. 15

3.2.2 Four-terminal characterizations .................................................................. 16

3.3 Figures ................................................................................................................ 17

CHAPTER 4 EXTERNAL LATCHUP ............................................................................ 21

4.1 Analysis of External Latchup ............................................................................. 21

4.1.1 Negative I-test ............................................................................................. 22

4.1.2 Positive I-test .............................................................................................. 24

4.1.3 Undervoltage on VDDO ................................................................................ 25

4.1.4 Considerations for the substrate current ..................................................... 26

4.2 Figures ................................................................................................................ 28

CHAPTER 5 MEASUREMENT RESULTS AND DISCUSSIONS ............................... 33

5.1 Test Structures .................................................................................................... 33 5.2 Collection Efficiency .......................................................................................... 34

5.2.1 Layout geometry ......................................................................................... 34

5.2.2 Temperature ................................................................................................ 35

5.2.3 Bias conditions ............................................................................................ 35

5.2.4 N-well guard rings ...................................................................................... 37

vii

5.2.5 Multiple detectors ....................................................................................... 38

5.2.6 P-type guard rings ....................................................................................... 39

5.2.7 P-well taps ................................................................................................... 40

5.3 Measurement Results of Itrig ............................................................................... 41 5.4 Figures ................................................................................................................ 43 5.5 Tables ................................................................................................................. 58

CHAPTER 6 MODELING THE LATCHUP TRIGGER CURRENT ............................. 59

6.1 Collection Efficiency of a Single Detector ........................................................ 59

6.1.1 Effects of spacing ........................................................................................ 59

6.1.2 Effects of bias voltage ................................................................................. 70

6.1.3 Effects of temperature ................................................................................. 72

6.1.4 Effects of injection current .......................................................................... 73

6.2 Effects of Guard Rings on the Collection Efficiency ......................................... 75

6.2.1 Modeling α*NW ............................................................................................ 75

6.3 Modeling the Latchup Trigger Current .............................................................. 81

6.3.1 Parameter extraction ................................................................................... 83

6.4 Figures ................................................................................................................ 84 6.5 Table ................................................................................................................... 98

CHAPTER 7 TRANSIENT LATCHUP TESTING ......................................................... 99

7.1 Experimental Setup ............................................................................................ 99 7.2 Results and Discussions ................................................................................... 101

7.2.1 Pulse-width dependence............................................................................ 101

7.2.2 Effect of trigger source rise-time .............................................................. 105

7.2.3 Orientation of the victim ........................................................................... 107

7.2.4 Guard ring efficiency under TLU testing.................................................. 109

7.2.5 Triple well technology .............................................................................. 109

7.2.6 Negative I-test vs. positive I-test .............................................................. 110

7.3 Modeling and Simulations ............................................................................... 110 7.4 Figures .............................................................................................................. 112

CHAPTER 8 CONCLUSIONS AND FUTURE WORK ............................................... 125

8.1 Conclusions ...................................................................................................... 125 8.2 Future Work ..................................................................................................... 128

8.2.1 Negative I-test ........................................................................................... 128

8.2.2 Positive injection ....................................................................................... 129

8.2.3 Transient latchup ....................................................................................... 129

viii

8.2.4 Latchup and substrate noise ...................................................................... 129

8.3 Figure ............................................................................................................... 130

REFERENCES ............................................................................................................... 131

1

CHAPTER 1

INTRODUCTION

1.1 Motivation

Latchup is a CMOS integrated circuit failure mechanism characterized by

excessive current flow between the power supply and ground rails. It may be a temporary

state that is eliminated upon removal of the exciting stimulus, a catastrophic state

requiring shutdown of the system in order to clear, or a fatal state requiring that the

damaged device be replaced.

Integrated circuits can be protected against latchup by use of guard rings. Guard

rings are commonly used to improve the latchup resilience of CMOS chips. Efficiency of

the guard rings in mitigating latchup hazards depends on the type of guard rings, i.e., P-

well or N-well rings, and their design, i.e., the layout geometry. These issues are

described below.

N-well and P-well guard rings are available in a design kit. The former is

recommended for preventing latchup caused by electrons, and the latter for latchup by

holes. Therefore, before choosing the appropriate guard rings, one must decide which

type of carrier, electron or hole, is more likely to trigger latchup. This is no trivial task

without having a good understanding of how latchup is triggered in the circuit.

2

As a general rule, wider guard rings are more effective in preventing latchup.

However, wider guard rings consume more area and, hence, are more expensive. The

minimum required guard ring width is always preferred to minimize cost. A model for

latchup that includes the effects of the guard ring geometry can be used to design the

guard rings.

These issues can be addressed by analyzing latchup and the effect of guard rings

under various testing conditions. If a model for latchup were available, the designer could

simulate the circuit and estimate the latchup susceptibility of the chip. If the effects of

guard rings were included in the model, the designer could simulate different geometries

and design the optimum guard ring.

The purpose of this work is, first, to understand how latchup is triggered in a

circuit under various testing conditions. Next, it will develop a geometry-dependent

physical model for latchup that can determine the latchup susceptibility of a layout prior

to fabrication. With such a model in hand, layout can be analyzed to ensure that the

product will pass the latchup tests [1].

1.2 Dissertation Overview

Chapter 2 gives background on latchup. It explains the difference between

internal and external latchup. It shows that latchup can be triggered by static or transient

events. A brief history of previous work on latchup is presented.

Chapter 3 focuses on internal latchup. Latchup triggering modes and

characterization methods are explained.

3

Chapter 4 is devoted to analysis of external latchup and the standard latchup

tests. The term collection efficiency is defined in this chapter to represent the number of

injected carriers participating in triggering latchup. Circuit level models are proposed to

understand latchup behavior under various testing conditions. These circuit schematics

provide a base for modeling latchup susceptibility later in Chapter 6.

Measurement results of the collection efficiency and external latchup trigger

current are presented and investigated in Chapter 5. The effects of layout geometry are

studied. Guard ring interactions and their effect on latchup resilience are explained.

A model for the external latchup trigger current is proposed and compared to the

measurement results in Chapter 6. The model can be used in a circuit simulator to

estimate the latchup susceptibility of a layout. The model captures the effects of the guard

rings.

Transient latchup testing is discussed in Chapter 7. The worst case testing

conditions for static and transient latchup are reported. Guard rings are evaluated under

transient latchup testing. Finally, conclusions are drawn and future work is suggested in

Chapter 8.

4

CHAPTER 2

LATCHUP BACKGROUND

Latchup is a potential hazard in every technology that requires both kinds of MOS

transistors, NMOS and PMOS, on a single substrate, meaning that both N- and P-type

wells are needed. NMOS and PMOS transistors are formed by creating the N-well, P-

well, P+ diffusion, and N

+ diffusions shown in Figure 2-1. Unfortunately, CMOS

transistors are not the only structures that exist; PNPN devices consisting of two parasitic

bipolar transistors are also made. The first transistor is a PNP formed by P+ diffusion, N-

well, and P-well. The second is an NPN transistor formed by N+ diffusion, P-well, and N-

well. These two transistors form a PNPN that lies between VDD and VSS. Under normal

operating conditions, the PNPN does not conduct current and remains in the off state.

However, as a result of a sudden change in the supply voltage, it may switch to a low-

impedance state and create a short circuit path between VDD and the ground (Figure 2-1).

The CMOS structure may be permanently damaged depending on the amount of current

flowing through the short circuit path.

Figure 2-2 shows the device cross-section of a two-terminal PNPN, as well as its

IV characteristics. If the voltage across the PNPN is less than the switching voltage (VS),

it remains off and, the current drawn from the power supply will be only that dissipated

in the functional circuitry. However, if the voltage is higher than VS, the PNPN switches

to a low-impedance state.

5

When the PNPN is triggered by an undershoot or an overvoltage on one of its

terminals, it is called internal latchup because the stress source was directly connected to

the PNPN structure. Another form of latchup is when the stress source is placed away

from the PNPN and is called external latchup. Figure 2-3 shows a substrate current

injector, called the injector, next to a CMOS inverter. During an event, carriers may be

injected to the substrate by the injector. The parasitic PNPN associated with the inverter,

called the victim in this work, may be latched if NW (the detector) or PW collects enough

numbers of injected carriers from the substrate. The minimum injected current at the

injector that results in external latchup is denoted as the trigger current, Itrig.

Electronic products are usually required to pass static and, sometimes, transient

latchup tests. In static latchup testing, the injection source has a long pulse duration (10

µs-1 s) and slow rise-time (5 µs-5 ms) [1]. It consists of I-tests and overvoltage tests. I-

tests refer to injection of positive and negative current into each input, output, or I/O pin,

and overvoltage tests refer to overvoltage testing of each supply pin.

The setup for static latchup testing is fairly simple. However, static latchup tests

are not believed to emulate real-world transient disturbances that could trigger latchup.

Such events have short pulse duration (hundreds of nanoseconds) and fast rise-time (a

few nanoseconds). For example, a cable discharge event, described later in this chapter,

can be as short as 100s of ns. Testing under short pulse durations is called transient

latchup (TLU) testing. A variety of non-standardized procedures have been proposed for

TLU testing. One such test is described in a recommended practice document published

by the ESD Association [2]; in this test, the stimulus—a negative voltage pulse—is

applied directly to the supply terminal of the PNPN device, placing it in the category of

6

static latchup testing. More relevant to this work is the transient I-test [3], [4], in which

the trigger source is a current pulse with short pulse duration and fast rise-time. Details of

the experimental setup for the transient I-test are given in Section 7.1.

Latchup is the result of current flow in the substrate. The current is due to carriers

injected into the substrate by substrate carrier injectors, which are commonly formed as

parasitic devices connected to signal pins. They are explained in the next section.

2.1 Substrate Current Injectors

Figure 2-4 shows a typical I/O circuitry. The power supply and ground rails in an

I/O domain are connected to VDDIO and VSSIO, respectively. Two types of substrate

current injectors are found at I/O pads: bottom injectors and top injectors. A bottom

injector is connected between an I/O pad and VSSIO, while a top injector is connected

between an I/O pad and VDDIO. The bottom injector may be either an ESD protection

device, e.g., a diode, or the drain/body junction of an NMOS transistor. The top injector

may be either an ESD protection device or the drain/body junction of a PMOS transistor.

In this work, without loss of generality, P-well and N-well diodes are used as the bottom

and top injectors, respectively.

When a PN junction is forward-biased, carriers are injected from one side to the

other. For instance, consider an N+ diffusion forming a diode with the grounded P-

substrate. This N+ diffusion may be the source or drain of an NMOS transistor. Electrons

are injected into the substrate when the diode is forward-biased by an undershoot on the

N+ diffusion.

7

There are several causes for such voltage undershoots. It is true that the substrate

is always tied to the lowest voltage in the circuit, VSS, and that all of the N+-substrate PN

junctions are reverse-biased in a CMOS device. However, capacitive coupling and cross-

talk may transiently reduce the voltage of a node below VSS. Another possible reason for

forward-biasing a substrate diode is a cable discharge event (CDE). Diodes tied to the I/O

pads may turn on and inject carriers into the substrate as a result of a CDE.

2.2 Cable Discharge Event

A cable discharge event (CDE) is a real reliability issue in the networking

industry that may lead to permanent device malfunction [5]. A CDE occurs when charge

is injected into a circuit as a result of plugging in a cable. The charge transfer from the

high to the low potential causes a current flow and likely permanent damage [6]. A

twisted-pair cable can store charge quite like a capacitor. The conductors inside the cable

and ground are the capacitor plates, and the cable insulator acts as the dielectric. While

CDE is relevant to virtually any twisted-pair cable, Ethernet cables have captured the

most attention [7].

Charge may be stored in a cable from several sources. For example, dragging a

cable across a carpet will result in an accumulated charge. Another example is charge

induced from adjacent electromagnetic fields. Once charged, the cable may retain the

charge for several hours. High-quality Ethernet cables, for instance, retain the stored

charge for more than 24 hours [8].

There are several ways to prevent CDE damage at an end-user’s side. One is

ensuring that the cable is discharged to ground before plugging into a circuit, preventing

8

the charge injection. Another is to power down the system before connecting the cable.

While these methods can prevent or reduce CDE damage, they may be inconvenient or

even unfeasible in some cases.

2.3 Literature Review

While latchup is typically known as a reliability issue for commercial

semiconductor products, historically, it was first observed in space applications [9], [10].

The low-power advantage of CMOS technology made it the best choice for implementing

space circuitry. However, these devices frequently failed when they were exposed to

single-particle radiation, an unavoidable situation in space applications [11]. It was later

found that CMOS devices may be triggered into a low-impedance mode in radiation

environments [12].

Latchup was not considered a reliability issue for commercial semiconductor

products until the mid-1970s, when scientists at Sandia National Laboratory found that

there were other latchup triggering modes besides high-energy particles [13]–[17]. By

dramatically scaling the channel length of transistors and progressively integrating

devices in a single chip, latchup became a major issue in commercial semiconductor

products in the mid-1980s [18], [19]. Several triggering modes relevant to commercial

products were investigated by Troutman [20]. Based on these investigations, circuit and

device techniques were proposed to eliminate the hazard [21], [22]. A few models were

proposed to predict latchup susceptibility [23]–[25]. Latchup testing procedures were

documented as a JEDEC standard in 1988 [26].

9

Years later, it was shown that plugging a charged cable into a system may trigger

latchup in a circuit [5]. This triggering mode is considered as external latchup because

latchup is triggered as a result of injection elsewhere in the circuit, for example in an I/O

pad [27]. For example, if electrons are injected into the substrate, depending on the

carrier lifetime, some of the injected carriers find the way to the devices [3]. Carrier

lifetime depends on substrate doping. Low-doped substrates are now typically used to

reduce noise coupling and achieve high Q for passive elements in RF applications [28].

Despite all of its advantages, using a low-doped substrate comes with increased carrier

lifetime. Hence, with a low-doped substrate, minority carriers have a greater chance to

survive and trigger latchup before recombining with the majority carriers. Furthermore,

spacing between I/O pads and CMOS devices has been reduced with the increased focus

on cost, density, and high level of integration. When I/O pads are placed closer to the

core circuitry, more carriers reach CMOS devices. This is of great concern especially in

flip chip technologies where I/O pins are placed very close to the core circuitry.

Therefore, the technology trend has increased the susceptibility of CMOS devices to

external latchup.

Latchup can be investigated by performing device simulations [29], [30]. The

device parameters such as doping levels must be well calibrated in order to get predictive

results. The calibration procedure is complicated and performing the simulations is

always time consuming.

Ever since latchup was identified as a concern for commercial electronic devices,

the need for a model that predicts susceptibility of a circuit has emerged [31]. In [6], a

simple model is proposed that estimates the number of carriers in the substrate at a

10

distance r from the injection source. The model is entirely empirical and incapable of

capturing the effects of layout geometry. The effects of guard rings are not incorporated

in the model, which makes it impractical for most real design situations, where guard

rings are always used.

Electrons or holes can trigger latchup in a circuit. Kontos claims that electrons are

more likely to trigger latchup [4]. We will show that this is too general a claim. Latchup

triggered by electrons or holes could be the worst case, depending on the layout and bias

conditions.

Kontos and Domanski report that Itrig of transient latchup is a decreasing function

of the pulse-width of the injection current [3], [4]. Nevertheless, they do not explain why

this is so. We will mathematically show why Itrig is a decreasing function of the

pulse-width. We will also show that the pulse-width dependence depends on whether

latchup is triggered by electrons or holes.

2.4 Figures

P+ N+

NWPW

P+N+P+ N+

NMOS PMOS

VDDVSS OUT OUT ININ VDDVSS

Figure 2-1: Device cross-section of a CMOS device showing the parasitic bipolar

transistors.

11

P+ N+P+ N+

NWPW

VDDVSS

Voltage

Current

VS

Ih

Figure 2-2: (a) PNPN device cross-section and (b) its IV characteristics.

(b)

(a)

12

Figure 2-3: Device cross-section of a CMOS inverter next to a substrate current injector.

The carriers in the substrate may reach the CMOS inverter and trigger latchup. The N-

well of the victim is where the electrons are collected and is called the detector.

VDDIO

VSSIOVDDIO

VSSIO

EN

EN’

EN

EN’

I/O

Figure 2-4: A typical I/O circuitry. The diodes are for ESD protection and could be

replaced by other ESD clamps.

CMOS inverter

Substrate

NW

P+ P+N+

PW

I/O

VSSIO

VDD

Substrate current

injector (injector)

N+ P+P+ N+ N+ P+

VSS

PW

In

OutDetector

13

CHAPTER 3

INTERNAL LATCHUP

Internal latchup is studied in this chapter. This type of latchup is called internal

latchup because the stimulus is connected directly to the victim, the parasitic PNPN.

3.1 PNPN Triggering Modes

3.1.1 Overshoot and undershoot on PNPN terminals

The voltage on an output node may temporarily exceed the supply voltage as a

result of a signal reflection at a mismatched interface. This could trigger latchup if a

parasitic PNPN is connected to the output node. When this transient overshoot is on a P+

diffusion, holes are injected into the N-well. The injected carriers are collected by the

substrate contact and produce a voltage drop across the substrate. If the voltage drop

across the base-emitter junction of the NPN is high enough, the parasitic NPN is turned

on. The collector current of this NPN builds up a voltage drop across the base-emitter

junction of the PNP. Latchup is triggered when both transistors are on [20].

Latchup can also be triggered when the output node falls below ground. In this

case, electrons are injected into the substrate and leave a voltage drop as they are

collected by an N-well.

3.1.2 Overvoltage/avalanching N-well junction

Since both parasitic bipolar transistors in a parasitic PNPN are normally off, the

supply voltage appears across the reverse-biased N-well/P-substrate PN junction. When

14

the supply voltage is raised, e.g., because of a power supply glitch, the resulting

avalanche current may forward-bias one of the base-emitter junctions and trigger latchup

[20].

3.1.3 Punchthrough

The depletion region of the reverse-biased N-well/P-substrate junction may

spread into a closely spaced N+ diffusion in the substrate, causing a punchthrough current

that may bias either of the parasitic transistors. Similarly, punchthrough current flows

when the depletion region spreads into a closely spaced P+ diffusion in the N-well.

Although silicon devices are engineered to ensure that punchthrough does not occur at

the nominal supply voltage, since the depletion width of a PN junction is an increasing

function of the voltage, punchthrough current flows when the supply voltage exceeds the

nominal voltage. Depending on the device characteristics, either avalanche or

punchthrough current may trigger latchup at a lower voltage [20].

3.2 Latchup Characterization

The aim of latchup characterization is to find the minimum allowable N+-to-P

+

spacing and maximum allowable diffusion-well tap spacing in a given technology by

extracting the key latchup parameters, such as the internal latchup trigger current. The

main idea is to trigger one of the parasitic bipolar transistors by an external voltage or

current excitation. Once one of the transistors is on, it provides enough current to turn on

the other transistor.

15

Depending on how the PNPN terminals are biased, characterization methods fall

into one of two groups: two-terminal characterizations and four-terminal

characterizations.

3.2.1 Two-terminal characterizations

A two-terminal PNPN is formed and biased by tying the P+ diffusion and N-well

taps to VDD and grounding the N+ diffusion and substrate taps. The PNPN is triggered by

either a voltage or current stress.

Supply overvoltage stress

Voltage across the terminals is slowly raised, and the current through the device is

recorded, as shown in Figure 3-1. Current compliance of the tester is set low enough to

prevent permanent damage to the device. This method does not capture the negative

resistance region of the PNPN I-V curve unless resistance is added in series with the

voltage source.

Supply overcurrent stress

A supply overcurrent stress test is used to get the complete I-V curve of the

PNPN, including holding current and voltage. Unlike the previous test, in this test, shown

in Figure 3-2, a current source is connected to one of the terminals. The PNPN snaps

back and switches into its low-impedance regime when the current is raised. The

difficulty of this test is that the injection current needed to forward-bias either of the

parasitic transistors is typically much larger than the typical leakage current of the N-

well/P-substrate PN junction. Therefore, a relatively large voltage is induced across the

device when the current is raised, which may cause a failure before triggering latchup.

16

3.2.2 Four-terminal characterizations

In these methods, the PNPN terminals are individually connected to the curve

tracer, and the current or voltage of each terminal is separately measured.

Voltage excitation at P+ diffusion

Referring to Figure 3-3, while the N-well voltage is fixed at VDD and N+ diffusion

and the substrate tap are grounded, the voltage at the P+ diffusion is raised from VDD to

forward-bias the base-emitter junction of the PNP. Latchup is triggered when the

collector current of the PNP is high enough to forward-bias the base-emitter junction of

the NPN.

Current source excitation at substrate or well contact

There are two ways to do this test. First, a current source is connected to the N-

well tap, the P+ diffusion is tied to VDD, and the substrate tap and N

+ diffusion are

grounded (Figure 3-4 (a)). The PNP is turned on when the voltage drop across the N-well

is high enough to forward-bias the base-emitter junction.

In the second test, shown in Figure 3-4 (b), latchup is triggered by turning on the

NPN. A current source provides current at the substrate tap to forward-bias the base-

emitter junction of the NPN. The N+ diffusion is grounded, and the N-well tap and P

+

diffusion are tied to VDD (Figure 3-4 (b)).

Current source excitation at P+ or N

+ diffusion

Latchup may be triggered by injecting current into the P+ diffusion, as depicted in

Figure 3-5. Unlike a two-terminal supply overcurrent stress, the N-well tap is tied to VDD,

17

and current is only injected into the diffusion. Alternatively, latchup can be triggered by

sinking current from the N+ diffusion (Figure 3-5 (b)).

3.3 Figures

P+ N+P+ N+

NWPW

VSource

+-

Figure 3-1: Supply overvoltage stress test.

P+ N+P+ N+

NWPW

ISource

Figure 3-2: Supply overcurrent stress test.

18

P+ N+P+ N+

NWPW

VSource

+

-

VDD

Figure 3-3: Voltage excitation at P+ diffusion.

19

ISource

P+ N+P+ N+

NWPW

VDD

ISource

N+P+ N+P+

PW NW

VDDVDD

Figure 3-4: Current excitation at (a) N-well tap and (b) substrate tap.

(b)

(a)

20

ISource

P+ N+P+ N+

NWPW

VDD

ISource

N+P+ N+P+

PW NW

VDDVDD

Figure 3-5: Current excitation at (a) P+ diffusion and (b) N

+ diffusion.

(b)

(a)

21

CHAPTER 4

EXTERNAL LATCHUP

4.1 Analysis of External Latchup

External latchup is the result of the substrate current flow. Substrate current may

consist of majority carriers (holes) and/or minority carriers (electrons). To understand

how Itrig is related to layout parameters, the type of carrier that triggers latchup must first

be determined.

Figure 4-1 shows the cross-section of a parasitic PNPN. The terms ,

crit

coll nI

and

,

crit

coll pI

are the minimum amount of collected current that turn on the parasitic PNP and NPN,

respectively. Latchup will be triggered if the minority carrier current collected by the N-

well of the PNPN (Icoll,n) exceeds ,

crit

coll nI or if the majority carrier current collected by the

P-well of the PNPN (Icoll,p) exceeds,

crit

coll pI .

Standards have been developed to establish methods for determining latchup

characteristics and to define latchup failure criteria. The testing procedure outlined in the

JEDEC standard is designed to trigger latchup between a supply rail and its ground (i.e.,

VDDx and VSSx) [1]. It consists of I-tests and overvoltage tests, with the former referring

to injection of positive and negative current into each input, output, or I/O pin, and the

latter referring to overvoltage testing of each supply pin. Each test associated with

22

external latchup is examined in the following sections. In each case, the roles of substrate

majority and minority carriers in triggering latchup are elucidated.

4.1.1 Negative I-test

The carrier injector is a substrate diode placed near a parasitic PNPN device,

shown in Figure 4-2 (a). Figure 4-3 shows a circuit model corresponding to the cross-

section of Figure 4-2 (a), for the case of a negative transient at the I/O pad. In Figure 4-3,

QPNP1 and QNPN1 represent the cross-coupled bipolar transistors that form the PNPN, and

QNPN2 represents the lateral NPN formed by the N+ cathode of the diode, the P-substrate,

and the N-well.

Most of the electrons injected into the substrate by the diode will recombine with

holes, but some will be collected by the N-well of the PNPN. The resulting N-well

current will flow through RNW. The corresponding I R drop forward-biases the base-

emitter junction of QPNP1. However, turning on QPNP1 is not sufficient to induce latchup.

The collector current of QPNP1 must be large enough to forward-bias the base-emitter

junction of QNPN1. Due to current flow through Rdiode, the substrate in the vicinity of the

undershooting I/O is at a lower potential than VSS; the resulting majority-carrier substrate

current through RPW1 and RSUB tends to reverse-bias the base-emitter junction of QNPN1.

In order for latchup to occur, IC,PNP1 must be large enough to counteract the substrate

current flowing from PW1 to the diode. Latchup is triggered if the current collected by the

N-well is large enough to result in forward-biasing both bipolar transistors. The necessary

current ,critIcoll n is given by

23

, _ , 1

,

1

critBE on P C PNPcrit

coll nNW PNP

V II

R. (4.1)

The first term on the right side of (4.1) counts for the required collected current to trigger

QPNP1, and the second term counts for forward-biasing the base-emitter junction of QNPN1.

The nodal equation at the base of QNPN1 gives the following:

, 1

, _2

1 1

( )

0

trigcrit

diode sub C PNP diodeBE on NNPN

diode sub PW PW

IR R I R

V

R R R R. (4.2)

In (4.2), VBE,on_P and VBE,on_N represent the base-emitter voltage drops of QPNP1 and QNPN1,

respectively, at the PNPN triggering point. The common-emitter current gains of QNPN2

and QPNP1 are represented by NPN2 and PNP1, respectively. The current collected by the

N-well, Icoll, may be related to the substrate current injected by the diode Iinj, as follows:

, 2coll n NPN inj

I I , (4.3)

where NPN2 is the common-base current gain of QNPN2. From (4.3), one finds

,

2

.crit

coll n

trigNPN

II (4.4)

Equations (4.1), (4.2), and (4.4) may be solved for the external latchup trigger current:

1, _ 1 , _

1

1 2

2 2

.

( )1 1

diode sub PW diode subBE ON N PNP BE ON P

PW NWtrig

PNP NPN diodediode sub

NPN NPN

R R R R RV V

R RI

RR R

(4.5)

If RSUB>>RPW1 and RSUB>>Rdiode, then (4.5) reduces to

24

2

, _ , _

1, _ , _1

1 2 1 1

2

1.

1

BE ON N BE ON P

PNPBE ON N BE ON PPW NW

trigPNP NPN NPN PNP PW NW

NPN

V V

V VR RI

R R (4.6)

On the far right-hand side of (4.6), the expression inside the parentheses is equal to ,critIcoll n

and is a function of only the PNPN geometry. From studies of internal latchup, e.g., [20],

it is known that VBE,on_P and VBE,on_N are functions of the PNPN anode-to-cathode

spacing (i.e., P+-to-N

+ spacing). Specifically, for a larger anode-to-cathode spacing, the

current gains of the bipolar transistors inside the PNPN are reduced, and so a larger

forward-bias is needed on each transistor to reach the triggering point. Small well

resistances, RPW1 and RNW, will increase the trigger current for both internal and external

latchup; RPW1 and RNW are layout-dependent parameters. Clearly, the expression inside

the parentheses, ,

crit

coll nI , is correlated with the internal latchup trigger current .

In contrast, NPN2 of (4.6) is relevant only for external latchup. The symbol will

be shortened toNW, and this quantity will be referred to as the collection efficiency.

4.1.2 Positive I-test

In a positive I-test, a positive current source is connected to an I/O pin, and the

top diode of Figure 4-2 (b) will inject substrate current. The corresponding circuit model

for latchup analysis is shown in Figure 4-4. The PNP transistor QPNP2 is formed by the P+

diffusion of the diode, NW2, and the P-substrate. During a positive I-test, QPNP2 injects

holes into the substrate. These majority carriers will forward-bias the base-emitter

junction of QNPN1 as they are collected by PW1. In contrast, the minority carrier substrate

25

current injected by QNPN2 has the wrong polarity to turn on QPNP1. Therefore, for a

positive I-test, majority carriers trigger latchup.

For the circuit of Figure 4-4, one can show

,

2

.crit

coll p

trigPNP

II (4.7)

The term ,

crit

coll pI can be

approximated as

, _ , _

, , 3.BE on N BE on Pcrit

coll p C PNPPW NPN NW

V VI I

R R (4.8)

Note that the base-width and, hence, the current gain of QPNP3 are independent of

ddet. This means that IC,PNP3 is also independent of ddet. Therefore, none of the parameters

in (4.7) or (4.8) are functions of ddet, and thus one expects that for a positive I-test, Itrig

will be insensitive to injector-to-detector spacing. Note that IC,PNP3 is a function of Iinj

and, hence, (4.7) or (4.8) cannot estimate Itrig. Instead, one has to simulate circuit

schematics of Figure 4-4 to find Itrig.

4.1.3 Undervoltage on VDDO

The top N-well diode of Figure 4-2 (c) will also provide substrate current if an

undervoltage event causes VDDIO to dip below the voltage on the I/O pin; analysis of the

corresponding circuit in Figure 4-5 shows that this can result in latchup on a separate VDD

line. In this case, Itrig is defined as the current flowing through power supply VDDIO just

before latchup is triggered.

26

In the circuit of Figure 4-5, QPNP2 injects majority carriers into the substrate. The

collector current of QPNP2 may turn on QNPN1; the corresponding condition is

1 , 2 , _PW C PNP BE on PR I V . In this case, latchup is the result of majority carrier collection.

However, the collector current of QPNP2 may also turn on QNPN2; the condition for this to

occur is 1 , 2 ,PW SUB C PNP DDIO BE on

R R I V V . QNPN2 injects minority carriers into the

substrate, which may trigger latchup. Although this analysis indicates that latchup can be

triggered by either majority or minority carriers, for any specific case, one can easily

determine the underlying cause of latchup. One simply examines whether Itrig varies with

ddet; Itrig is a decreasing function of ddet only when minority carriers trigger latchup.

If QNPN1 turns on before QNPN2, the latchup condition is simply

,

2

.crit

coll p

trigPNP

II (4.9)

A comparison of (4.7) and (4.9) shows that an undervoltage on VDDO can be more

hazardous than positive current injection at the I/O, because β > α.

4.1.4 Considerations for the substrate current

In Figure 4-4 and Figure 4-5, the inclusion of QPNP3 (the parasitic PNP formed by

the P-substrate, NW1, and PW1) might seem unnecessary, but, as will be shown in

Section 5.3, it is required to achieve agreement between measurement and simulation

results. The activity of QPNP3 is highlighted by the experiment sketched in Figure 4-6 (a).

The N+ diffusion of an N-well diode was tied to VDD, the P

+ diffusion in PW1 was

grounded, and positive current was applied to the I/O. All other terminals were left

floating, unless otherwise indicated. The current at the P+ diffusion IPW,1 was measured

27

two times, once with NW1 floating and once with NW1 connected to VDD. Biasing NW1

increases IPW,1, as shown in Figure 4-6 (c). This result can be understood by considering

the effect of QPNP3. Referring to Figure 4-6 (b), when NW1 is floating, QPNP3 remains off.

IPW,1 is initially an increasing function of Iinj, but eventually levels off when QPNP2 is

driven into saturation and the voltage drop across the substrate becomes roughly constant.

In contrast, when NW1 is biased at VDD, IPW1 does not level off. After QPNP2 is driven into

saturation, the emitter voltage of QPNP3 becomes larger than its base voltage, thus

forward-biasing this junction and turning on QPNP3. The forward-bias on the emitter-base

junction is a result of the following relations that are valid when QPNP2 operates in

saturation: VE,PNP3 = VC,PNP2 > VB,PNP2 = VDD; VB,PNP3 < VDD. When QPNP3 turns on,

IC,PNP3 adds to IPW,1. Even though the current through RSUB becomes almost constant

when QPNP2 is driven into saturation, IPW,1 remains an increasing function of Iinj as long as

QPNP3 is not saturated. Therefore, the inclusion of QPNP3 is necessary to accurately model

the majority carrier collection by PW1.

28

4.2 Figures

Figure 4-1: Cross-section of a parasitic PNPN. Icoll,n and Icoll,p are the minority carrier and

majority carrier substrate currents, respectively, collected by this structure.

P-Substrate

PW

VDD

NW

P+N+ N+ P+

VDD

Icoll,pIcoll,n

29

Substrate

PW2

Substrate Current Injector

NW NW

ddet

NGR NGRN+ N+

VDDVDD

NW1

N+ P+ N+ P+

PW1

VSSVDD

P+ P+N+

I/OVSSIOVSSIO

Victim

Substrate

P+ P+ N+ P+

NW2

VSS VSS

Substrate Current Injector

PGRPGR

ddet

NW1

N+ P+ N+ P+

PW1

N+

PWPW

VDD VSS

Victim

I/OVDDIO VDDIO

Substrate

P+ P+ N+ P+

NW2

VSS VSS

PGRPGR

ddet

NW1

N+ P+ N+ P+

PW1

N+

PWPW

VDD VSS

Victim

I/O

VDDIO -ΔVDDIO

Figure 4-2: Setups for (a) a negative I-test, (b) a positive I-test, and (c) an undervoltage

test.

(c)

(b)

(a)

30

RPW1

VDD VDD

VSSVSSVSSIO

Iinj

RSUB

RNW1

Rdiode

QNPN2

QPNP1

QNPN1

I/O

Icoll,n

Icoll,p

Figure 4-3: Circuit-level model of a substrate current injector (bottom diode) and victim

(PNPN) for a negative I-test.

RPW1

VDD VDD

VSSVSS

VDDIO

RNW1

QNPN2

QPNP1

I/O

QPNP2

Iinj

RSUB

QPNP3

QNPN1

Icoll,n

Icoll,p

Figure 4-4: Circuit-level model of injector (top diode) and victim (PNPN) for a positive I-

test.

31

RPW1

VDD VDD

VSSVSSIinj

RSUB

RNW1

QNPN2

QPNP1

QNPN1

I/O

QPNP2

INW

IPW

VDDIO+-

QPNP3

Icoll,n

Icoll,p

Figure 4-5: Circuit-level model of injector (diode) and victim (PNPN) for an

undervoltage on VDDO with a top N-well diode.

32

P-Substrate

P+N+

PW2NW2 NW1

N+ P+

VDD

N+ P+

VSS

PW1

VDD

N+

VDD

Iinj

IPW,1

RPW1

VDD

VSS

VDD

RNW1

QNPN2

I/O

QPNP2

Iinj

RSUB

QPNP3

Icoll,p

0 0.002 0.004 0.006 0.008 0.01

0

1

2

3

4

5

6x 10

-3

Iinj

(A)

I PW

1 (

A)

NW1 is biased

NW1 is floating

(b)

(a)

(c)

Figure 4-6: (a) Experiment setup. (b) Circuit-level model. (c) IPW,1 vs. Iinj with and

without biasing NW1. SmartMOS technology. Room temperature.

33

CHAPTER 5

MEASUREMENT RESULTS AND

DISCUSSIONS

5.1 Test Structures

Test structures were fabricated in four different technologies: 0.25-μm SmartMOS

[32], 0.18-μm RF-CMOS, 0.13-μm CMOS, and 90-nm CMOS. Figure 5-1, Figure 5-2,

and Figure 5-3 show the test structure. In the SmartMOS test structures, the injector has

25 N+-stripes, each 25 μm wide (25 × 25 μm), the N-well detector is 60 μm wide, and

dTAP = 30 μm. In the RF-CMOS test structures, the injector is a 15 μm wide, single-stripe

diode, the victim contains a 15 μm wide N-well, and dTAP = 5 μm. In the 130-nm and 90-

nm CMOS test structures, the injector has four N+-stripes, each 20 μm wide (4 × 20 μm),

and the detector is 20 μm wide. In these structures, dTAP = 40 μm, and dvictim = 5 μm.

Guard rings are 1 μm wide and dPGR = dNGR = 2 μm.

Referring to Figure 5-1, the collection efficiency NWwas measured with the

anode grounded, a negative current source of magnitude Iinj connected to the cathode, the

NW terminal connected to VDD, and all other terminals floating. Since the guard rings are

almost always used in a design, they were added to the test structures but were left

floating when NWwas measured. We found that the induced voltage on a floating NGR

is negative. Since the P-wells are grounded, the P-well/NGR junctions are forward-biased

and do not block the carrier flow.

34

In advanced CMOS technologies, different supply voltages are used with I/O and

core transistors. The supply voltage varies from 2.5 V to 5 V for the I/O and from 1 V to

1.8 V for the core for the technologies used in this work. Parasitic PNPNs are found in

both I/O and core logic circuits, meaning that the victims of Figure 5-1 and Figure 5-2

could have VDD in the range of 1 V to 5 V. However, latchup will be sustained after the

removal of the trigger source only if VDD > 1.2 V [33]. We know that Itrig is a decreasing

function of VDD, but we will show that the effect is small (Section 5.2.3). In this work,

VDD was set to 1.5 V for the 130-nm CMOS and 90-nm CMOS devices and to 2 V for the

0.25-μm SmartMOS and 0.18-μm RF-CMOS devices. VDDIO was also set equal to VDD,

arbitrarily, because Itrig is insensitive to VDDIO.

A semiconductor parameter analyzer is used to ramp the injection current and

provide VDD. It has four SMUs (source-measure units), which can simultaneously provide

voltage and measure current.

5.2 Collection Efficiency

5.2.1 Layout geometry

As evident from the data of Figure 5-4 and Figure 5-5, collection efficiency is a

decreasing function of ddet because more electrons recombine within the substrate as ddet

increases.

As shown in Figure 5-6 and Figure 5-7, NW is an increasing function of Wdet and

Ldet because more carriers are collected as the area of the victim increases. Note that Wdet

is set equal to the width of the N-well, rather than the width of the N+ diffusion inside the

well, because measurement data show that NW is a far stronger function of the former

35

dimension [34]. Data also indicate that the width and the length dependences are

nonlinear.

5.2.2 Temperature

The data of Figure 5-4 and Figure 5-5 also show that the collection efficiency is

an increasing function of temperature. This dependence is expected when NW is

interpreted as the common-base current gain of a bipolar transistor,

T

, (5.1)

where is the emitter injection efficiency and is the base transport factor. For an

ordinary, vertical bipolar transistor, NW is dominated by the emitter injection efficiency,

which is an increasing function of temperature [35], in agreement with the data of Figure

5-4 and Figure 5-5. Moreover, the NPN lying between the injector and the detector,

QNPN2, has a very long base and, thus, the base transport factor significantly affects the

value of NW. The base transport factor is also an increasing function of temperature

because, in the range 0–125 oC, carrier lifetime is an increasing function of temperature

[36]; base recombination is thus reduced as temperature increases. Therefore, the

experimental results for NW(T) are consistent with theory.

5.2.3 Bias conditions

Let Vdet denote the bias voltage of the N-well of the victim. Then NW is an

increasing function of the bias voltage of the detector Vdet, as shown in Figure 5-8. This

behavior is consistent with the Early effect in bipolar transistors:

36

detdet

0 1NW NW

A

VV

V. (5.2)

Physically, however, the observed voltage dependence is not due to the Early

effect. If the Vdet dependence were a result of the Early effect, then the extracted Early

voltage, VA, would be an increasing function of ddet. The data in Figure 5-9 and Figure

5-10 show that the extracted Early voltage is fairly insensitive to ddet. Furthermore, the

extracted values of VA are much smaller than would be expected for the true Early effect.

It is further noted that VA is insensitive to temperature.

We claim that the change in the area of the detector Acol is the reason for the

voltage dependence of NW. One should note that Acol is larger than what is extracted

from the layout because the depletion region of the N-well/substrate junction extends the

detector into the substrate, as illustrated by the dashed lines in Figure 5-11. The area of

the extended detector is defined as Acol and is equal to

det , det , det , ,

det , ,

2 2 2 2

2 2 .col D PW D PW D PW j D SUB

D PW j D SUB

A W X L X W X X X

L X X X (5.3)

In (5.3), XD,PW and XD,SUB are the width of the N-well/P-well and N-well/substrate

depletion regions, respectively. They are functions of the P-well, substrate, and N-well

doping levels (NPW, NSUB, and NNW, respectively) as well as Vdet, as indicated in (5.4).

1

, det

1

, det

2 1 1

2 1 1

ns

D PW iNW PW

ns

D SUB iNW SUB

X Vq N N

X Vq N N

. (5.4)

37

In (5.4), φi is the built-in voltage of the N-well/substrate junction, and n depends on the

gradient of the change in the doping profiles at the N-well/P-well or N-well/substrate

junctions. For an abrupt junction, n = 2. From (5.3) and (5.4), one concludes that Acol is

an increasing function of Vdet. We know that NW is an increasing function of the

collector area. Therefore, one expects NW to be an increasing function of Vdet. Equation

(5.3) predicts that the relative increase in Acol will be more pronounced for smaller

detector geometries. Therefore, one should expect VA to be an increasing function of Wdet

and Ldet. This expectation is borne out by the data of Figure 5-12 and Figure 5-13.

Figure 5-14 shows that NW is a function of the injection current Iinj. This

observation is consistent with the behavior of bipolar transistors under high-level

injection conditions. As Iinj increases, the electron density in the substrate increases. At

some point, the electron density exceeds the substrate doping density, and the density of

the majority carriers then starts to increase to maintain charge neutrality in the substrate.

Therefore, similarly to the current gain of a bipolar transistor, one expects NW to be a

decreasing function of Iinj under high-level injection conditions.

5.2.4 N-well guard rings

The term *

NW denotes the collection efficiency of the detector measured with the

N-well guard rings (NGRs) tied to the positive voltage supply. As shown in Figure 5-15,

wide guard rings that are placed close to the injector are most effective in reducing

current collection by the detector. At moderate current levels, guard rings reduce carrier

collection by the detector by 90% or more (Figure 5-15); however, this does not imply

that the latchup trigger current is increased by about an order of magnitude. A measure of

38

guard ring efficiency is * /NW NW

which is between 0 and 1. Measurement results show

that guard rings are less efficient at the high current levels typically needed to trigger

latchup (Figure 5-16).

5.2.5 Multiple detectors

In this experiment, *

NWis measured with the secondary detector rather than with

the NGRs activated (Figure 5-17). The primary and secondary detectors are equidistant

from the injector. Note that unlike a guard ring, a secondary detector is not a ring and

does not surround the injector. It simply represents the N-well of another victim. One

might expect that the presence of an identical second detector will lower *

NW by a factor

of one-half relative to NW

, but this is contradicted by the data of Figure 5-18, which

show a smaller effect. A 2-D device simulation provides insight. The simulated electron

current flow is shown in Figure 5-19. In Figure 5-19 (a), only the primary detector is

active, whereas both detectors are active in Figure 5-19 (b). The effect of the second

detector diminishes as the spacing increases, as shown by the measurement data in Figure

5-20. These effects may be understood as follows.

For the case of a single detector, some of the electron flux that initially flows

leftward from the injector (labeled Group II in Figure 5-19 (a)) will be collected by the

primary detector on the right side of the injector. When both detectors are activated, the

carriers in Group II are collected by the second detector (see Figure 5-19 (b)), which

explains the reduced collection efficiency ( *

NW<

NW); however, the effect is limited

because the flux contained in Group II is less than that in the Group I. Furthermore, the

data of Figure 5-20 indicate that the effect of the second detector diminishes as ddet,L is

39

made larger. This is because at large ddet,R, the secondary victim collects the carriers that

otherwise recombine in the substrate. Therefore, as ddet,L increases, *

NWapproaches

NW.

The effect of the second detector is also reduced when NGR is active (Figure 5-21).

Table 5-1 lists *

,NW R measured when the primary and secondary detectors are not

equidistant from the injector. When det, det,R Ld d , activating NWL has only a small

effect on carrier collection at NW:

*

, ,NW R NW R. (5.5)

In fact, (5.5) provides a reasonable, albeit conservative, estimate of *

,NW R, except for the

case of small ddet, where small means that ddet is much less than the electron diffusion

length in the substrate (tens of m [34]). For small ddet, *

,NW R may be significantly less

than predicted by (5.5), especially for the case det, det,L Rd d .

5.2.6 P-type guard rings

The collection efficiency of the primary detector when the P-well guard ring

(PGR) is grounded (i.e., activated) is NW

. In this experiment, the NGR and secondary

detector are inactive. Since PGRs collect majority carriers, whereas this experiment

measures minority carrier collection, one might expect the PGRs to have no effect.

However, the PGRs increase the collection efficiency of the detector (Figure 5-22), and

the effect worsens as the PGR is moved closer to the detector (Figure 5-23). Device

simulation results are shown in Figure 5-24. Figure 5-24 (a) and Figure 5-24 (c) are for

the case that the PGRs are inactive, and Figure 5-24 (b) and Figure 5-24 (d) are for an

40

activated PGR. In Figure 5-24 (c), the current density along the injector PN junction is

highly non-uniform; it is highest at the edges and lowest near the middle of the bottom

surface of the junction. This indicates there is a non-uniform potential along the PN

junction. The potential varies due to IR drops caused by the laterally directed hole

current, analogous to the non-uniform base resistance effect in bipolar junction transistors

(BJTs) [37]. Current crowding at the edges of the junction causes high-level injection

effects to occur at a lower current level than they would if the current density were

uniform. In Figure 5-24 (d), the current density along the injector PN junction is more

uniform because more of the hole current (base current) is flowing vertically. Therefore,

for a fixed injection current, high-level injection effects are reduced when the PGR is

active. The PGR increases collection efficiency by delaying the onset of high-level

injection, as is evident from the data of Figure 5-22. Note that NW NW

at low Iinj.

The deleterious effect of PGR is especially pronounced when NGR is active (Figure

5-25). The deleterious effect of PGR is also observed if one measures the latchup trigger

current instead of the minority carrier collection efficiency.

5.2.7 P-well taps

Similarly to PGRs, an active P-well tap (PT) increases the collection efficiency

(Figure 5-26). A PT on the same side of the injector as the detector has a bigger impact

than does one on the opposite side (Figure 5-27). This is because PTR increases current

uniformity on the right side of the junction, which increases the number of electrons

injected toward the detector.

41

5.3 Measurement Results of Itrig

Figure 5-28 shows Itrig as a function of ddet for a positive I-test (Figure 5-1 (b)).

The device dimensions are given in Section 5.1. The resistors RNW_ext and RPW_ext are

external resistors optionally added in series with the N+ and P

+ diffusion in NW1 and PW1

(Figure 5-1 (b)), respectively, in order to emulate the effect of a large well tap spacing.

Figure 5-28 shows that Itrig is insensitive to ddet; this is expected from Section 4.1.2

because latchup is triggered by majority carriers during a positive I-test. For a fixed

RNW1, increasing RPW1 lowers Itrig as predicted by (4.8). In contrast, for a fixed RPW1, Itrig

is an increasing function of RNW1. One may notice that the first two terms of (4.8)

indicate that ,

crit

coll pI is a decreasing function of RNW1. However, increasing RNW1 will also

lower IB,PNP3, which in turn lowers IC,PNP3. As a result, increasing RNW1 lowers the current

through RPW1, requiring a higher Iinj in order to forward-bias the base-emitter junction of

QNPN1 and trigger latchup. Although increasing the N-well resistance was shown here to

provide increased resistance against positive external latchup, it is not recommended as a

latchup prevention method because it increases the susceptibility to negative external

latchup [38], and also increases susceptibility to internal latchup.

Figure 5-29 shows Itrig as a function of ddet for an undervoltage test, as shown in

Figure 5-1 (c). As discussed in Section 4.1.3, either majority or minority carriers can

trigger latchup during an undervoltage test. The data of Figure 5-29 show that Itrig is an

increasing function of ddet. Therefore, latchup was triggered by minority carriers in these

experiments.

42

Table 5-2 summarizes the results of measuring Itrig on a variety of test structures

at an elevated temperature of 125 ºC. The Itrig values of both the positive and negative I-

tests are decreasing functions of temperature; this is supported by previous works [3],

[38]. For example, in the positive I-test, raising the temperature decreases Itrig by a factor

of ~ 3.5. Because of the positive temperature dependence of the N-well and P-well

resistances, Itrig is a decreasing function of temperature. In addition, Itrig of a negative I-

test is a decreasing function of temperature because of the positive temperature

dependence of NW [34].

The data in Table 5-2 show that Itrig is a decreasing function of dTAP for both a

positive I-test and an undervoltage test. RPW1 and RNW1 are increasing functions of dTAP.

For a positive I-test, increasing RPW1 lowers Itrig, while increasing RNW1 increases Itrig. The

data shown in the table indicate that the effect of RPW1 is dominant; Itrig is a decreasing

function of dTAP. Furthermore, the data indicate that Itrig of an undervoltage test is a

stronger function of dTAP than is Itrig of a positive I-test. We expect Itrig to be an especially

strong function of dTAP when latchup is triggered by minority carriers, as in this

undervoltage experiment. Increasing dTAP not only increases the well resistances, it also

increases NW, which further lowers Itrig. The value of NW is an increasing function of

dTAP because structures with increased dTAP have larger Ldet. Therefore, Icoll,n becomes an

increasing function of dTAP which means that smaller Iinj can trigger latchup.

43

5.4 Figures

Substrate

PW2

Substrate Current Injector

NW NW

dvictim = ddet

NGR NGRN+ N+

VDDVDD

NW1

N+ P+ N+ P+

PW1

VSSVDD

dTAP

P+ P+N+

I/OVSSIOVSSIO

Victim

dNGRLNGR

Substrate

P+ P+ N+ P+

NW2

VSS VSS

Substrate Current Injector

PGRPGR

dvictim = ddet

NW1

N+ P+ N+ P+

PW1

N+

PWPW

VDD VSS

Victim

I/OVDDIO VDDIO

dPGRLPGR

Substrate

P+ P+ N+ P+

NW2

VSS VSS

PGRPGR

ddet

NW1

N+ P+ N+ P+

PW1

N+

PWPW

VDD VSS

Victim

I/O

VDDIO -ΔVDDIO

Figure 5-1: Test structure cross-sections for (a) a negative I-test, (b) a positive I-test,

and (c) an undervoltage test. The victims are oriented 180º.

(c)

(b)

(a)

44

Substrate

PW

Substrate Current Injector

NW NW

dvictim

NGR NGRN+ N+

VDDVDD

N+P+N+P+

PW1

VSS VDD

dTAP

P+ P+N+

I/OVSSIOVSSIO

Victim

dNGRLNGR

NW1

ddet

Substrate

P+ P+ N+ P+

NW

VSS VSS

Substrate Current Injector

PGRPGR

dvictim

NW1

N+P+N+P+N+

PW1PW

VDDVSS

Victim

I/OVDDIO VDDIO

dPGRLPGR

GR

NW

ddet

Victim

Winj

Ldet

Wdet

Injector

(b)

(a)

Figure 5-3: Top view of a test structure with a single-finger injector.

Figure 5-2: Test structure cross-sections for (a) a negative I-test and (b) a positive I-test.

The victims are oriented 0º.

45

Figure 5-4: αNW vs. ddet and temperature. RF-CMOS technology.

Figure 5-5: αNW vs. ddet and temperature. SmartMOS technology.

0 20 40 60 80 1000.015

0.02

0.025

0.03

0.035

0.04

0.045

0.05

0.055

0.06

ddet

(m)

N

W

T=25 C

T=75 C

T=100 C

0 20 40 60 80 1000.015

0.02

0.025

0.03

0.035

0.04

0.045

0.05

0.055

0.06

ddet

(m)

N

W

T=25 C

T=75 C

T=100 C

46

Figure 5-6: αNW vs. Wdet. 90-nm CMOS technology. Room temperature.

Figure 5-7: αNW vs. Ldet. 90-nm CMOS technology. Room temperature.

0 10 20 30 400

0.02

0.04

0.06

0.08

0.1

0.12

0.14

0.16

Detector width (m)

N

W

20 30 40 50 60 70 800

0.02

0.04

0.06

0.08

0.1

0.12

0.14

Detector length (m)

N

W

47

Figure 5-8: αNW as a function of detector voltage Vdet and ddet. RF-CMOS technology.

Room temperature.

Figure 5-9: VA as a function of ddet. VA is fairly insensitive to spacing. 90-nm CMOS

technology. Room temperature.

0 0.5 1 1.5 20.015

0.02

0.025

0.03

0.035

0.04

0.045

0.05

Vdet

(V)

N

W

ddet

= 13 m

ddet

= 30 m

ddet

= 50 m

0 200 400 600 800 10000

5

10

15

20

25

30

35

40

ddet

(m)

|VA|

(V)

48

Figure 5-10: VA as a function of ddet and temperature. VA is fairly insensitive to spacing

and temperature. RF-CMOS technology.

Detector

Substrate

NW

Vdet

N+

XPW

LdetXD,PW

PW

XD,SUB

Figure 5-11: Device cross-section of the detector. The dashed lines show the boundaries

of the depletion region formed around the detector. Acol is the area of the region enclosed

by the dashed lines.

0 20 40 60 800

1

2

3

4

5

6

7

8

ddet

(m)

|VA|

(V)

T=25 C

T=75 C

T=100 C

49

Figure 5-12: VA as a function of Wdet. 90-nm CMOS technology. Room temperature.

Figure 5-13: VA as a function of Ldet. 90-nm CMOS technology. Room temperature.

0 10 20 30 40 5010

15

20

25

30

35

40

Wdet

(m)

|VA|

(V)

0 20 40 60 80 10010

15

20

25

30

35

Ldet

(m)

|V

A| (

V)

50

Figure 5-14: Measured NW vs. Iinj. NW decreases at high currents. P-well type injectors.

SmartMOS technology. Room temperature.

Figure 5-15: Ratio of *

NW to

NW for different NGR layouts.

NWand *

NWare extracted

at the current level that gives the highest NW

( = 0.11). ddet = 49 µm. 130-nm CMOS

technology.

10-6

10-4

10-2

100

0

0.5

0.10

0.15

0.20

0.25

0.30

0.35

0.40

Iinj

(A)

N

W

2 2.5 3 3.5 4 4.5 5 5.50.05

0.06

0.07

0.08

0.09

0.1

0.11

0.12

0.13

dNGR

(m)

* N

W/

NW

LNGR

= 1(m)

LNGR

= 2(m)

LNGR

= 4(m)

51

Figure 5-16: *

NW/NW

vs. current injected at the I/O. LNGR = 1 µm and ddet = 49 µm. 90-

nm CMOS technology.

Figure 5-17: Device cross-section of the test structures designed to investigate the effect

of a secondary detector.

0 5 10 15 200.08

0.1

0.12

0.14

0.16

0.18

0.2

0.22

Iinj

(mA)

* N

W/

NW

Primary

detector

Secondary

detector

Substrate

NWLNWR

P+ P+ P+N+ P+

PW

I/O

VSSIO

VSS VSSVDD VDD

Substrate Current Injector

PGR / PTRPGR / PTL

NW NW

ddet,Rddet,L

NGR NGR

N+ N+

dNGR

N+ N+

VDDVDD

52

Figure 5-18: ,NW R

and *

,NW Ras a function of Iinj. The NGRs and PGRs are inactive.

ddet,R = ddet,L = 49 µm. 130-nm CMOS technology. The presence of a second detector

slightly reduces carrier collection by the primary one.

Figure 5-19: Electron current flow lines when (a) only NWR (primary victim) is active,

and (b) both NWR and NWL (secondary victim) are active. NWL collects the electrons

from Group II and leaves fewer electrons for NWR, the primary detector.

0 2 4 6 8 100.05

0.06

0.07

0.08

0.09

0.1

0.11

Iinj

(mA)

Collection e

ffic

iency

NW,R

NW,R*

(a)

Injector NWR NWL

Group II

Group I

(b)

Injector NWR NWL

53

Figure 5-20: *NW,R /NW,R vs. injector-to-detector spacing. ddet,R = ddet,L. αNW,R and α

*NW,R

are extracted at Iinj corresponding to the highest αNW,R. 130-nm CMOS technology.

Figure 5-21: ,NW R

and *

,NW Rvs. Iinj. NGR is activated. Data obtained from device

simulation. The effect of a second detector is less noticeable when NGR is used (compare

with Figure 5-18).

0 10 20 30 40 50 60

0.65

0.7

0.75

0.8

0.85

0.9

0.95

1

ddet,R

(m)

N

W,R

* /

N

W,R

0.2 0.4 0.6 0.8 10.02

0.025

0.03

0.035

0.04

0.045

0.05

Iinj

(mA)

Collection e

ffic

iency

Second detector active

Second detector inactive

54

Figure 5-22: NW

and NW

vs. Iinj. ddet = 49 µm and dPGR = 6.5 µm. 130-nm CMOS

technology. Collection efficiency increases when PGR is active, increasing the latchup

hazard.

Figure 5-23: / *100NW NW NW

as a function of the relative placement of the

PGR. Data obtained from device simulation. The effect of PGR is heightened when they

are placed closer to the detector.

10-3

10-2

10-1

100

101

0.05

0.06

0.07

0.08

0.09

0.1

0.11

0.12

Iinj

(mA)

Collection e

ffic

iency

+NW

NW

0.1 0.2 0.3 0.4 0.5 0.6 0.724

26

28

30

32

34

36

38

40

dPGR

/ ddet

Incre

ase in

NW

(%

)

55

Figure 5-25: Collection efficiency vs. Iinj. NGRs are active. dNGR = 3.5 µm, dPGR = 4.5

µm, and ddet = 50 µm. 130-nm CMOS technology. Active PGR increases minority carrier

collection by the detector.

0 5 10 15 20 25 300.012

0.014

0.016

0.018

0.02

0.022

0.024

Iinj

(mA)

Collection e

ffic

iency

PGR active

PGR inactive

Figure 5-24: Current flow lines for (a) inactive PGR ((c) zoomed-in view), and (b) active

PGR ((d) zoomed-in view). In (a), hole current is injected only from the injector P+

diffusions; but in (b), the current is also injected from the PGR.

(a)

Injector PGR PGR NW

R

(b)

Injector PGR PGR NW

(d)

N+

(c)

N+

56

Figure 5-26: Collection efficiency vs. Iinj with and without an active PT on the right side.

NGRs, PTL, and the secondary detector are inactive. ddet = 49 µm and dPGR = 5 µm. 90-nm

CMOS technology.

Figure 5-27: Collection efficiency with PTL and PTR individually activated. Data

obtained from device simulation.

0 2 4 6 8 10

0.08

0.09

0.1

0.11

0.12

0.13

0.14

Iinj

(mA)

Collection e

ffic

iency

+NW

NW

2 4 6 8 100.03

0.04

0.05

0.06

0.07

0.08

0.09

Iinj

(mA)

Collection e

ffic

iency

Inactive PTL and PT

R

Only PTL is active

Only PTR is active

Active PTL and PT

R

57

Figure 5-28: Itrig is plotted as a function of injector-to-PNPN spacing for a positive I-test

with an N-well injector. 180º victim orientation. SmartMOS technology. Room

temperature.

Figure 5-29: Itrig is plotted as a function of injector-to-PNPN spacing for an undervoltage

test (see Figure 4-5). An external resistor (RNW_ext = 10 kΩ) is connected to the N-well

contact of the PNPN to increase RNW. Without RNW_ext, Itrig is outside the range of the

measurement equipment (>100 mA). 180º victim orientation. SmartMOS technology.

Room temperature.

0 5 10 150

5

10

15

20

25

ddet

(m)

I trig

(m

A)

RNW_ext

=10 k RPW_ext

=200

RNW_ext

=10 k RPW_ext

=0

RNW_ext

=0 RPW_ext

=0

0 5 10 1518

20

22

24

26

28

30

32

ddet

(m)

I trig

(m

A)

58

5.5 Tables

Table 5-2: Measured Itrig. 125 ºC. 180º victim orientation. SmartMOS technology. All

PNPN dimensions are held constant in the experiments, except dTAP. Injectors are N-well

diodes. ddet scales with dTAP in the test structures.

Positive I-test Undervoltage test

dTAP = 30 μm 3.7 mA 13.6 mA

dTAP = 50 μm 2.2 mA 1.7 mA

Table 5-1: *

,NW Ras a function of both ddet,R and ddet,L.

,NW Rand *

,NW Rare extracted at

the injection current corresponding to the highestNW

. 130-nm CMOS technology.

ddet,R (µm) ddet,L (µm) ,NW R

,NW L *

,NW R

5 14 0.34 0.23 0.29

14 5 0.23 0.34 0.11

49 57 0.11 0.09 0.097

57 49 0.09 0.11 0.077

59

CHAPTER 6

MODELING THE LATCHUP TRIGGER

CURRENT The purpose of this chapter is first to provide a semi-physical analytical model for

the collection efficiency of a detector, NW. Then, with a model for NW in place, Itrig is

obtained by simulating the proposed circuit models.

6.1 Collection Efficiency of a Single Detector

First, the case of a single minority carrier detector is studied. This occurs when

other N-well regions except the primary detector are floating or non-existent. Therefore,

carriers that are injected to the substrate either recombine with the majority carriers or are

collected by the single detector.

6.1.1 Effects of spacing

Collection efficiency NW is a decreasing function of ddet, as explained in Section

5.2.1. This section proposes a semi-physical analytical model for NW as a function of

ddet.

To find the current collected by the detector, the electron distribution in the

substrate must be first determined by solving the diffusion equation,

2

2

p

p

n

nn

L (6.1)

60

In (6.1), Ln is the electron diffusion length in the substrate. Given the electron

distribution, one may calculate the current crossing the boundary of the detector by

solving

n n pJ qD n (6.2)

A closed-form, analytic solution to (6.1) does not exist for the geometry of the test

structures [39]. A closed-form solution may be obtained only by simplifying the problem

geometry. Two sets of approximations are used: one when ddet is smaller than or close to

Ln and the other when ddet >> Ln. The former is called the near spacing model and the

latter the far spacing model.

The near spacing model

If the injector width, Winj, is much less than ddet, then the injector may be modeled

as a point source, and (6.1) should be solved using spherical coordinates. Conversely, if

Winj >> ddet, then the injector may be modeled as an infinitely long line source, and a

cylindrical coordinate system is used. Neither inequality is valid for all values of Winj and

ddet used in this work; nevertheless, good results are obtained using the line-source model

[40].

For an infinitely long line source of minority carriers, centered at the origin of the

coordinate system, (6.1) may be rewritten as

2

2 2

2 2

( ), 0p p p

n

n n n rr r r r

rr L. (6.3)

A Neumann boundary condition is taken at the silicon surface, i.e., the normal

component of the current is zero. Below the silicon surface, for a finite-sized detector, the

61

boundary condition for (6.3) will be spatially non-uniform. Further simplification of the

problem geometry is needed in order to obtain a closed-form solution.

Case I: No detector

First, (6.3) is solved for the case that there is no detector. In this case, one

boundary condition is

lim ( ) 0prn r . (6.4)

The solution to (6.3) is thus

1 0p

n

rn r C K

L, (6.5)

where K0(x) is the modified Bessel function of the second type and order zero.

Define *

injI as the current injected into the substrate per unit length. C1 in (6.5) is

found by substituting (6.5) into (6.2) and setting

*

0

10 lim

n injrJ I

r. (6.6)

One thus obtains

*

1

inj

n

IC

qD, (6.7)

where γ is the electron injection efficiency, defined as the ratio of the injected electron

current to the total injected current.

n n

n p

inj inj

inj inj inj

I I

I I I. (6.8)

From (6.2), (6.5) and (6.7), one obtains

62

*

1

inj

nn n

I rJ r K

L L, (6.9)

where K1(x) is the modified Bessel function of the second type and order one.

Case II: Radially uniform detector

Next, (6.3) is solved for the case that one boundary condition is det

0pn r d .

Indeed, 0pn is the boundary condition at the edge of the depletion region outside the

real detector, provided the carrier velocity inside the N-well is not saturated [41]. The

solution to (6.3) is

1 0 2 0

( ) , 0p

n n

r rn r C K C I r

L L, (6.10)

where I0(x) and K0(x) are the modified Bessel functions of the first and the second type,

respectively, and order zero.

Using (6.6) as the boundary condition at r = 0, one obtains

*

1

inj

n

IC

qD. (6.11)

The value of C2 is found by satisfying the boundary conditiondet

0pn r d :

det0

2 1

det0

n

n

dKL

C Cd

IL

. (6.12)

Current density is found using (6.2), (6.10), (6.11), and (6.12):

63

det* 0

1 1

det0

inj n

n

n n n

n

dK

I Lr rJ r K I

L L LdIL

, (6.13)

where I1(x) is the modified Bessel function of the first type and order one.

General solution

The device simulation results of Figure 6-1 indicate that the diffusion current in

the substrate follows two main trajectories. Group I flow lines leave the injector as if

there were no detector. Some of these lines bend in the vicinity of the detector, but the

carrier density is given to the first order by (6.5). Group I carriers are primarily collected

by the bottom plate of the reverse-biased N-well/P-substrate junction.

Group II flow lines leave the injector as if there were a radially uniform detector.

The carrier density is given by (6.10). Group II carriers are primarily collected by the N-

well detector sidewall that lies closest to the injector.

For Group I, the collected current may be written using (6.9):

, det, 1

inj

col I I I injn n inj

IrI G K I

L L W. (6.14)

For Group II, the collected current may be written using (6.13):

det0

, det, 1 1

det0

injn

col II II II inj

n n n inj

n

dK

ILr rI G K I I

L L L WdIL

(6.15)

64

Above, Winj is the injector width. det,IG and

det,IIG are the geometric factors that model

the effective collection areas.

Assuming that some fraction ρ of the minority carriers in the substrate falls into

Group I and the rest into Group II, the total collected current may be written as

, ,

1 1coll col I col II I II injI I I I . (6.16)

In Figure 6-2 and Figure 6-3, measurement results for both technologies are

compared with the model in Equation (6.16). det,IG ,

det,IIG , and ρ are treated as fitting

factors to get the best overall fit. As expected for a physics-based model, the extracted

values of Ln are the same order of magnitude, 55 m and 25 m for RF-CMOS and

SmartMOS technologies, respectively. Furthermore, the fit of the model to data is good.

Note that for multi-stripe devices, each finger is considered as a separate injector. The

solution is then found using the superposition principle, as a sum of solutions for each

single-finger injector. In the results of Figure 6-2 and Figure 6-3, ρ is treated as a fitting

factor. We found that ρ is independent of the layout parameters as long as ddet is less or

slightly greater than Ln.

The far spacing model

A different approach is needed to model the collection efficiency when ddet >> Ln.

Equation (6.16) fails because the current flow lines cannot be divided into Group I or II

unless ρ is modeled as a function of ddet. Instead, a different set of approximations is

sought to solve the diffusion equation in the substrate.

65

The carrier collection over the surface of the detector is not uniform. The parts of

the detector that are closer to the injector collect most of the carriers, whereas those that

are farther away collect fewer. However, when ddet >> Ldet, we can assume that the

carriers are uniformly collected over the surface of the detector; i.e., Jcol is the same over

the surface. As will be shown, this will let us use a boundary construction approach to

solve (6.1). Similarly to the near spacing model, further approximations are needed to

simplify the geometry.

Spherical coordinate system

The injector is taken as a point source injn

in the spherical coordinate system, and

the detector as a full sphere (Figure 6-4 (a)). Note that only the carriers collected by the

bottom half of the sphere contribute to NW. In the case of Figure 6-4 (a), by removing

the detector and inserting an image sink 0imn , one can always construct a second case

that gives the same solution for np everywhere in the substrate. This is shown in Figure

6-4 (b). One can see that the current flow lines of Figure 6-4 (a) and Figure 6-4 (b) have

the same form. This occurs only with careful choice of imn .

In the case of Figure 6-4 (b), the electrons in the substrate originate from either

injn

or

imn . Those from the former have the density of

1

, 1

1

n

r

L

p s inj

en r n

r, (6.17)

and those from the latter

66

2

, 2

2

n

r

L

p im im

en r n

r. (6.18)

In (6.17) and (6.18), r1 and r2 are the distance from injn and

imn , respectively. The final

solution can be found using the superposition principle

1 2 , ,,

p p s p imn r r n n . (6.19)

Here, imn must be determined before using (6.19). Although the detector is

removed from the geometry of the case of Figure 6-4 (b), it is useful to consider the

dashed sphere in Figure 6-4 (b) as a virtual detector. We define the current collected by

the virtual detector as the integral of the current density over the surface of the dashed

sphere. The solutions for np in the case of Figure 6-4 (a) and Figure 6-4 (b) are identical if

the boundary conditions at the surface of the detector and virtual detector are the same.

For the case of Figure 6-4 (a), 0pn over the surface of the detector. Hence,

imn must

be chosen to enforce 0pn along the surface of the virtual detector in the case of Figure

6-4 (b). At r1 = ddet and at r2 = Ldet/2, the surface of the virtual detector, (6.19) gives

det det

2det

det

det det

,2

2

n n

d L

L L

p inj im

L e en d n n

d L. (6.20)

To have 0pn along the surface of the virtual detector,

det det2

2det

det2

n

L d

L

im inj

Ln e n

d. (6.21)

Therefore, the current density along the surface of the virtual detector is

67

det

det1 det 2

det

2

, , 2,2 det

12

4

n

L

LnLcol n p s p im n imr d r

L

LJ qD n n qD e n

L. (6.22)

When injn and

imn satisfy (6.21), the solutions for np in the case of Figure 6-4 (a) and

Figure 6-4 (b) are identical. Hence, the current collected by the detector and the virtual

detector are the same, and (6.22) represents the current collected by either of them.

Collection efficiency is found as

det det

detdet det

det det

1 12

2n n

d d

col L L

NW

inj n

J dS LL e G e

I L d d, (6.23)

where Gdet is a geometry factor. The fit of the model to the measurement results is shown

in Figure 6-5 (dashed line). The model closely follows the measurement results.

Cylindrical coordinate system

If the injector and the detector widths are large and comparable to ddet, then the

spherical coordinate system cannot be used because the injector can no longer be

represented by a point source. The cylindrical coordinate system is a better

approximation for these cases. The injector is taken as an infinitely long line source and

the detector as a cylinder. Similarly to the approach presented in the previous section, the

detector is replaced with an image imn with opposite polarity. To have 0

pn

along the

surface of the virtual detector, injn and

imn

must satisfy the following equation

68

det0

det0 2

n

im inj

n

dKL

n nL

KL

. (6.24)

It can be shown that collection efficiency has the following form,

' detdet 1NW

n

dG K

L, (6.25)

where '

detG is a geometry factor. Figure 6-5 compares the fit of the models in the spherical

and cylindrical coordinate systems to the measurement results. Both models accurately

predict the results.

The general model

Previous sections suggest that two models for NW are needed, one for near

spacing and the other for far spacing. The former is used when ddet is smaller or around

Ln, while the latter is used when Ln<<ddet. Occasionally, one may need to try both to

decide which one to use. Another problem with the proposed models is the difficulty of

implementation in circuit simulators. For example, use of the Bessel functions in circuit

simulators may be computationally inefficient.

The need to have two separate models for NW can be eliminated by using a

generalized model that gives a reasonable estimate of NW at all ddet. We propose an

exponential-based equation in the from of

det

detn

d

L

NWG e . (6.26)

69

In (6.26), detG and

nL are fitting factors and are different from Gdet and Ln, respectively.

Physical estimates of Gdet and Ln can be used as initial guesses for extracting detG and

nL . Figure 6-6 shows that the fit to the measurement results is reasonably good. Note that

the fitting factors are chosen to minimize the absolute mean square error, which explains

why the fit is much better for higher NW. Error in calculating NW at very far spacing is

acceptable because the latchup hazards at such spacing are minimal. Equation (6.26) can

be easily implemented in circuit simulators.

Multi-finger injectors

Collection efficiency when the injector has more than one stripe can be modeled

in two ways. In the first, the multi-finger injector is treated as a single-finger injector

placed at a distance ddet,s from the detector; then, ddet,s is taken as a fitting parameter and

det det, dets injd d d L , where Linj is the length of the injector. In the second, each

finger is treated as a separate injector, and the collection efficiency is obtained as

,

1

m

NW NW ii

. (6.27)

In (6.27), m is the number of fingers, and NW,i is the fraction of the carriers injected by

the ith

finger that is collected by the detector. The results of both methods are similar. The

second method is preferred and used in this work because it has one fewer fitting factor,

ddet,s, which simplifies the model extraction procedure.

70

6.1.2 Effects of bias voltage

The collection efficiency is an increasing function of Vdet (refer to Section 5.2.3).

Empirically, this can be well modeled using an Early voltage construct, as indicated in

(6.28).

det

det0 1

A

VV

V. (6.28)

The fit of the model to the measurement results is shown in Figure 6-7. Section 5.2.3

shows that, although insensitive to ddet, VA is a function of Wdet and Ldet. Hence, a model

for VA as a function of Ldet and Wdet should accompany equation (6.28).

The area of the detector is a function of the depletion width of the N-well/P-well and N-

well/substrate junctions XD,PW and XD,SUB, respectively (refer to (5.3)). Here for

simplicity, we assume , ,D PW D SUB D

X X X . The terms 0

colA and DDV

colA denote the

detector area for Vdet = 0 and Vdet = VDD, respectively, and are equal to

0 0 0 0 0

det det det

0 0

det

2 2 2 2

2 2 ,col D D D j D

D j D

A W X L X W X X X

L X X X (6.29)

and

det det det

det

2 2 2 2

2 2 .

dd ddV VVDD VDD VDD

col D D D j D

VDD VDD

D j D

A W X L X W X X X

L X X X (6.30)

In (6.29) and (6.30), 0

DX and DDV

DX denote the depletion width of the detector/substrate

junction for Vdet = 0 and Vdet = VDD, respectively. It can be shown that

71

0 2

det det10 2 2 3 2DDV

col col D D jA A X X W X L , (6.31)

where

0DDV

D D DX X X . (6.32)

Therefore,

2

det det

0

det det det det

10 2 2 3 21

2

DDVD D jcol

col j

X X W X LA

A W L X W L. (6.33)

From (6.28),

0

01

0

NW DDA DD

NW DD NW NW DD

NW

VV V

V V. (6.34)

The data of Figure 6-8 indicate that NW is an increasing function of Acol, and that the

dependence can be modeled by

1 2NW colC A C . (6.35)

Therefore,

1 20

1 20

DDVNW DD col

colNW

V C A C

C A C, (6.36)

Which can be simplified to

00

DDVNW DD col

colNW

V A

A, (6.37)

if

72

0

10

2

1DD

DD

VVcol colcol

col

A A CA

CA. (6.38)

The condition in (6.38) is met, because the change in the detector area is relatively small,

for a voltage change from 0 to VDD. By substituting (6.37) in (6.34), one gets

01

DD

DDA V

col

col

VV

A

A

. (6.39)

Equation (6.39) together with (6.33) can be used to estimate VA as functions of Wdet and

Ldet. The terms DX and Xj can be taken as fitting parameters to get the best results. The

model is compared to the measurement results in Figure 6-9 and Figure 6-10. Extracted

values of DX and Xj (0.2 µm and 5 µm, respectively) are within their expected ranges

from the process technology.

6.1.3 Effects of temperature

The two key temperature-dependent parameters in the model for NW are

diffusion length Ln and electron injection efficiency . It has been shown that, over the

range 25–100 °C, Ln is an increasing function of temperature [36]. The injection

efficiency is analogous to the emitter injection efficiency of an NPN bipolar transistor,

which is an increasing function of temperature [35]. Therefore, both Ln and contribute

to the positive temperature dependence of NW. From electrical measurements of the test

structures employed in this work, it is not possible to separately extract the temperature

dependence of Ln and that of . Therefore, for simplicity, all of the temperature

73

dependencies are modeled inside . It is found that a linear model well represents γ(T).

This linear model was employed in Figure 6-2 and Figure 6-3.

6.1.4 Effects of injection current

So far in this chapter, NW is assumed to be independent of Iinj; however, the

measurement data of Section 5.2.3 show that NW decreases at high currents. This high-

level injection (HLI) effect is addressed by modeling the injection efficiency as a

decreasing function of the current density [42]. We know that is defined as:

, ,

, , ,

,

1

1

E n E n

E E n E p E p

E n

I I

I I I I

I

. (6.40)

In (6.40), IE,n and IE,p are the currents carried by electrons and holes, respectively,

at the emitter-base junction. To find IE,p, the diffusion equation in the emitter is solved.

The high background doping density of the emitter permits the use of the low-level

injection (LLI) assumption. Hence,

, 0

2 1BEqV

kTE p p EI qD p e . (6.41)

Dp is the hole diffusion constant, and pE0 is the equilibrium hole density in the emitter

region. To find IE,n, the minority carrier distribution in the substrate, np, is given in (6.10).

Under HLI, the boundary conditions are

_det

2

( ) 0

( 0) 1( 0)

BE

p inj

qV

i kTp

p SUB

n r L

nn r e

n r N

, (6.42)

74

and these are applied to find C1 and C2 in (6.10). In (6.42), NSUB is the substrate (base

region) doping density. The base region of QNPN2 is not uniformly doped; nevertheless,

the assumption of uniform doping in the base region significantly simplifies the analyses.

The results are later parameterized, which corrects for any error introduced by this

assumption. At high currents, the substrate majority carrier density increases to maintain

neutrality, and this gives rise to an electric field. Therefore, under HLI, IE,n has both

diffusion and drift components. Carrying out the algebra and making a few

simplifications, one obtains

2

,

det

0

1

ln

1

BEqV

kTn i

E n

injE ESUB

n n SUB inj

qD n e

Id

IX XN K

L qD N W

. (6.43)

In (6.43), XE is the depth of the N+ diffusion region of the injector, Dn is the electron

diffusion constants, and Winj is the width of the injector. Finally, is found by

substituting (6.41) and (6.43) in (6.40):

det

0

1

ln

1 2 1p B injEE

n E n n B inj

d

D N IXXK

D N L qD N W

. (6.44)

In (6.44), NE is the doping density of the N+ diffusion region of the injector. Hence, NW

can be approximately written as

75

0

1NW

inj

K

I

I

. (6.45)

Above, 0 is given in Section 6.1.1, and IK is defined as

2

0

det det0

2

lnln

E inj n KK

Ep

E n

qN W D II

d X dD K

X L

. (6.46)

From (6.46), IK is a decreasing function of ddet and may be treated as a fitting

parameter. The fit of the model to the data is demonstrated in Figure 6-11 and Figure

6-12for RF-CMOS and SmartMOS technologies.

6.2 Effects of Guard Rings on the Collection Efficiency

The NGR lowers the collection efficiency of the detector by collecting some of

the electrons in the substrate. The term *

NW denotes the collection efficiency of the

detector when NGR is present and is obviously smaller than NW. Referring to Section

5.2.4, *

NW is a function of the injection current Iinj, the guard ring length LNGR, and the

NGR distance from the injector dNGR (Figure 6-13 (a)). The collection efficiency of the

NGR when other carrier detectors are absent is denoted by NGR. The modeling approach

in Section 6.1 can be used to model NGR as a function of dNGR, LNGR, and Iinj. However, a

new model for *

NW must be developed.

6.2.1 Modeling α*

NW

The modeling approach presented in Section 6.1 assumes that the injected

electrons either recombine in the substrate or get collected by the detector. This

76

assumption is false when NGR is active, and, hence, the previous models cannot be

directly used to model *

NW. The goal of this section is to build a model for *

NW based

on the existing models for NW and NGR.

Figure 6-13 (b) and Figure 6-13 (c) show two device cross-sections, one with and

one without NGR, respectively. Let us assume that the number of electrons injected per

cm2 into the substrate of the devices shown in Figure 6-13 (b) and Figure 6-13 (c) are

different and denoted by N*

inj and Ninj, respectively. Similarly, the injected electron

densities in Figure 6-13 (b) and Figure 6-13 (c) are denoted as n*

inj and ninj, respectively.

In Figure 6-13, S1 is a hypothetical box that separates the injector and the NGR from the

substrate. In Figure 6-13 (b), where NGRs are present, n*

inj_sub and N*

inj_sub denote the

number of electrons along the edges of S1 per cm3

and per cm2, respectively. Similarly in

Figure 6-13 (c), where NGR is absent, ninj_sub and Ninj_sub denote the number of electrons

along the edges of S1 per cm3

and per cm2, respectively. The number of electrons

collected by the detectors in Figure 6-13 (b) and Figure 6-13 (c) are denoted by N*

col and

Ncol, respectively.

Obviously, N*

col and Ncol are functions of N*

inj and Ninj, respectively. We will

show that there exists a constant CI such that N*

col = Ncol when Ninj = CI∙N*

inj. For these

choices of N*

inj and Ninj,

**

* * * *

inj injcol col colNW NW I NW

injinj inj inj inj

N NN N NC

NN N N N. (6.47)

77

Equation (6.47) indicates that if CI were known, one could construct a model for *

NW

using the model presented earlier in this chapter for NW together with (6.47). An

expression for CI is obtained below.

Referring to Figure 6-13 (a), the X and Y directions are horizontal and vertical,

respectively; X = 0 is the surface of the silicon and Y = 0 is the center of the injector.

Therefore, the injector lies between –Linj/2 and Linj/2, where Linj is the length of the

injector. The number of electrons per cm3

is related to the number of electrons per cm2 by

1

* * *

_ _ _

0

2

2* *

_ _

0

2 2

PW

injNGR NGR

injNGR NGR

PW

inj injNGR NGR NGR NGR

PW

X X

inj sub inj sub inj subLS X

Y d L

Ld LX X

inj sub inj subLX L

Y d L Y d LX X

N n dr n dx

n dx n dy

(6.48)

and

1

_ _ _

0

2

2

_ _

0

2 2

PW

injNGR NGR

injNGR NGR

PW

inj injNGR NGR NGR NGR

PW

X X

inj sub inj sub inj subLS X

Y d L

Ld LX X

inj sub inj subLX L

Y d L Y d LX X

N n dr n dx

n dx n dy

, (6.49)

in Figure 6-13 (b) and Figure 6-13 (c), respectively. The first two terms in the right-hand

sides of (6.48) and (6.49) are the integrals along the right and the left (vertical) edges of

S1, and the last terms are the integrals along the bottom (horizontal) edge of S1. The

length of the left and the right edges of S1 is XPW, and the length of the bottom edge is

Linj + 2dNGR + 2LNGR. We found that the first two terms in the right-hand sides of (6.48)

78

and (6.49) can be neglected. This is a reasonable approximation because XPW << Linj +

2dNGR + 2LNGR in most designs. Therefore, (6.48) and (6.49) are simplified to

2* *

_ _

2

injNGR NGR

injNGR NGR

PW

Ld L

inj sub inj sub

LY d L

X X

N n dy , (6.50)

and

2

_ _

2

injNGR NGR

injNGR NGR

PW

Ld L

inj sub inj sub

LY d L

X X

N n dy . (6.51)

We need n*

inj_sub and ninj_sub to calculate the integrals of (6.50) and (6.51). Figure

6-14 (a) shows that the electrons near the injector are almost uniformly distributed when

NGRs are absent. Therefore, we can assume that the electron density along the bottom

surface of S1 is approximately constant when guard rings are absent, which gives

2

_ _ _ _0

2

2 2

injNGR NGR

injNGR NGR

Ld L

inj sub inj sub inj sub inj NGR NGR

Ld L

N n dy n L d L , (6.52)

where ninj_sub_0 is the electron density at X = XPW and is related to ninj by

_ _0

1inj sub injn B n . (6.53)

In (6.53), 0 < B < 1 represents the fraction of injected electrons that has recombined in

the P-well. It is a function of the P-well background doping and depth. From (6.52) and

(6.53), one obtains

79

_

1 2 2inj sub inj inj NGR NGRN n B L d L . (6.54)

For two reasons, N*

inj_sub is different from Ninj_sub in (6.52). First, the NGRs

collect some of the electrons in the P-well that would cross into the substrate otherwise.

Second, the N-well/substrate junction forces the electron density to be near zero, which

means that there should be almost no electrons beneath the NGRs. Figure 6-15 shows

n*

inj_sub along the bottom edge of S1. Note that the electron distribution near the injector is

non-uniform in the Y direction when NGRs are present. The value of n*

inj_sub is highest

right below the injector (02injL

Y ) and becomes almost zero below the NGRs. In

(6.50), the integral of n*

inj_sub is needed to calculate N*

inj_sub. Because of its complicated

shape, the exact profile is approximated by the dashed curve showed in Figure 6-15,

where n*

inj_sub is assumed constant for 0

0 Y Y and equal to zero for

0 2inj

NGR NGR

LY Y d L . The value of Y0 is chosen to ensure that the areas under

the solid and the dashed curves are equal.

By integrating the approximated electron density profile, N*

inj_sub can be found:

2* * *

_ _ _ _0 0

2

*

_ _0

2

2

injNGR NGR

injNGR NGR

PW

Ld L

inj sub inj sub inj sub

LY d L

X X

inj sub inj NGR

N n dy n Y

n L A d

, (6.55)

where

80

0 2

inj

NGR

LY

Ad

, (6.56)

and

* * * *

_ _01 1

inj sub inj NGR inj NGRn n B n B . (6.57)

In (6.57), it is assumed that the collection efficiency of the NGR is independent of the

detector, which is usually true because dNGR << ddet and NGR >> NW. Equation (6.55)

can be rewritten as

* *

_1 2

inj sub inj NGR inj NGRN n B L A d . (6.58)

From (6.54) and (6.58), one concludes that if Ninj_sub and N*

inj_sub were equal, one

would hypothesize that the total number of electrons that leave S1 is the same in both

cases, and, hence, the number of the electrons collected by the detectors in Figure 6-13

(b) and Figure 6-13 (c) would be approximately equal. This condition is met when Ninj_sub

and N*

inj_sub from (6.54) and (6.58) are equal:

* * '

1 2'

1 2 2

NGR inj NGR

inj inj inj NGR

inj NGR NGR

B L A dn n n A B

B L d L, (6.59)

where

'

'

2

1 2 2

1

inj NGR

inj NGR NGR

NGR

L A dA

B L d L

B B

. (6.60)

Therefore, one can find CI as

81

'

*'inj

I NGR

inj

NC A B

N. (6.61)

Therefore, using (6.47), it can be shown that NW and *

NW are related by

* ' 'NW I NW NGR NW

C A B . (6.62)

Analytical models for NW and NGR are constructed according to Section 6.1.

Therefore, one can use (6.62) to estimate *

NW as a function of the layout geometry.

Parameters A′ and B′ can be taken as fitting factors to get the optimum results.

Figure 6-16 and Figure 6-17 show the fit of the model to the measurement results. The

model is capable of capturing the effects of guard ring design parameters, LNGR and dNGR,

as well as Iinj.

6.3 Modeling the Latchup Trigger Current

The circuit-level models presented in Chapter 4 are used to predict Itrig for a given

layout and bias condition. They are shown in Figure 6-18, Figure 6-19, and Figure 6-20.

To model the effect of the PGR, RPGR is added to the schematics.

In Section 4.1.2, we showed that latchup in a positive I-test is triggered when

,

crit

coll p PWI I . The current collected by the P-well of the victim, Icoll,p, can be written as

, 2

, , , ,coll p inj PNP victim PGR PGRI f I d L d . (6.63)

The device cross-section of Figure 6-21 shows the substrate resistive network formed

between the injector and the grounded P+ and N

+ diffusions of the victim. Function f in

(6.63) can be implemented by modeling and extracting the resistive network of Figure

82

6-21. A complete model of the substrate network can be constructed only by numerical

techniques such as those presented in [43]. However, in this work, we seek a method that

is computationally efficient. Therefore, a simplified resistive network shown in Figure

6-19 is proposed. Assuming QPNP2 does not enter into the saturation mode,

, 2

12

1 2

( , )

( , ) ( )

PGRcoll p PNP inj

PGR SUB PW

PGR PGRPNP inj

PGR PGR SUB PW

RI I

R R Rf L d

If L d f d R

. (6.64)

Above, f1 is a weakly increasing function of dvictim, and f2 is a decreasing function of

guard ring length, LPGR, and an increasing function of dPGR. In [44], a similar approach is

used for modeling the substrate for evaluating the substrate noise hazards. Analytical

models for f1(dvictim) and f2(LPGR,dPGR) are presented in [44]. The extraction of the fitting

parameters of the model requires test structures that, unfortunately, were not available. In

this work, RSUB and RPGR are extracted from measurement results of Itrig vs. LPGR (consult

Figure 6-25) as well as the measured base resistance of QNPN1 (Rb,NPN1) [45], which gives

the sum of RSUB and RPGR as

, 1

, 1

PW b NPN

PGR SUBPW b NPN

R RR R

R R. (6.65)

Simulations are done in Spectre and the results are shown in Figure 6-22 and

Figure 6-23 for the positive I-test and the undervoltage test, respectively, when guard

rings are inactive. The effect of guard rings are simulated and compared to the

measurement results as shown in Figure 6-24 and Figure 6-25. A good fit between the

model and the measurements is observed for all cases.

83

6.3.1 Parameter extraction

Parameter extraction must be done before one can simulate the circuit schematics.

The Gummel–Poon model is used for all the transistors except QNPN2. For the other

transistors, except QPNP3, saturation current (IS) and current gain are extracted from a plot

of IC vs. VBE and a Gummel plot, respectively [45]. The model parameters for QPNP3

cannot be extracted using these procedures because its terminals are inaccessible. Instead,

its parameters are extracted from substrate current measurements, such as the one in

Figure 4-6. The values of RNW1 and RPW1 are functions of well-tap spacing and are

extracted from collector resistance measurements on QPNP1 and QNPN1, respectively [45].

We cannot model QNPN2 well with standard, compact BJT models due to its highly

non-uniform geometry and boundary conditions. Instead, the models presented in

Sections 6.1 and 6.2 are used. The model presented in Section 6.2 is used when NGRs are

active. A few test structures, described below, have to be fabricated to extract the fitting

factors of the model, IK0, A, B, detG , and

nL .

Table 6-1 lists the test structures needed for extracting the fitting parameters of

the model for NW and *

NW. The test structures consist of an injector and a victim,

similar to those shown in Figure 5-1 (a). The test structures with at least three different

injector-to-victim spacings, dvictim,1, dvictim,2, and dvictim,3, must be used to extract the fitting

factors. We recommend that dvictim,1 be taken as the minimum spacing between the

injector and victim allowed in the technology, and that dvictim,2 and dvictim,3 be a typical,

relatively large injector-to-victim spacing, respectively. We recommend to take dNGR,1

and LNGR,1 as the minimum allowed in the technology, and to take dNGR,2 and LNGR,2 as a

typical guard ring spacing and length, respectively. By measuring the collection

84

efficiency of structures T1, T2, and T3, and finding the best fit-to-measurement results,

one can extract detG and

nL . Structures T1 and T4 are needed to extract parameters A and

B in order to construct a model for *

NW. Measurement of NW vs. Iinj on structures T1,

T2, and T3 can be used to extract IK0.

As presented in Section 5.2.1, detG

is a function of detector width and length, Wdet

and Ldet. We found that models for the geometry factors are best implemented using

lookup tables, where detG is recorded for different combinations of Wdet and Ldet. Data of

Figure 5-6 and Figure 5-7 indicate that a line could result in a good fit for Ldet > 20 µm

and Wdet > 5 µm. Therefore, test structures with only two different Ldet and two different

Wdet are enough for constructing a model for detG . These structures are labeled as T5 and

T6 in Table 6-1. Additional test structures may be needed for modeling small detector

geometries.

6.4 Figures

Figure 6-1: Current density in a test structure was simulated using DESSIS. The injector

diode is forward-biased, and the detector N-well is reverse-biased.

Injector Detector

x

y

85

Figure 6-2: NW vs. ddet and temperature. RF-CMOS technology. Markers are

measurement data, and solid lines are the model. Model parameter Ln = 55 m.

Figure 6-3: NW vs. ddet and temperature. SmartMOS technology. Markers are

measurement data, and solid lines the model. Model parameter Ln = 25 m. For these

multi-finger injectors, ddet is measured from the injector finger closest to the detector.

0 20 40 60 80 1000.015

0.02

0.025

0.03

0.035

0.04

0.045

0.05

0.055

0.06

ddet

(m)

N

W

T=25 C

T=75 C

T=100 C

0 5 10 150.12

0.14

0.16

0.18

0.20

0.22

0.12

0.14

0.16

0.18

ddet

(m)

N

W

T=25 C

T=75 C

T=100 C

86

Figure 6-4: Current flow lines in the substrate. The injector is a point source ninj at the left

side of the figures. At the right side, the detector is a sphere in (a) and a point sink nim in

(b). nim is chosen in a way to recreate the current flow lines of (a). The dashed lines in (b)

represent the virtual detector. The current collected by the detector in (a) and the virtual

detector in (b) are the same when nim is chosen according to (6.21).

(a)

(b)

87

Figure 6-5: NW as a function of ddet. Markers show the measurement data, the solid line

the spherical model, and the dashed line the cylindrical model. 90-nm CMOS technology.

Room temperature.

Figure 6-6: NW as a function of ddet. Markers show the measurement results, and the line

shows the model. 90-nm CMOS technology. Room temperature.

0 200 400 600 800 1000 120010

-8

10-6

10-4

10-2

100

102

ddet

(m)

N

W

Measurement

Cylindrical Model

Spherical Model

0 200 400 600 800 1000 120010

-10

10-8

10-6

10-4

10-2

100

ddet

(m)

N

W

Measurement

Exponential Model

88

Figure 6-7: αNW as a function of detector voltage Vdet and ddet. Markers show the

measurement data, and solid lines show the model. RF-CMOS technology. Room

temperature.

Figure 6-8: αNW as a function of the detector area. 90-nm CMOS technology. Room

temperature.

0 0.5 1 1.5 20.015

0.02

0.025

0.03

0.035

0.04

0.045

0.05

Vdet

(V)

N

W

ddet

= 13 m

ddet

= 30 m

ddet

= 50 m

0 500 1000 1500 2000

0.08

0.09

0.1

0.11

0.12

0.13

0.14

0.15

0.16

N

W

Acol

(m2)

89

Figure 6-9: VA as a function of Wdet. Markers show the measurement results, and the

solid curve shows the model. 90-nm CMOS technology. Room temperature.

Figure 6-10: VA as a function of Ldet. Markers show the measurement results, and the

solid curve shows the model. 90-nm CMOS technology. Room temperature.

0 10 20 30 40 5010

15

20

25

30

35

40

Wdet

(m)

|VA|

(V)

0 20 40 60 80 10010

15

20

25

30

35

Ldet

(m)

|VA|

(V)

90

Figure 6-11: NW vs. Iinj. Markers show the measurement data, and solid lines show the

model. RF-CMOS technology. Room temperature. The injector is a single-finger P-well

diode.

Figure 6-12: NW vs. Iinj. Markers show the measurement data, and solid lines show the

model. SmartMOS technology. Room temperature. The injector is a 25-finger P-well

diode.

10-2

10-1

0.005

0.01

0.015

0.02

0.025

0.03

0.035

0.04

0.045

0.05

Iinj

(A)

N

W

ddet

=13 m

ddet

=30 m

ddet

=50 m

ddet

=80 m

10-3

10-2

10-1

0

0.05

0.1

0.15

0.2

0.25

Iinj

(A)

N

W

ddet

=1.51 m

ddet

=3.01 m

ddet

=15.1 m

91

Detector

Substrate

NW

P+ P+N+

PW

I/O

VSSIO

VDD

Substrate Current Injector

NW NW

ddetLNGR

NGR NGR

N+ N+

dNGR

N+

VGRVGR

S1S1 XPW

Linj

Detector

Substrate

NW

P+ P+N+

I/O

VDD

NW NW

N+ N+ N+

VGRVGR

S1S1

VSSVSS

n*inj

n*inj_sub n

*col

Detector

Substrate

NW

P+ P+N+

I/O

VDD

N+S1S1

VSSVSS

ninj

ninj_sub ncol

Figure 6-13: Device cross-section of an injector near a detector. In (a) and (b) NGRs

are present and in (c) NGRs are absent. n*

inj and ninj are the injected electron density

in (b) and (c), respectively. n*

col and ncol are the collected electron density by the

detectors of (b) and (c) , respectively. S1 is a hypothetical box that encloses the

injector and NGRs.

(c)

(b)

(a)

Y

X

92

Figure 6-14: Contours of electron density near the injector when (a) NGRs are absent and

(b) NGRs are present. Injector is a P-well diode with five fingers. Note that there is only

one contour line in (a), while there are several in (b), which means that the electron

distribution near the injector is less uniform when NGRs are present ( (b) ). This is

caused by the boundary condition at the depletion regions of the NGR/substrate and the

NGR/P-well junctions. The detector is at the far right side of the injector (not shown in

the diagrams).

Injector

(a)

Injector NGR NGR

(b)

Y

X

93

Figure 6-15: n*

inj_sub along the bottom (horizontal) edge of S1, underneath the injector and

the NGR (at X = XPW). The solid curve is extracted from the device simulation results of

Figure 6-14(b), and the dashed line is an approximated curve for estimating the area

under the solid curve. Y0 is chosen to ensure that the areas under the solid and the dashed

curves are equal.

Figure 6-16: *

NW as a function of Iinj. NGRs are biased at VDD. Markers show the

measurement results, and the solid lines show the model. 130-nm CMOS technology.

Room temperature.

0 0.02 0.04 0.06 0.080

0.005

0.01

0.015

0.02

Iinj

(A)

* N

W

LNGR

= 1 m

LNGR

= 2 m

LNGR

= 4 m

94

Figure 6-17: α*

NW as a function of Iinj. NGRs are biased at VDD. Markers show the

measurement results, and the solid lines show the model. 130-nm CMOS technology.

Room temperature.

RPW1

VDD VDD

VSSVSSVSSO

Iinj

RSUB

RNW1

Rdiode

QNPN2

QPNP1

QNPN1

I/O

Icoll,n

Icoll,p

Figure 6-18: Circuit-level model of a substrate current injector (P-well diode) next to a

victim (PNPN), for a negative I-test.

0 0.02 0.04 0.06 0.080

0.005

0.01

0.015

0.02

Iinj

(A)

* N

W

dNGR

= 1 m

dNGR

= 2 m

dNGR

= 4 m

95

RPW1

VDD VDD

VSSVSS

VDDIO

RNW1

QNPN2

QPNP1

I/O

QPNP2

Iinj

RSUB

QPNP3

QNPN1

Icoll,n

Icoll,p

VSS

RPGR

Figure 6-19: Circuit-level model of a substrate current injector (N-well diode) next to a

victim for a positive I-test.

RPW1

VDD VDD

VSSVSSIinj

RSUB

RNW1

QNPN2

QPNP1

QNPN1

I/O

QPNP2

INW

IPW

VDDIO+-

QPNP3

Icoll,n

Icoll,p

VSS

RPGR

Figure 6-20: Circuit-level model of a substrate current injector (N-well diode) next to a

victim for an undervoltage test on VDDIO.

96

Substrate

P+ P+ N+ P+

NW

VSS VSS

Substrate Current Injector

PGRPGR

N+P+N+

PW1PW

VSSI/OVDDIO VDDIO VSS

Figure 6-21: Substrate resistive network formed between the injector and P+ and N

+

diffusions of the victim.

Figure 6-22: Itrig vs. ddet for a positive I-test with an N-well injector (see Figure 4-4).

Markers are measurement data, and solid lines are the model. The injector is a 25-finger

P-well diode. Victim orientation is 180º. SmartMOS technology. Room temperature.

0 5 10 150

5

10

15

20

25

ddet

(m)

I trig

(m

A)

RNW_ext

=10 k RPW_ext

=200

RNW_ext

=10 k RPW_ext

=0

RNW_ext

=0 RPW_ext

=0

97

Figure 6-23: Itrig vs. ddet for an undervoltage test. An external resistor (RNW_ext = 10 kΩ) is

connected to the N-well contact of the PNPN to increase RNW. Victim orientation is 180º.

SmartMOS technology. Room temperature.

Figure 6-24: Itrig of a negative I-test as a function of the NGR length. Markers are

measurement data, and solid lines are the model. The leftmost data point belongs to an

unbiased NGR. Victim orientation is 0º. 130-nm technology. Temperature is 100 ºC.

0 5 10 1518

20

22

24

26

28

30

32

ddet

(m)

I trig

(m

A)

Measurement

Model

0 1 2 3 410

20

30

40

50

60

70

80

90

100

NGR length (m)

I trig

(m

A)

Measurement

Simulation

98

Figure 6-25: Itrig of a positive I-test as a function of the PGR length. Markers are

measurement data, and solid lines are the model. The leftmost data point belongs to an

unbiased PGR. Victim orientation is 0º. 130-nm technology. Room temperature.

6.5 Table

Table 6-1: The necessary test structures for extracting the fitting parameters for modeling

Itrig of a negative I-test. Device cross-sections of the test structures are shown in

Figure 5-1 (a).

Test

Structure dvictim dNGR LNGR Ldet Wdet

T1 dvictim,1 dNGR,1 LNGR,1 Ldet,1 Wdet,1

T2 dvictim,2 dNGR,1 LNGR,1 Ldet,1 Wdet,1

T3 dvictim,3 dNGR,1 LNGR,1 Ldet,1 Wdet,1

T4 dvictim,1 dNGR,2 LNGR,2 Ldet,1 Wdet,1

T5 dvictim,1 dNGR,1 LNGR,1 Ldet,2 Wdet,1

T6 dvictim,1 dNGR,1 LNGR,1 Ldet,1 Wdet,2

0 1 2 3 40

100

200

300

400

500

600

700

800

PGR length (m)

I trig

(m

A)

Measurement

Simulation

99

CHAPTER 7

TRANSIENT LATCHUP TESTING

7.1 Experimental Setup

Figure 7-1 and Figure 7-2 illustrate the experimental setup and the test structures

used to study TLU in this work. A high-power pulse generator, with output impedance of

50 Ω, is connected to the signal pad of the test structure, labeled I/O, via a rise-time filter

(RTF) and a 50-Ω resistive matching network. The RTF sets the rise-time of the pulse, tr,

to the desired value, which is 7 ns, unless otherwise noted. The pulse-width, TPW, is

variable. The use of the matching network results in cleaner pulse waveforms by

eliminating reflections [46]. The current injected into the signal pin, Iinj, is calculated by

measuring the voltage drop across RS of the matching network (refer to Figure 7-1). The

current provided by the power supply connected to the PNPN, or victim, is denoted by

IDD. Latchup is said to have been triggered if IDD exceeds 2 mA after the trigger source

has been removed.

The length of the ground connection between the power supply and the pulse

generator is important. Because of the fast rise-time of the pulse, one has to ensure that

the voltage drops across the parasitic inductances are not significant enough to alter the

measurement results. Litz cables, which have very small inductance, are used everywhere

a ground jumper is needed, for example, to connect the grounds of the pulse generator

100

and the dc supply. It is best to connect the N+ and P

+ diffusions inside the P-well of the

victims on silicon. This helps to minimize the inductance between the diffusions.

In the setup for the positive I-test TLU, the current injected into the I/O pin has its

return path. The inductance of the cable that connects the power supply to the device

under test degrades the quality of the injection waveform, as shown in Figure 7-3. In a

real chip, the on-chip decoupling capacitors connected to VDDIO provide an alternative

current path for the injection current, which bypasses the dc power supply. The test

structures that have on-chip capacitors are highly recommended if measurements with a

pulse-width of less than 50 ns are done. Unfortunately, such test structures were not

available in time for this work. Therefore, results with TPW less than 50 ns are not

reported.

It is important to note that during a negative [positive] I-test, the PN junction

injects minority [majority] carriers into the substrate. It is normal practice to surround a

minority carrier injector with an N-well guard ring (NGR), to prevent the electrons from

reaching the victims. Similarly, majority carrier injectors are surrounded by P-type guard

ring (PGR), which is comprised of a P+ diffusion inside a P-well. The guard ring efficacy

may be assessed by measuring Itrig both with and without the guard ring activated. An

inactive guard ring is left floating; in this work, an active NGR is connected to VDD, and

an active PGR is connected to VSS.

101

7.2 Results and Discussions

7.2.1 Pulse-width dependence

The pulse-width dependence of Itrig is investigated by changing the TPW of the

trigger source. The measurement results are shown in Figure 7-4 and Figure 7-5. The

results shown in Figure 7-4 confirm previous observations [3], [4]: negative Itrig is a

decreasing function of TPW. These data also show that for a fixed spacing between

substrate current injector and victim (dvictim), negative Itrig is virtually identical for 90- and

130-nm CMOS technologies. The data of Figure 7-5 reveal that positive Itrig is also a

function of pulse-width; a comparison of Figure 7-4 and Figure 7-5 indicates that Itrig

becomes independent of TPW on a significantly shorter time scale under positive test

conditions than under negative test conditions. The different time dependencies observed

under positive and negative test conditions suggest that these time dependencies are not

intrinsic to the victim. This hypothesis is confirmed by applying a pulsed overvoltage to

the VDD terminal of the victim so as to trigger internal latchup. The measurement results

of Figure 7-6 show that the latchup trigger voltage is independent of TPW on a time scale

ranging from less than 100 ns up to 100 µs.

The pulse-width dependence of negative Itrig is attributed to the non–quasi-static

behavior of the parasitic NPN transistor Q1, formed by the N+ region of the injector, the

P-substrate, and NW1 (refer to Figure 7-1). This is confirmed by an experiment. The

potential at the emitter of QNPN2 is pulled below zero, resulting in a non-zero emitter

current. The steady-state value of IE is just a little bit less than the value of Itrig obtained

from the static I-test. The measured rise-time for IE is 7 ns. The collector current IC,NPN1(t)

is monitored. As shown in Figure 7-7, IC,NPN2 approaches steady state far more slowly

102

than does IE. We know from Section 4.1.1 that latchup is triggered when IC,NPN2 is large

enough to forward-bias the base-emitter junction of the victim, i.e., when

, 2

crit

C NPN NWI I . (7.1)

In (7.1), crit

NWI is the minimum amount of current that has to be collected by NW1 to

trigger latchup. Based on Figure 7-7, if the current injected at the I/O pad is just slightly

higher than the static Itrig, it will take about 10 µs for IC,NPN2 to reach crit

NWI . Therefore, Itrig

should be a decreasing function of TPW for TPW ≤ 10 µs, which is consistent with the data

of Figure 7-4.

Slowly, IC,NPN2 increases as a result of the large transit time for minority carriers

in the substrate. The transit time is affected by recombination in the base region of QNPN2.

One may show this mathematically by solving the diffusion equation in the base region of

QNPN2 to obtain an analytical expression for IC,NPN2(t). A closed-form solution cannot be

obtained if one attempts to model the non-uniform, three-dimensional geometry of QNPN2.

Here, we formulate and solve the diffusion equation for a simplified NPN transistor that

has uniform geometry in two dimensions. This transistor is shown in Figure 7-8. The base

length in the x-direction is dbase. Under low-level injection conditions, the continuity

equation in the base is written as

1p pn

n

n nJ

t q x. (7.2)

In (7.2), Jn and n are the current density and the carrier lifetime, respectively, of

electrons in the substrate (base of QNPN2). Neglecting any drift component, the electron

current in the base region may be written as

103

p

n n

nJ qD

x, (7.3)

where Dn is the diffusion constant for electrons in the substrate. Substituting this

expression for Jn into (7.2), one obtains the diffusion equation,

2

2

p p p

nn

n n nD

t x. (7.4)

The partial differential equation (7.4) is solved by the Laplace transform method.

Taking the Laplace transform of (7.4) and solving for Np(s,x), one gets

1 1

1 2( , )

n n

n n

s s

x xD D

pN s x C e C e (7.5)

and

1 1

2 1

( , )( , )

1

n n

n n

p

n n

s s

x xD Dn

nn

N s xJ s x qD

x

s

qD C e C eD

. (7.6)

One may set C2 to zero, as long as the solution will not be used to find the current

in devices with base n nd D , the diffusion length for electrons in the substrate. C1 is

found by considering the boundary condition at the base edge x = 0,

( ,0) ( )n EJ t J u t , (7.7)

where u(t) is the unit step function and JE is the emitter current density. A unit step

function is used in (7.7) because the source driving the emitter has a very fast rise-time,

104

justifying the step function approximation, which greatly simplifies the algebra. Equation

(7.7) can be rewritten in the Laplace domain,

( ,0) En

JJ s

s. (7.8)

Equation (7.8) is substituted in (7.6), yielding

1

1

1

E

nn

n

JC

ss

qD xD

. (7.9)

The final expression for Jn(s) thus becomes

1

( , )n

n

s

xDE

n

JJ s x e

s. (7.10)

The collector current density, JC(t), is calculated by setting x = dbase in (7.10) and then

taking the inverse Laplace transform:

2

4

1.50

( )2

base

n n

dtt D t

baseC E

n

d e eJ t J dt

tD. (7.11)

Finally, one may write an expression for the common base current gain, α:

2

4

1.50

( )2

base

n n

dtt D t

C C base

E E n

J I d e et dt

J I tD. (7.12)

From (7.1), latchup is triggered when the current collected by NW1 of the victim

is equal to crit

NWI . This N-well region is analogous to the collector region of the transistor

105

in Figure 7-8. We know that Itrig is related to crit

NWI by the NW collection efficiency, αNW.

Reasonably assuming that αNW has the same functional form as does α derived above, one

obtains the following expression for the pulse-width-dependent Itrig:

2

4

1.50

base

PW n n

crit

NWtrig dt

T D t

II

e eC dt

t

. (7.13)

In (7.13), the constant C is a function of the emitter and collector areas, and other

material and geometric constants. Equation (7.13) is plotted in Figure 7-9 with Dn = 30

cm2s

-1 and n = 3 µs, reasonable values for 90- and 130-nm technologies. The model

predicts that Itrig should be a decreasing function of TPW for TPW ≤ 10 µs, which is

consistent with the measurement data. Generally, in a technology with a moderate or high

resistivity substrate, n will be large and a negative Itrig will be a strong function of TPW.

The pulse-width dependence of a positive Itrig (see Figure 7-5) may be understood

by considering current conduction through QPNP2 (refer to Figure 7-2 (c)). Figure 7-10

shows that IC,PNP2 saturates after 200 ns, which is consistent with the behavior of Itrig in

Figure 7-5. The value of IC,PNP2 reaches steady state much faster than does IC,NPN1 because

of the short base-width of Q2. Therefore, the pulse-width dependence of a negative Itrig is

more pronounced than that of a positive Itrig.

7.2.2 Effect of trigger source rise-time

During transient test conditions, displacement current will augment the carrier

injection into the substrate. Recall that the PN junction current injectors have an

associated capacitance. Displacement current is a majority carrier current. Referring to

106

Figure 7-4, let Idisp denote the amount of displacement current injected into the I/O when

the pad voltage is raised [lowered] from VDDIO to Vinj [0 to –Vinj] with a rise-time [fall-

time] of tedge. Because Idisp is a decreasing function of tedge, fewer carriers are injected into

the device as tedge increases. Therefore, one might expect Itrig to be an increasing function

of tedge. However, both positive and negative Itrig are insensitive to tedge (Figure 7-11 and

Figure 7-12). These results are explained below.

During a negative I-test, latchup is triggered by electrons, whereas the

displacement current in the substrate is a hole current. In fact, based on the analysis in

Section 4.1.1, during a negative I-test, substrate hole current has the wrong polarity to

trigger latchup. Thus, negative Itrig is insensitive to tedge, as was shown in Figure 7-11.

Figure 7-13 shows parasitic PNP QPNP2, which controls substrate current injection

during a positive I-test. The substrate current is equal to the collector current of QPNP2,

IC,PNP2. The displacement current component of IC, PNP2 is denoted as IC, PNP2,disp. By

solving KCL at the base of Q2, we get

2

2

BE r NW BCdisp inj

r r NW BC BE

C t R CI V

t t R C C. (7.14)

By solving KCL at the emitter of Q2,

, 2,

NW BC BEC PNP disp inj

r r NW BC BE

R C CI V

t t R C C. (7.15)

The resistor RNW2 is a few ohms and CBC is not more than 1 pF. Since the product

of RNW2 and CBC is much less than tedge,

107

, 2, 2

2

1C PNP disp NW BC

disp r NW BC

I R C

I t R C, (7.16)

which means that only a small fraction of the displacement current at the I/O pin is

injected into the substrate. This is why positive Itrig is insensitive to tedge.

7.2.3 Orientation of the victim

In previous work, it was claimed that a 0° victim orientation (Figure 7-2 (a))

provides the lowest value of negative Itrig [3], [4]. Figure 7-14 and Figure 7-15 indicate

that this is generally not a correct assertion. It is true only under static test conditions in

the absence of guard rings. In most cases, the 180° oriented victim (Figure 7-2 (b)) has

the lower trigger current; this can be attributed to the smaller base-width of QNPN2, dbase.

The device simulation results of Figure 7-16 may be used to further understand

the effects of orientation. The value of Itrig depends both on the fraction of current

injected at the I/O pad that gets collected by NW1 of the victim (i.e., αNW) and on the

direction of current flow within NW1. The current must be directed such that it lowers the

N-well potential in the vicinity of the P+ diffusion, thus forward-biasing the PN junction,

a necessary step to trigger latchup. When NGRs are used (Figure 7-16 (a)), current flows

vertically through NW1, regardless of orientation, and the 180o oriented victim always

has lower Itrig due to the smaller dbase and consequently larger αNW. Figure 7-16 (b) and

Figure 7-16 (c) illustrate current flow in structures without guard rings. For the 180°

oriented victim (Figure 7-16 (b)), the portion of the current that flows laterally between

the injector and NW1 does not assist in lowering the N-well potential in the vicinity of the

P+ diffusion (see Figure 7-16 (d)). For the 0° oriented victim (Figure 7-16 (c)), all of the

current in NW1 helps to lower the potential near the P+ diffusion (see Figure 7-16 (e)).

108

Thus, for the case of no NGRs and long TPW, Itrig of the 0° oriented victim is lower than

that of the 180° oriented victim. However, as the stress pulse-width is made small, (7.13)

indicates that the number of carriers collected by NW1 of the 0o oriented victim (long

dbase) becomes a decreasing fraction of the number collected by NW1 of the 180o oriented

victim (shorter dbase). Therefore, for short stress durations, the 180o oriented victim has

the lowest Itrig, as shown in Figure 7-14.

Figure 7-17 examines the effect of orientation on positive Itrig. For the positive I-

test, the 180o victim orientation (Figure 7-2 (d)) provides the lower Itrig, regardless of

TPW; only the active guard ring case is examined. In Section 4.1.2, it is shown that in a

positive I-test,

, ,

,1

1 BE on P

trigPW PW

VI

R, (7.17)

where αPW is the common-base current gain of Q2, RPW,2 is the P-well resistance, and

VBE,on represents the on-state base-emitter voltage drop of Q2. Equation (7.17) seems to

suggest that Itrig of a positive I-test will be independent of both spacing (dvictim) and

orientation; the first of these predictions is consistent with measurement data (refer to

Section 5.3). The orientation effect seen here (Figure 7-17) is an artifact of the test

structure design. Since the test structures contain guard rings, (7.17) is modified to

account for their presence:

, ,

,1

1 1 BE on P

trigPW PGR PW

VI

f R, (7.18)

109

where fPGR is the fraction of injected carriers that is collected by the PGRs. Note that Itrig

is a decreasing function of RPW,1. In the test structures with a 0o oriented victim, the PGRs

are placed in the same well as is the victim (PW1). In these test structures, the PGRs not

only increase Itrig by collecting some of the excess holes from the substrate, they also

increase Itrig by decreasing RPW,1.

7.2.4 Guard ring efficiency under TLU testing

The N-well [P-well] guard rings increase negative [positive] Itrig, thus improving

latchup resilience; however, Figure 7-18 shows that the relative benefit of NGRs

decreases for short stress durations. In the earlier dataplots, e.g., Figure 7-4, it was shown

that Itrig is higher for short TPW; we have shown in Section 5.2.4 that NGR efficiency

drops under high-level injection conditions. Taken together, these two observations

explain why NGRs raise Itrig by a smaller percent as TPW decreases. Data of Figure 7-18

indicate that the benefit of PGRs is insensitive to TPW.

7.2.5 Triple well technology

Triple well technology can be used to reduce the latchup hazard due to substrate

hole injection, which occurs during a positive I-test. In the 130-nm technology, placing

the victim inside a deep N-well was found to increase Itrig by almost a factor of two (280

mA vs. 590 mA at 150 °C). However, a comparison of the data in Figure 7-4 and Figure

7-19 shows that placing the victim inside a deep N-well enhances its susceptibility to

negative TLU. A similar observation was made about static latchup [38]. Triple well

technology raises the latchup threat because the deep N-well provides an additional

collection area for electrons.

110

7.2.6 Negative I-test vs. positive I-test

Previously, it had been reported that the negative I-test provides the lowest Itrig;

that is, it is the worst-case test condition [4]. However, the data of Figure 7-20 and Figure

7-21 show that this is too general a claim. These figures compare the values of Itrig

obtained from positive and negative I-tests, both when the guard rings are inactive

(Figure 7-20) and when they are active (Figure 7-21). If TPW is large, as is the case for

static latchup testing, the negative I-test does yield the smallest Itrig. However, for stress

durations less than about 500 ns, the positive I-test yields a lower value of Itrig.

7.3 Modeling and Simulations

We know from Section 4.1.1 that Itrig of a negative I-test is related to αNW by the

following equation:

crit

NWtrig

NW

II . (7.19)

In Chapter 6, a model for αNW is presented as functions of layout geometry, temperature,

and bias conditions. Data of Figure 7-22 indicate that αNW is frequency dependent; this

dependence is important in modeling the transient effects. We can express the current

gains in the frequency domain by

3 , 2

( )

1

dc

NWNW

dB NPN

ff

jf

, (7.20)

111

where dc

NW and f3dB,NPN2 are the common-base current gain at low frequencies (dc) and

the 3-dB bandwidth of QNPN2, respectively. One can take the inverse Fourier transform of

(7.20) and insert it into (7.19) to get

3 , 22

1 dB NPN PW

crit

NWtrig f Tdc

NW

II

e. (7.21)

The model presented in Chapter 6 for the collection efficiency is used for dc

NW in (7.21).

The value of f3dB,NPN2 can be extracted from dataplots such as in Figure 7-22. The data

from this figure suggest that f3dB,NPN2 is well below 300 kHz, the minimum frequency

limit of the network analyzer used in this work. To show that (7.21) is capable of

modeling Itrig of a negative I-test, f3dB,NPN2 is treated as a fitting parameter. Results are

shown in Figure 7-23. The model fits well with the measurement results. The extracted

f3dB,NPN2 is 20 kHz.

The value of Itrig of a positive I-test can be similarly modeled using the presented

single-pole model. The terms dc

NW, crit

NWI , and f3dB,NPN2 in (7.21) are replaced with dc

PW,

crit

PWI , and f3dB,PNP2, respectively.

112

7.4 Figures

Substrate

P+ P+N+

I/OVSSIO

VDD

Substrate current injector

- +

Pulse

Generator

ScopeMatching

Network

Rise Time

Filter

IDD

Victim

RsRp Rp

Matching Network

Ls

Rise Time Filter

Cp Cp

Iinj

NW2

N+P+N+P+PW

Figure 7-1: TLU experimental setup. The rise-time filter adjusts the rise-time of the pulse

that reaches the device under test. Iinj is calculated from the measured voltage drop across

the matching network. IDD is the current through the dc power supply.

113

Substrate

P+ P+N+

PW2

I/O

Substrate Current Injector

NW NW

dbase dTAP

NGR NGRN+ N+

VDDVDD

NW1

N+P+N+P+

VSS

PW1

VDD

dvictim

Victim

VSSIO VSSIO

QNPN2

Substrate

PW2

Substrate Current Injector

NW NW

dvictim=dbase

NGR NGRN+ N+

VDDVDD

NW1

N+ P+ N+ P+

PW1

VSSVDD

P+ P+N+

I/OVSSIOVSSIO

Victim

QNPN2

Substrate

P+ P+ N+ P+

NW2

VSS VSS

Substrate Current Injector

PGRPGR

NW1

N+P+N+P+

PW1

N+

PW

VDDVSS

dvictim

Victim

I/OVDDIO VDDIO

QPNP2

Substrate

P+ P+ N+ P+

NW2

VSS VSS

Substrate Current Injector

PGRPGR

PW1

N+ P+N+ P+

NW1

N+

PW

VSSVDD

dvictim

Victim

I/OVDDIO VDDIO

QPNP2

Figure 7-2: The setup and structures for performing negative, (a) and (c), and positive, (b)

and (d), I-tests. The victims in (a) and (c) are 0o oriented, which means that the P-well of

the victim (PW1) is closer to the injector than is its N-well (NW1). (b) and (d) show 180o

oriented victims, in which the relative positions of PW1 and NW1 are reversed.

(d)

(c)

(b)

(a)

114

+

-I/O

VDDP

+

N+

P+

N+

VDDIO

DUT

VSS

Lpar

Iinj

Iinj

Iinj

I inj

Figure 7-3: (a) The setup for the positive I-test showing the cable that connects the dc

supply to VDDIO with its parasitic inductance Lpar. (b) The injection current as a function

of time during a transient positive I-test.

-0.1 -0.05 0 0.05 0.1 0.15 0.2-0.2

0

0.2

0.4

0.6

0.8

1

1.2

Time (s)

I inj (N

orm

alized)

(b)

(a)

115

Figure 7-4: Negative I-test. 0° oriented victims. Itrig is a decreasing function of TPW and

dTAP. 90-nm and 130-nm CMOS technologies. NGRs are inactive.

Figure 7-5: Itrig from positive I-test. Guard rings are inactive. 0° oriented victim. 130-nm

CMOS technology.

10-1

100

101

102

0

100

200

300

400

500

600

700

TPW

(s)

I trig

(m

A)

130-nm CMOS

90-nm CMOS

10-1

100

101

102

70

80

90

100

110

120

130

140

150

TPW

(s)

I trig

(m

A)

116

Figure 7-6: Vtrig for internal latchup vs. TPW. The victim is shown in Figure 7-1. The

terminals of the substrate injector are left floating. A trigger source with pulse-width of

TPW and rise-time of 7 ns is placed in series with the dc supply, VDD. 130-nm CMOS

technology.

Figure 7-7: Collector and emitter current of QNPN2 during a negative I-test for a 0°

oriented victim. 130-nm CMOS technology.

10-1

100

101

102

7

7.5

8

8.5

9

9.5

TPW

(s)

Vtr

ig (

V)

0 5 10 15 200

0.2

0.4

0.6

0.8

1

Time (s)

Curr

ent

(Norm

alized)

IC,NPN2

IE,NPN2

117

N P NEmitter Collector

Base

x=0 x=dbase

Figure 7-8: A 1-d NPN is used to simplify the derivation of the diffusion equation.

Figure 7-9: Itrig vs. TPW as predicted by (7.13). Dn = 30 cm2s

-1 and n = 3 µs, which are

reasonable values for 90- and 130-nm technologies. Itrig becomes constant for TPW ≥ 10

µs, which is similar to the data of Figure 7-4.

10-1

100

101

102

0

0.2

0.4

0.6

0.8

1

TPW

(s)

I trig

(N

orm

alized)

118

Figure 7-10: Collector current of QPNP2 during a positive I-test for a 0° oriented victim.

130-nm CMOS technology.

Figure 7-11: Negative I-test. Itrig is insensitive to tedge. TPW = 500 ns. 0° oriented victims.

130-nm CMOS.

0.05 0.1 0.15 0.20

0.2

0.4

0.6

0.8

1

Time (s)

I C,P

NP2 (

Norm

alized)

5 10 15 20 25 30

200

250

300

350

400

450

500

tedge

(ns)

I trig

(m

A)

NGR active

NGR inactive

119

Figure 7-12: Positive I-test. Itrig is insensitive to tedge. TPW = 1 µs. 0° oriented victims. 130-

nm CMOS.

Substrate

P+

NW2

N+

I/OVDDIO

QPNP2

RNW2CBE

CBC

P+

VSS

IC,PNP2

Iinj

PW1

Idisp

Figure 7-13: Parasitic PNP QPNP2 is the substrate current injector during a positive I-test

(see Figure 7-2 (c) and (d)). RNW2 is the N-well resistance. CBE and CBC are the

base-emitter and the base-collector junction capacitances, respectively. Only the P+

diffusion of the victim is shown.

5 10 15 20 25 300

100

200

300

400

500

tedge

(ns)

I trig

(m

A)

PGR active

PGR inactive

120

Figure 7-14: Negative I-test with inactive NGRs. Only for large TPW does the 0° oriented

victim have smaller Itrig than the 180o oriented victim. 130-nm CMOS technology.

Figure 7-15: Same experiment as for Figure 7-14, except that the NGRs are active. The

180° oriented victim has the smallest Itrig, regardless of TPW.

100

101

102

20

40

60

80

100

120

140

TPW

(s)

I trig

(m

A)

0o oriented victim

180o oriented victim

10-1

100

101

102

0

100

200

300

400

500

600

TPW

(s)

I trig

(m

A)

0o oriented victim

180o oriented victim

121

Figure 7-17: Positive I-test with active PGRs. The 180° oriented victim has the lower Itrig.

130-nm CMOS technology.

10-1

100

101

102

250

300

350

400

450

500

TPW

(s)

Itr

ig (

mA)

0o oriented victim

180o oriented victim

(c)

N+ P+ N+

NW1

Substrate

1.3V1.2V

N+

P+

NW1

(d)

1.3V

1.2V1.1V

P+

N+

NW1

(e)

(b)

N+ N+ P+

NW1

Substrate

(a)

N+ N+ P+

NW1

Substrate

NGR

Figure 7-16: Simulated current flow during a negative I-test for (a) a 180° oriented

victim with active NGRs, (b) a 180° oriented victim without NGR, and (c) a 0

° oriented

victim without NGRs. Figures (d) and (e) show potential contours for cases (b) and (c),

respectively. Iinj= 100 mA/µm in all simulations.

122

Figure 7-18: ΔItrig/Itrig (guard rings inactive) where ΔItrig ≡ Itrig (guard ring active) - Itrig

(guard ring inactive). 0° oriented victims. Circular data markers are for a negative I-test;

square ones are for a positive I-test. 130-nm CMOS technology.

Figure 7-19: Negative I-test on 0° oriented victims built using triple well technology,

which lowers the latchup trigger current. 130-nm CMOS technology.

10-1

100

101

102

100

150

200

250

300

350

400

450

500

550

TPW

(s)

Itr

ig/Itr

ig (

%)

PGR

NGR

10-1

100

101

102

5

10

15

20

25

30

35

TPW

(s)

Itr

ig (

mA)

dvictim

=5.5 m

dvictim

=14 m

123

Figure 7-20: Itrig from positive and negative I-tests. Guard rings are inactive. 0° oriented

victims. 130-nm CMOS technology.

Figure 7-21: Same experiment as for Figure 7-20, except the guard rings are active.

10-1

100

101

102

0

100

200

300

400

500

600

700

800

TPW

(s)

I trig

(m

A)

Negative I-test

Positive I-test

10-1

100

101

102

100

200

300

400

500

600

TPW

(s)

Itr

ig (

mA

)

Negative I-test

Positive I-test

124

Figure 7-22: Common-base current gain of QNPN2 vs. frequency. A network analyzer is

used to perform the measurement. 130-nm CMOS technology.

Figure 7-23: Model vs. measurement for the negative I-test. Guard rings are inactive.

130-nm technology. Room temperature.

106

108

-65

-60

-55

-50

-45

Frequency (Hz)

20*lo

g(

NW

)

10-1

100

101

102

103

0

200

400

600

800

1000

1200

1400

TPW

(s)

I trig

(m

A)

Measurement

Model

125

CHAPTER 8

CONCLUSIONS AND FUTURE WORK

8.1 Conclusions

A parasitic PNPN device will be triggered on, resulting in latchup, if current

larger than a critical value is injected into the substrate. The key factors of external

latchup are (i) the critical current that is needed to trigger the PNPN, (ii) the amount of

current injected into the substrate (Iinj), and (iii) the amount of current collected by the

wells (Icol). A model for the critical current can be developed along the lines of existing

models for the (internal) latchup trigger current. A semi-physical analytical model for the

collection efficiency was presented in this work. It predicts that the collection efficiency

is a function of device geometry, temperature, bias conditions, and the presence of guard

rings and other detectors. Model parameters are extracted from measurements performed

on a limited number of test structures. Subsequently, latchup hazards can be identified in

any layout.

Either minority or minority carrier injection to the substrate can trigger latchup.

Which type of carrier triggers latchup depends on the substrate current injector, the bias

conditions, and the layout. When latchup is triggered by majority carriers, Itrig is

relatively insensitive to injector-to-PNPN spacing. This highlights the key role of P-type

rings and substrate taps in preventing external latchup, since spacing does little to

126

mitigate the latchup hazard. On the other hand, when latchup is triggered by minority

carriers, Itrig is an increasing function of injector-to-PNPN spacing.

High-level injection effects greatly reduce the efficacy of NGRs for preventing

latchup; thus, guard rings should be evaluated under high-current conditions. In most

cases, the collection efficiency of an isolated detector is not very different from that in the

presence of multiple detectors.

P-well guard rings, which are required to prevent latchup triggering by positive

current injection and for substrate noise reduction, increase minority carrier collection

efficiency and the latchup hazard from negative current injection.

Negative current injection is the worst-case condition during static latchup testing,

which is generally used for product qualification. However, real world stresses, such as

cable discharges, are transient, in which case positive current injection is the worst-case

condition.

The circuit schematics presented in this work can be used to simulate the value of

Itrig for various bias conditions. A good fit is observed between the model and simulation

for the latchup tests described in the JEDEC standard.

Based on the results of this work, we recommend the following design guidelines

for minimizing the latchup hazards.

Identify the victims. Skip those that are located in the domains with supply

voltages below 1.2 V. Pay special attention to the victims that are biased at voltages

127

higher than 1.5. These victims are more likely to latchup. Be careful with victims biased

at voltages between 1.2 V and 1.5 V. Some of them may latchup.

Identify the injectors. They are usually PN junctions connected to signal pins.

Determine which of them inject electrons and which ones inject holes. Add appropriate

guard rings to the injectors. The guard ring lengths larger than 6 µm do not improve

latchup hazards. Keep the guard ring-injector spacing minimum. Expect a factor of 4-6

improvement by using NGRs and a factor of 7-9 by using PGRs. To decrease latchup

hazards from minority carriers, increase the spacing between the injectors and the

victims, or use NGRs. When latchup is triggered by majority carriers, using PGRs is the

only option. Avoid adding PGRs to minority carrier injectors. If PGRs must be added for

noise issues, place the P-well ring inside the N-well ring. NGRs can be safely connected

to VSS instead of VDD to ease the layout routing.

If the product has to pass only the static latchup tests, guarding minority carrier

injectors has priority over majority carrier injectors, because the negative injection is the

worst testing condition. On the other hand, if the product has to pass only the transient

latchup tests, majority carrier injectors must be given a higher priority.

Do the latchup testing at evaluated temperatures. A product that passes the

latchup tests at room temperature may fail at evaluated temperatures. The latchup trigger

current at 100°C is usually a factor of 2-3 smaller.

128

8.2 Future Work

8.2.1 Negative I-test

We showed in Section 5.26 that PGRs have an adverse effect on latchup triggered

by electrons, because the PGRs increase the collection efficiency of the victim. This

effect is not captured by the model presented in Chapter 6.

Lookup tables are proposed to model the effect of detector geometry in Section

6.1. Lookup tables are computationally inefficient. One can further investigate these

effects and construct a physical based model that includes the effect of detector geometry.

A computer program can be written that automatically extracts the model

parameters. This program speeds up the extraction procedure needed for developing the

model.

Figure 8-1 illustrates four victims with different orientations near an injector. We

only studied the 180° and 0° victim orientations in this work, Victims B and D,

respectively. Victim C is not studied in any of the previous publications. Among A, B,

and D, the orientation of Victim A is claimed to be the worst case in [3] and [4].

However, these structures did not have guard rings worst case victim orientation. The

injector-to-detector spacing in Victims A, B, and C are the same, but the directions of the

current flow are different. Unfortunately, test structures with orientations of Victims A or

C were not available in time to draw a conclusion. New test structures or 3-D device

simulations can be done to understand how latchup is triggered in victim orientations

other than 0° and 180°.

129

8.2.2 Positive injection

We showed that the circuit schematics in Figure 6-19 can be used to estimate the

Itrig of a layout. A sophisticated extraction method has yet to be developed for extracting

RPGR and RSUB for various layout geometries, i.e., functions f1 and f2 in Section 6.3. The

model can be based on existing work such as [44].

8.2.3 Transient latchup

The setup for the transient latchup testing can be improved to perform

measurements for TPW < 50 ns. Adding on-chip capacitors to test structures is one way to

improve the quality of the injection current waveform.

The single-pole model presented in Section 7.3 for predicting the Itrig in TLU

testing is promising; however, it has not been verified for various conditions. For

example, the 3-dB band width of QNPN2, f3dB,NPN2, is a function of injector-to-victim

spacing. Furthermore, activating guard rings may also change f3dB,NPN2. This dependence

is important and not yet incorporated in the model.

8.2.4 Latchup and substrate noise

In addition to preventing latchup triggering by positive injection, PGRs and P-taps

are commonly used for suppressing the substrate noise. However, Section 5.2.6 shows

that PGRs and P-taps increase the collection efficiency of the detector and the latchup

hazard from negative current injection. For example, we showed in Section 5.2.6 that

when NGRs are active, activating PGRs may lower Itrig by a factor of ~ 30%. Therefore, a

tradeoff exists between suppressing the substrate noise and the latchup hazards; a design

practice that improves one may degrade the other. New design techniques that could

simultaneously improve both hazards should be investigated.

130

8.3 Figure

Injector

Victim A

P+ N

+

Victim D

P+ N

+

Victim B

P+

N+

Vic

tim C

NW NWN

W

P+

N+

NW

N+

P+

Figure 8-1: Victims near an injector at different orientations. Victims B and D are 180°

and 0° oriented, respectively.

131

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