820 Park Two Drive, Sugar Land, Texas 77478 Phone: (281) 240-7233 Fax: (281) 240-7238

E-Mail: naztec@naztec.com Web: www.naztec.com

NAZTEC, INC.

Model 2070 Controller Version 1.7

Validation Suite Operation Manual

Table of Contents 1. Introduction 3

1.1. Naztec 2070 Validation Suite 3 1.2. Version 1.7 Software 3 1.3. Copyright Information 3

2. Getting Started 4

2.1. Installation 4 2.2. Starting the software 4 2.3. Running Individual Tests 5 2.4. Continuous Testing 6 2.5. Dump Terminal Mode 7

3. Interface and Navigation 9

3.1. Keyboard and Display 9 3.2. Test Suite Map 10

4. Processor Tests 12

4.1. CPU/OS Test 12 4.2. DRAM Test 13 4.3. SRAM Test 13 4.4. Flash ROM Test 15 4.5. Boot ROM Test 16 4.6. TOD Clock Test 18 4.7. Timers Test 18 4.8. Datakey Test 20 4.9. A/C Power Test 23

5. Front Panel Tests 24

5.1. Display Test 24 5.2. Keyboard Test 27 5.3. LED Test 28 5.4. Speed Test 29

Table of Contents (continued) 6. Field I/O Tests 30

6.1. I/O Status Test 30 6.2. I/O Loopback Test 31 6.3. I/O Modes Test 32 6.4. I/O Filtering Test 33 6.5. CPURESET Test 34 6.6. I/O Diagnostic 35

7. Port Tests 37

7.1. Loopback Tests 37 7.1.1 Individual Port Loopback Test 43 7.1.2 Port-Port Loopback Test 39

7.2. Changing Asynchronous Port Parameters 43 7.3. SP1/SP2 Port Tests 44

8. Other Testing using the OS-9 Shell 45

8.1 Setting the OS-9 Time of Day Clock 45 8.2 Setting the Hardware Time of Day Clock 45 8.3 Testing Daylight Savings Time 46 8.4 Testing for Installed Software 47 8.5 Testing Warmboot 48 8.6 Running FLRESTORE 48 8.7 Running OS-9 xmode 48 8.8 Error Logging 49 8.9 Buffering Mode Demonstration 50

1 Introduction 1.1 Naztec 2070 Validation Suite The Naztec 2070 Validation Suite has been designed to provide functional testing of the major functions of the 2070 unit. It provides a suite of tests to verify proper operation of both the hardware components of the unit as well as proper operation of the OS-9 operating system. The software has been designed as a set of test programs, each capable of running by itself, to test the specific function they were programmed for. A single menu function that binds all of the tests into a single module for performing tests from the 2070 Front Panel Assembly Display and using the 2070 Front Panel Assembly Keypads has also been provided. The Validation Suite can also be run in dumb terminal mode allowing capturing of data for reports during certification testing. 1.2 Version 1.7 Software Version 1.7 of the validation suite software has been developed in the C language using the Microware Hawk development system. Each program was developed as a separate component of an overall project within Hawk. 1.3 Copyright Information Copyright 2000 by Naztec, Inc. All intellectual property rights are reserved, except as described as follows, by the copyright owners under the laws of the United States of America. Permission to freely reproduce, distribute, and/or translate into other languages is granted provided that (1) this copyright notice appears in the document, and (2) the text is not edited or used out of context.

2 Getting Started 2.1 Installation The validation suite software comes preinstalled on the Naztec 2070. The validation suite main menu program resides in the /CMDS directory on the Flash ROM Drive /f0. The individual test components reside in the /naztec directory on the Flash ROM Drive /f0. The main menu program module is named “valsuite” and is executed by the OS-9 sysgo program as described in the following section. 2.2 Starting the software The 2070 automatically starts execution of the validation suite software when power is applied if the OPEXEC module is not found on the system. If OPEXEC does exist, many of the functions in the validation suite will conflict with the operation of OPEXEC. OPEXEC must first be stopped before the validation suite can be executed. Once OPEXEC has been stopped, the validation suite can be executed from the system console by entering the following command: valsuite <>>/sp6 & When the validation suite is initialized, it will display the main menu screen on the front panel display as in Figure 2.1.

2070 Validation Suite 1) Processor C) Run Continuous 2) Front Panel 3) Field I/O 4) Ports Enter Selection:

Figure 2.1 Selecting items from the main menu tells the validation suite to display sub-menus containing finer test details. For example, to run tests related to the 2070 processor card, select item 1 from the main menu. To run Field I/O Unit tests, select item 3.

2.3 Running Individual Test Programs The validation suite software has been designed so tests can be run within the framework of the validation suite menus or individually executed from the OS-9 shell. The available test program modules developed for the Validation Suite are as follows:

vs_acpwr Processor A/C Power Test (4.9) vs_buff Buffering Mode Demonstration (Shell only) (8.9) vs_clk Processor TOD Clock Test (4.6) vs_cpureset Field I/O CPURESET Test (6.5) vs_disp Front Panel Assembly Display Test (5.1) vs_dkey Processor Datakey Test (4.8) vs_dram Processor DRAM Test (4.2) vs_dspeed Front Panel Assembly Display Speed Test (5.4) vs_eprom Processor Boot ROM Test (4.5) vs_fiodiag Field I/O Diagnostic (6.6) vs_fiofilter Field I/O Module Filtering Test (6.4) vs_fioloop Field I/O Module Loopback Test (6.2) vs_fiomode Field I/O Module Modes Test (6.3) vs_fiostatus Field I/O Module Status Test (6.1) vs_flash Processor Flash ROM Test (4.4) vs_led Front Panel Assembly LED Test (5.3) vs_keys Front Panel Assembly Keypad Test (5.2) vs_spseta Port Async Settings Test (7.2) vs_sploop1 Port Individual Loopback Test (7.1.1) vs_sploop2 Port to Port Loopback Test (7.1.2) vs_sptest Port SP1/SP2 Test (7.3) vs_sram Processor SRAM Test (4.3) vs_sysinfo Processor CPU/OS Test (4.1) vs_timer Processor Timer Test (4.7)

To run a test individually, it is first necessary to insure that the module containing the test is loaded into OS-9. This can be done using the OS-9 “load” command as follows substituting the test module name from the list above in the command for <testmodule>: load –d /f0/naztec/<testmodule> Once loaded, a test module can be executed by entering it’s name at the OS-9 Shell $ prompt. To run in dumb terminal mode, a –t should be added to the command line.

For example, if you wanted to run the Field I/O Loopback test (module vs_fioloop), you would type the following sequence at the OS-9 Shell $ prompt: load –d /f0/naztec/vs_fioloop vs_fioloop In the example, the display output for the test is designed to work on the Front Panel Assembly display. Since this display behaves as if it were an ANSI terminal, it is necessary to have a console setup as an ANSI terminal (or VT100) for proper display output from most tests. Test programs can optionally be run in a “dumb terminal” mode by adding –t to the command line (see Section 2.5). Any test can be run to direct it’s output and input to the Front Panel Assembly display and keyboard by redirecting the input and output to SP6 by adding “<>/SP6” to the command. For example, to execute the Field I/O Module Loopback Test from the example above and have the output displayed on the Front Panel Assembly display and accept keys from the Front Panel Assembly keypads type: vs_fioloop <>/sp6 NOTE: The Validation Suite makes use of features specific to the 2070 Front Panel Assembly display and keypads and may therefore not produce accurate display information when run from a terminal connected to the OS-9 shell console unless run in dumb terminal mode (see Section 2.5). 2.4 Continuous Testing The Validation Suite provides the capability to run in a continuous testing loop. This is done in a two step process first selecting the tests to run in the loop and then initiating the continuous testing loop from the Front Panel Assembly Keypad. Each sub-menu contains an item C that allows selection and de-selection of the tests on the sub-menu when the continuous testing loop is initiated. To change the selected tests, press the C key on the Front Panel Assembly Keypad followed by the menu item numbers of the tests you wish to run as part of the continuous test loop. Tests are selected and de-selected each time the test number is pressed. Tests that are selected are displayed using a check mark (√). When test selections have been made on a sub-menu, pressing the C key again returns the keypad to normal menu mode. You can then move to other menus and make selections from the tests on those menus.

Figure 2.2 is an example of tests selected for continuous execution from the 2070 Processor Tests sub-menu.

2070 Processor Tests 1)√CPU/OS Test 6) TOD Clocks 2)√DRAM Test 7) Timers 3)√SRAM Test 8)√Datakey 4) Flash ROM 9) A/C Power 5) Boot ROM C) Select Continuous 0) Previous Menu Enter Selection:

Figure 2.2

In this example, the CPU/OS Test, DRAM Test, SRAM Test, and Datakey Tests are all flagged to be executed when the 2070 is placed in a Continuous Test loop. To initiate the Continuous Test loop, return to the main menu and select the C option followed by YES to begin the testing loop. Any other key aborts the request and returns to normal operation. Once continuous loop testing has been initiated, pressing the ESC key on the Front Panel Assembly keypad (ESC key twice on dumb terminal) terminates the continuous loop at the end of the current test and returns the Validation Suite to normal menu operation. NOTE: The Validation Suite software minimizes delay times during continuous loop testing. 2.5 Dumb Terminal Mode The Validation Suite software can optionally be run in a dumb terminal mode (i.e., a terminal that does not support the ANSI sequences that the Front Panel Assembly responds to). In this mode, output from the Validation Suite menu program and test modules are scrolled rather than positioned on the screen. To run the Validation Suite menu program in dumb terminal mode, type the following command at the OS-9 Shell $ prompt: valsuite –t

Individual test modules can also be executed in dumb terminal mode by appending a –t to the command line when the test is run from the OS-9 Shell $ prompt.

3 Interface and Navigation 3.1 Keyboard and Display The keyboard is organized into two keypads. One keypad provides numeric keys and the letters A-F. The other keypad provides special function keys. Both keypads are active during validation suite programs. Specific key sequences available within tests are defined as much as possible on the display, however, the complete reference to available keys is contained in this document. The display on the 2070 Front Panel Assembly is capable of displaying up to eight rows of text each containing 40 columns. The validation suite breaks up the display screen into the following general areas:

Heading

Info Line 1 Info Line 2 Info Line 3 Info Line 4 Info Line 5 Info Line 6

Status

Figure 3.1 The “Heading” area of the display screen generally provides an indicator of where the validation suite is currently executing. It contains the menu/sub-menu name or a test name when a test program has been selected for execution. The “Info Line” area of the display screen contains information relating to the current menu, sub-menu, or test being executed. In the case of a menu or sub-menu, the information provides the available options to move around between the program areas. In the case of tests, the information provides details about the test configuration. The “Status” area of the display tracks the progress through the test. Most tests begin with a status of “Initializing” and terminate with a “Pass”, “Fail”, or “Complete” message. Depending on the test, more information regarding the exit status may be presented. For example, if a test fails, a reason for the failure as part of the status message is displayed.

3.2 Test Suite Map Table 3.1 outlines where the various tests available in the validation suite are located. The bold characters in the table reflect the key sequences required at each menu/sub-menu to run the indicated test. For example, to run the keyboard test from the main menu, you would first press the “2” key to bring up the Front Panel sub-menu and then press “2” again to run the keyboard test.

Table 3.1

Test Outline Manual Section

MAIN MENU 1 PROCESSOR

1 CPU/OS TEST 2 DRAM TEST 3 SRAM TEST 4 FLASH ROM TEST 1 WRITE TEST 5 BOOT ROM TEST 6 TOD CLOCK TEST 7 TIMER TEST 8 DATAKEY TEST 9 A/C POWER TEST

2 FRONT PANEL 1 DISPLAY 2 KEYBOARD 3 LED 4 SPEED

3 FIELD I/O 1 I/O STATUS 2 I/O LOOPBACK 3 I/O MODES 4 I/O FILTERING 5 CPU RESET 6 DIAGNOSTIC

4 PORTS 1 ASYNC LOOPBACK TESTS

1 SP1 2 SP2 3 SP3 4 SP4 5 SP5 6 SP8 7 SP1-SP2 8 SP3-SP5

2.2 4 4.1 4.2 4.3 4.4 4.4 4.5 4.6 4.7 4.8 4.9 5 5.1 5.2 5.3 5.4 6 6.1 6.2 6.3 6.4 6.5 6.6 7 7.1 7.1.1 7.1.1 7.1.1 7.1.1 7.1.1 7.1.1 7.1.2 7.1.2

Test Outline Manual Section

C Port Settings 2 SYNC LOOPBACK TESTS

1 SP1S 2 SP2S 3 SP3S 4 SP5S 5 SP8S 6 SP1S-SP2S 7 SP3S-SP5S 3 SP1 PORT TEST 4 SP2 PORT TEST

OS-9 SHELL TESTS Setting the OS-9 Time of Day Clock Setting the Hardware Time of Day Clock Testing Daylight Savings Time Testing for Installed Software Testing Warmboot Running FLRESTORE Running OS-9 xmode Error Logging Buffering Mode Demonstration

7.2 7.1 7.1.1 7.1.1 7.1.1 7.1.1 7.1.1 7.1.2 7.1.2 7.3 7.3 8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9

4 Processor Tests The Processor Tests section of the validation suite is designed to test the features and functions available on the 2070 CPU card. When selected from the main menu, the submenu in Figure 4.1 is displayed.

2070 Processor Tests 1) CPU/OS Test 6) TOD Clocks 2) DRAM Test 7) Timers 3) SRAM Test 8) Datakey 4) Flash ROM 9) A/C Power 5) Boot ROM 0) Previous Menu Enter Selection:

Figure 4.1 Individual tests are then selected using the indicated keys on the keypad. To return to the main menu, select 0 (zero) from this submenu. 4.1 CPU/OS Test This test demonstrates the CPU processor type and Operating System Revision installed in the 2070 CPU. In addition, the test computes the CPU clock frequency assuming that the Linesync frequency is constant at 120 Hz. The test begins by querying OS-9 for the processor type (M$CPUTyp) detected during system initialization and for the OS-9 operating system version (M$OS9Rev). A timer is started at the CPU clock frequency and compared with the OS-9 TOD Clock. The results are displayed as in Figure 4.2.

CPU/OS Test CPU Type: 68300 OS9 Rev: OS-9/68K V3.1 CPU Speed: 24.576 Press a key to continue

Figure 4.2

The results will remain until either a key is pressed or 30 seconds have elapsed. The validation suite software then returns to the Processor Tests submenu. 4.2 DRAM Test This test demonstrates the total amount of dynamic RAM memory reported by OS-9 and the amount of dynamic RAM memory currently free. Contiguous memory blocks are repeatedly allocated from OS-9 and tested by writing and checking a test pattern until all available memory has been tested. The results are formatted in the Figure 4.3.

DRAM Test Total DRAM: 4128768 Free DRAM: 2985216 Testing 172648 bytes @ 003c4700 Press a key to continue

Figure 4.3 The results will remain until either a key is pressed or 30 seconds have elapsed. The validation suite software then returns to the Processor Tests submenu.

4.3 SRAM Test This test demonstrates the total amount of static RAM memory reported by OS-9 on the /r0 drive and the amount of static RAM memory space on /r0 that is currently free. A file is then opened on the static RAM drive and written to until the drive is reported full by OS-9. The file is closed and reopened. The contents are then read back and checked against the pattern written. The results are displayed on a screen formatted as in Figure 4.4.

SRAM Information Test Total SRAM: 894976 Free SRAM: 88832 88832 bytes written to SRAM file 88832 bytes verified from SRAM file Press a key to continue

Figure 4.4 The results are displayed until either a key is pressed or 30 seconds have elapsed. The validation suite software then returns to the Processor Tests submenu.

4.4 Flash ROM Test This test demonstrates the total amount of FLASH memory reported by OS-9 on the /f0 drive and the amount of FLASH memory space on /f0 that is currently free. The results are displayed on a screen formatted as in Figure 4.5.

FLASH Test Total FLASH: 3145728 Free FLASH: 2864896 1) File Write Test Press any other key to continue

Figure 4.5 The Naztec 2070 is equipped with a total of 4 megabytes of Flash memory. This is divided into two areas. The first area contains the boot file and is 1 megabyte in length. The remaining 3 megabytes is used in an RBF disk drive (/f0) similar to a RAM drive. The following table identifies the use of this storage as delivered in the 2070 by Naztec:

Total Flash Storage 4194304 bytes Flash Boot Sector 1048576 bytes /f0 Subdirectory Structures 10240 bytes /f0 Validation Suite Software 301312 bytes /f0 ISP Networking Option 293376 bytes /f0 Free Storage 2540800 bytes

By pressing the ‘1’ key, an additional sub-test can be performed from within the Flash ROM Test for the purpose of demonstrating that a file written to flash will not become corrupted in the case of a power failure (TEES 9.2.7.2.10). The Validation Suite opens a file called “flash.tst” on the flash drive (/f0) and writes 128 kilobytes into it. A “READY” flag indicating that the file has been written is displayed as in figure 4.6.

FLASH Test Total FLASH: 3894976 Free FLASH: 3188832 1) File Write Test READY Press any other key to continue

Figure 4.6 The Validation Suite begins a 30-second timer. If any other key is pressed on the FPA keypad or the timer expires, the file is deleted and the test exits normally. If the power is turned off and the flash test is rerun, a test for the existence of the file will be performed. If the file exists, the program reads the content of the file on the Flash drive and compares it to an expected pattern. The program displays “SHORT" if the file is not the expected length or “ERROR” if the file does not match the expected pattern. If all the tests are successful, the program displays “MATCH” as in figure 4.7. The file is then deleted from the flash drive.

FLASH Test Total FLASH: 3894976 Free FLASH: 3188832 1) File Write Test MATCH Press any other key to continue

Figure 4.7 The results of the test will remain until either a key is pressed or 30 seconds have elapsed. The validation suite software then returns to the Processor Tests submenu.

4.5 Boot ROM Test This tests computes the checksum of the EPROM (if installed) and reports the checksum to the display. The checksum can be visually compared to the checksum written on the EPROM chip. The results are display on a screen formatted as in Figure 4.8.

Boot ROM Test Boot ROM Checksum: ca47 Press a key to continue

Figure 4.8 The results of the query will remain until either a key is pressed or 30 seconds have elapsed. The validation suite software then returns to the Processor Tests submenu.

4.6 TOD Clock Test This test samples the time from the hardware real-time Clock and the current OS-9 time and displays both on a screen formatted as in Figure 4.9. It can also be used to enable calibration of the crystal oscillator in the hardware clock circuit.

TOD Clock Tests DST: Disabled Calibrate: Disabled H/W RTC: 09/26/50 12:53:50 OS9 TOD: 09/26/50 12:53:50 1) Toggle DST 3) Sync H/W RTC 2) Toggle Calibrate 4) Sync OS-9 TOD Press any other key to return...

Figure 4.9 Pressing 1 toggles the DST flag in OS-9. The Daylight Saving Time Feature can then be tested using the OS-9 setime program (see Section 8.3). Pressing 2 sets the 2070 in hardware real-time clock calibration mode. This enables the hardware RTC test point on pin 1 of the Oki 6242B-clock chip. The Validation Suite will remain in calibration mode until pressing 2 again disables it or the TOD Clock Test is exited. Pressing 3 synchronizes the hardware real-time clock from the current OS-9 clock time. Pressing 4 synchronizes the OS-9 clock time from the hardware real-time clock time. The display will remain active until any other key is pressed or until 60 seconds have elapsed (unless it is in calibration mode). The validation suite software then returns to the Processor Tests submenu. When running this test from a terminal, the total test period time can be specified by using the –p option to specify the test time in seconds. For example, to run this test for a period of 10 minutes enter the following command at the OS-9 Shell $ prompt:

vs_clk –p600

4.7 Timers Test This test demonstrates the features available for the 68360 timer interface driver. The timer to be used in the test is first selected from a display screen similar to the one in Figure 4.10.

2070 Timer Tests 1) timer1 6) timer12 2) timer2 7) timer34 3) timer3 4) timer4 C) Select Continuous 0) Previous Menu Enter Selection:

Figure 4.10 timer1, timer2, timer3 and timer4, are normal timers (16-bit). timer12 and timer34 are cascaded timers (32-bit). Once selected, a timer is configured as follows:

Type Cascade Prescaler Clk Recycle Reference Period Normal NO 249 / 16 YES 61440 10 Seconds

Cascaded YES 249 / 16 YES 368640 30 Seconds The timer driver settings displayed reflect the timer register settings in the 68360 (see 68360 Users Manual for details). The timer counter register is sampled once a second and displayed on a screen similar to that depicted in Figure 4.11.

Timer Test Timer: /timer1 TGCR CAS: 0 FRZ:0 STP:0 RST:1 GM:0 MODE PS:249 CE:0 OM:0 ORI:0 FRR:1 ICLK:2 GE:0 TRR:61440 TCR: 0 TER REF:0 CAP:0 TCN: 6024 Initializing...

Figure 4.11 The test continues for up to 60 seconds, or until a key is pressed on the Front Panel Assembly keypad. For normal timers, the Timer Counter (TCN) recycles

every 10 seconds. For cascaded timers, the Timer Counter (TCN) recycles every 30 seconds.

4.8 Datakey Test This test demonstrates the use of the Datakey. The test attempts to open the /CPUDatakey device and obtain the contents of the key. If a datakey is not inserted, the test reports that no key is inserted as in Figure 4.12.

Datakey Test Key Status: Not Inserted Data: Looking for Datakey...

Figure 4.12 The test will wait up to 60 seconds for a key to be inserted. When a key is inserted, the content of the key is verified against the Test Key pattern and the results and data are displayed as Figure 4.13.

Datakey Test Key Status: Inserted Data: 00/ff 7f be db e4 ed c6 87 ........ 08/08 8b 4e 2b 0c 2d 4e 8f ..N+.-N. 10/10 93 56 3b 14 3d 56 97 ..V;.=V. 18/18 9b 5e 3b 1c 3d 5e 9f ..^;.=^. Datakey matches test pattern.

Figure 4.13

If the results obtained from the datakey do not match the expected Test Pattern key contents, the data is displayed however the display indicates that the pattern is not matched as Figure 4.14.

Datakey Test Key Status: Inserted Data: 00/55 55 00 00 00 00 00 00 UU...... 08/00 00 00 00 00 00 00 00 ........ 10/00 00 00 00 00 00 00 00 ........ 18/00 00 00 00 00 00 00 00 ........ Datakey fails test pattern match.

Figure 4.14 The up-arrow and down-arrow keys on the keypad can be used to scroll through the data retrieved from the datakey. If any other key is pressed, the test will exit and return to the Processor Tests submenu. If no keys are pressed and the data key status does not change for 60 seconds, the test automatically returns to the Processor Test submenu.

4.9 A/C Power This test demonstrates the ability of the 2070 to detect short-out and computes the line frequency based on a 68360 timer assumed to be constant at 24.576 MHz and the OS-9 Linesync Interrupt. The test displays the screen depicted in Figure 4.15 on the Front Panel Assembly.

A/C Power Test Short Out Status: NORMAL Short Out Period: 0 Linesync Freq: 120.010 Time Remaining: 37 Seconds

Figure 4.15 If a power interruption of less than the short-out period occurs, the Short Out Status field will indicate that the unit is currently in a short out period by reporting “A/C FAIL” in the Short Out Status field. The Short Out Period counts the number of clock ticks since the short-out period began and retains the short-out period length after power is restored until the beginning of the next Short Out. The test continues for 60 seconds. If the up-arrow is pressed, an additional 60 seconds is added to the test timer. Any other key forces the test to exit. If this test is run from the OS-9 shell, it can optionally specify an execution period instead of the default 60 second period by appending a –P<time in secs> to the end of the command line.

5 Front Panel Tests The Front Panel Tests section of the validation suite is designed to test the features and functions available on the 2070 Front Panel Assembly. When selected from the main menu, the submenu in Figure 5.1 is displayed.

2070 Front Panel Tests 1) Display 2) Keyboard 3) LED 4) Speed C) Select Continuous 0) Previous Menu Enter Selection:

Figure 5.1 Individual tests are then selected using the indicated keys on the keypad. To return to the main menu, select 0 (zero) from this submenu. 5.1 Display Test The display test has been designed to demonstrate the capability of the 2070 Front Panel display to perform per the specification. It does this by exercising feature codes available using a series of four display screens. The test can be allowed to progress automatically from screen to screen every 30 seconds or can be manually advanced by pressing any key on the keypad. The first screen displayed demonstrates the following display features: • Carriage Return • Line Feed • Backspace • Position Cursor at (x,y) • Position Cursor Pn positions to right • Position Cursor Pn positions to left • Position Cursor Pn positions up • Position Cursor Pn positions down • Home cursor • Compose Special Character • Display Special Character • Turn character blink on

• Turn character blink off • Illuminate Backlight • Extinguish Backlight • Cursor Blink on • Cursor Blink off • Reverse Video on • Reverse Video off • Underline on • Underline off • All attributes off • Cursor on • Cursor off

Figure 5.2 is an example of the screen display:

Display Test NORMAL BLINK REVERSE UNDERLINE BLINK/REVERSE BLINK/UNDERLINE REVERSE/UNDERLINE REVERSE/UNDER/BLINK Naztec Press a key to continue display test...

Figure 5.2 Before this test moves to the next screen, the cursor beings cycling back and forth across the screen as the screen backlight is alternately illuminated and extinguished. After each cycle, the cursor switches from off, to on, to blinking and back to off for each subsequent cycle. The next test performed is a blank screen test. This test is first announced by displaying Figure 5.3.

Screen Blank Test in 10 seconds...

Figure 5.3 When the timer on the screen counts down to zero, the screen is cleared demonstrating the following display features: • Clear screen with spaces • Auto scroll on • Line Feed The screen remains blank for 30 seconds or until a key is pressed on the keypad.

The next test performed is to fill the screen completely. This test is first announced by displaying Figure 5.4.

Screen Fill Test in 10 seconds...

Figure 5.4 Like the screen blank test, when the timer on the screen counts down to zero, the screen is filled with solid characters demonstrating the following display features: • Compose Special Character • Display Special Character • Auto-Scroll off • Auto-Wrap on • Auto-Wrap off The screen remains filled for 30 seconds or until a key is pressed on the keypad. The next test demonstrates the following display features: • Move cursor to next tab stop • Set tab at current cursor position • Clear tab stop During this test the screen in Figure 5.5 is displayed.

Tab Test Default Tabs: 1 2 3 4 Tabs 2 and 3 Cleared: 1 2 Custom Tabs: 1 2 Press a key to continue...

Figure 5.5

The default tabs demonstrate the initial tab positions defined in the display at power-up. Tab positions 2 and 3 are then cleared and two tab positions are then displayed demonstrating the cleared tab positions. All tab positions are cleared and two custom tab positions are created and displayed demonstrating that the original tab positions were cleared and the new positions created. The Tab Test screen remains displayed until either a key is pressed on the keypad or 30 seconds have elapsed. Finally, the display test performs a “soft reset” returning the display to its default settings and returns to the Front Panel Test submenu. NOTE: The Display Test can be executed under Dumb Terminal Mode, however, the output of the test is always sent to the FPA display. 5.2 Keyboard Test The keyboard test is designed to demonstrate the features of the 2070 Front Panel keypad and also demonstrates several display functions that could be better demonstrated using keypad inputs. The following Front Panel Assembly features are demonstrated in this test: • Status Cursor Position • Set Backlight Timeout • Auto-Repeat on • Auto-Repeat off • Bell The test begins by inquiring the current status of the display thereby obtaining the current auto-repeat, backlight timeout, and AUX switch position indications. The screen in Figure 5.6 is then displayed.

Keyboard Test Key Pressed: <none> Aux Switch: N/A Auto-Repeat: OFF Backlight Timeout: 0 Sound Bell Press ESC twice to exit...

Figure 5.6

The “Key Pressed” field is updated as keys are pressed on the keypad indicating which key was pressed. Each time the ‘A’ key is pressed, the auto-repeat feature is toggled on and off. Each time the ‘B’ key is pressed, the bell is sounded. The backlight timeout can be increased by pressing the up-arrow key and decreased by pressing the down-arrow key. The backlight timer is restarted after each change in the timeout. The position of the Auxiliary Switch on the front panel is tracked in the “Aux Switch” field. This test does not time out automatically. Pressing the ‘ESC’ key twice consecutively terminates this test. NOTE: Because the keyboard test requires access to the FPA keypads and operator intervention is required to perform the test, the Keyboard Test is not available in continuous testing mode or in dumb terminal mode. 5.3 LED Test The LED test is designed to demonstrate the operation of the LED on the Front Panel Assembly. When the test is run, the screen in Figure 5.7 is displayed on the Front Panel display:

FPA LED Test LED Status: ON Press UP-Arrow to turn LED ON Press DN-Arrow to turn LED OFF Press any other key to exit

Figure 5.7 When the up-arrow key is pressed on the keypad, the LED will be illuminated and the status will be updated on the display. When the down-arrow key is pressed on the keypad, the LED will be extinguished on the front panel and the status will be updated on the display. This test exits automatically after 30 seconds or by pressing any other key on the keypad. The Validation Suite then returns to the Front Panel tests submenu.

5.4 Speed Test The Speed test demonstrates the capability of the Front Panel Assembly Display to update every 50 milliseconds. The test is first announced as in Figure 5.8.

Display Speed Test Speed Test in 10 seconds...

Figure 5.8 The test then sets up a 50 ms OS-9 cyclic alarm. Each time the alarm expires, a counter is incremented and displayed in a 4-row by 3-column grid. The total output to the Front Panel Assembly is 176 bytes (45.83 ms.) every 50 ms allowing 4.17 ms of processing time for the task. The output looks as in figure 5.9.

Display Speed Test 1024 1024 1024 1024 1024 1024 1024 1024 1024 1024 1024 1024 Press any key to continue…

Figure 5.3 The test can be aborted at any time by pressing a key on the Front Panel Assembly keypad. The test automatically completes after 1200 cycles (60 seconds) if no key is pressed. NOTE: The Display Speed Test can be executed under Dumb Terminal Mode, however, the output of the test is always sent to the FPA display.

6 Field I/O Tests The Field I/O Tests section of the validation suite is designed to test the features and functions available on the 2070-2A and 2070-2B/2070-8 Field I/O Modules. When selected from the main menu, the submenu in Figure 6.1 is displayed:

2070 Field I/O Tests 1) I/O Status 6) I/O Diagnostic 2) I/O Loopback 3) I/O Modes 4) I/O Filter 5) CPU Reset C) Select Continuous 0) Previous Menu Enter Selection:

Figure 6.1 Individual tests are then selected using the indicated keys on the keypad. To return to the main menu, select 0 (zero) from this submenu. 6.1 I/O Status Test The I/O Status Test sends a Request Unit Status to the Field I/O Module and reports the results as in the example in figure 6.2.

FIO I/O Status Test P E K R T M L W System Status: E K SCC Rx Errors: 0 SCC Tx Errors: 0 Watchdog Set: YES Value: 99 Up-Arrow/Raise Dn-Arrow/Lower Watchdog Press any other key to exit...

Figure 6.2 By pressing the up-arrow or down-arrow, the value of the Field I/O Module Watchdog increments or decrements respectively between the limits 10-100 defined in the specification and the new value is transmitted to the Field I/O Module. Pressing any other key returns to the Field I/O Submenu.

Note: There must not be a loopback connector in C12S when running this test. 6.2 I/O Loopback Test The I/O Loopback test is designed to verify proper operation of the communications circuit between the 2070 CPU and the Field I/O Module as well as test the input and output circuitry on the Field I/O Module. In order to run this test, the proper FIO Loopback plug must be installed as follows:

Module Slot Connector Loopback P/N 2070-2A A3 C11S & C1S 10501-2000 2070-8 A, B, C & D 10502-2000

When the program begins, it initializes by establishing communications with the Field I/O Module and displays a screen formatted as in Figure 6.3.

FIO I/O Loopback Test Output: 1-1 Inputs(s): 1-1 13-01 Module ID: 2070-8 FIO Initializing . . .

Figure 6.3 The program then requests the module identification from the Field I/O Module and establishes whether it is a 2070-2A or 2070-8. Any other reported type results in an error and failure of the test. If valid, the reported module identification is displayed in the “Module ID” field and the test proceeds. The program then begins sending a sequence of commands to first output a signal on a Field I/O Module output and then read back the status of all Field I/O Module inputs. The output being tested is displayed in the “Output” field. The input(s) being checked are displayed in the “Inputs(s)” field. The input pin status is checked to make sure not only that the proper input is asserted, but also that all other inputs are not asserted. If either the proper input is not asserted, or an unexpected input is found asserted, the test fails reporting the failure. In the case of test run while using a 2070-8 Field I/O Module, there are more inputs than outputs so the loopback test connector is designed to feedback several of the outputs into multiple inputs. In this case, the program displays

both inputs in the “Inputs” field and checks both inputs to be sure the output is received. When the test completes, a pass message is displayed for 30 seconds before the test exits. The test may be prematurely exited by pressing a key during the test. Note: There must not be a loopback connector in C12S when running this test. 6.3 I/O Modes Test The I/O Modes test is designed to demonstrate the capabilities of the Field I/O Module to perform complex output functions and reporting of those functions. In order to run this test, the proper FIO Loopback plug must be installed as follows:

Module Slot Connector Loopback P/N 2070-2A A3 C11S & C1S 10501-2000 2070-8 A, B, C & D 10502-2000

The program begins by initializing 2 complex outputs as follows:

-------Duration------ Output Primary Secondary Clock 1 513 Ticks 513 Ticks MC 2 32 Ticks 32 Ticks Linesync

The defined outputs are monitored on the corresponding inputs. The inputs are configured so that every transition is recorded in the transition buffer. The transition buffer is then sampled every 500 milliseconds. The results are displayed as depicted in Figure 6.4.

FIO I/O Mode Test Input= 1,State = 0,Timestamp=FF09 Input= 1,State = 1,Timestamp=FFF6 Input=127,State = 0,Timestamp=0009 Input= 1,State = 0,Timestamp=0026 Input= 1,State = 1,Timestamp=0049 Initializing . . .

Figure 6.4 The transition buffer data presented to the display contains the input point number, the current state, and the time stamp sampled when the point change was recorded in the transition buffer. Time stamp rollover events are recorded as input point number 127.

Pressing 0 during the test resets the timestamp in the Field I/O Unit. The test runs for 60 seconds or until a key is pressed. Before exiting, the complex outputs defined during initialization are reset. Note: There must not be a loopback connector in C12S when running this test. 6.4 I/O Filtering Test The I/O Filtering Test is designed to demonstrate the input filtering capabilities of the Field I/O Module. In order to run this test, the proper FIO Loopback plug must be installed as follows:

Module Slot Connector Loopback P/N 2070-2A A3 C11S & C1S 10501-2000 2070-8 A, B, C & D 10502-2000

On initialization, four complex outputs are defined as follows:

-------Duration------ Output Primary Secondary Clock 1 128 Ticks 128 Ticks MC 2 144 Ticks 144 Ticks MC 3 144 Ticks 144 Ticks MC 4 160 Ticks 160 Ticks MC

The defined outputs are then monitored on the corresponding inputs. Input filters are configured as follows:

Input Leading Trailing 1 136 Ticks 136 Ticks 2 136 Ticks 152 Ticks 3 152 Ticks 136 Ticks 4 136 Ticks 136 Ticks

Samples are taken of both the raw data and the filtered data using the appropriate poll commands to the Field I/O Module. The results are displayed as depicted in Figure 6.5.

FIO Filtered I/O Test 76543210 Raw Inputs: 00001010 Filtered Inputs: 00000100

Figure 6.5 When the test is complete, the complex output definitions are deleted in the Field I/O Module and a message indicating that the program is done is displayed in the status area of the display screen. The program finally returns to the Field I/O Test sub-menu after 30 seconds or after a key press. Note: There must not be a loopback connector in C12S when running this test. 6.5 CPURESET Test The CPURESET Test is designed to trigger the CPURESET program. The test begins by displaying the screen depicted in Figure 6.6.

CPURESET Test Press YES to perform CPURESET Any other key to exit

Figure 6.6 By pressing the YES key on the Front Panel Assembly Function Keypad, the test program starts the CPURESET function. The CPURESET signal will be pulled low for approximately 250 ms. The 2070 Front Panel Assembly is reset by this function therefore, the display screen will clear for a short period.

When the test is complete, the display screen depicted in Figure 6.7 will be displayed signifying the end of the test. Any key returns to the Field I/O Test Sub-Menu.

CPURESET Test CPURESET Completed…

Figure 6.7 6.6 I/O Diagnostic The I/O Diagnostic is designed to assist in troubleshooting the 2070-2A and 2070-8 Field I/O Modules. The diagnostic displays the current module type and status, the current output (if any), any inputs detected, and the current timestamp. When the diagnostic is run, the display screen depicted in Figure 6.8 will be displayed.

FIO I/O Diagnostic Module ID: 2070-8 FIO Module Status: EK Output: 1-1 Timestamp: 00087234 Inputs: 1-1 2-4

Figure 6.8 The Module ID is obtained automatically from the Field I/O Module by the diagnostic when it initializes. Every 100 milliseconds, the module status is retrieved and displayed as well as any inputs (up to 6) that are currently active. A single output can be configured and sent to the Field I/O Module.

The following keys are active during the diagnostic:

Up-Arrow Increases the output port number by 1 up to the number of ports available for the Field I/O Module (2070-2A (8), (2070-8 (13))

Dn-Arrow Decreases the output port number by 1. When the output reaches zero, all outputs are turned off and NONE is displayed on the FPA.

Rt-Arrow Increases the output bit number. Bit numbers range from 1-8.

Lf-Arrow Decreases the output bit number. C Clears the current status reported by the Field I/O

Module. ESC Exits diagnostic testing.

7 Port Tests The Port Tests section of the validation suite is designed to test the features and functions available on the 2070 Asynchronous and Synchronous I/O Modules. When selected from the main menu, the submenu in Figure 7.1 is displayed:

2070 Port Tests 1) Async Loopback Tests 2) Sync Loopback Tests 3) SP1 Port Test 4) SP2 Port Test 0) Previous Menu Enter Selection:

Figure 7.1 Additional sub-menus and individual tests are then selected using the indicated keys on the keypad. To return to the main menu, select 0 (zero) from this submenu. 7.1 Loopback Tests Selecting Loopback tests from the Ports sub-menu brings up an additional submenu to select the port or port pair to be tested. The Async Port selection sub-menu is as in Figure 7.2a, the Sync Port selection sub-menu is as in Figure 7.2b.

2070 Async Port Loopback Tests 1) SP1 7) SP1-SP2 2) SP2 8) SP3-SP5 3) SP3 4) SP4 A) Port Settings 5) SP5 C) Select Continuous 6) SP8 0) Previous Menu Enter Selection:

Figure 7.2a

2070 Sync Port Loopback Tests 1) SP1S 7) SP1S-SP2S 2) SP2S 8) SP3S-SP5S 3) SP3S 4) SP5S 5) SP8S C) Select Continuous 0) Previous Menu Enter Selection:

Figure 7.2b Before running ANY loopback test, the port or ports must be terminated with the correct loopback connector assembly. Loopback connector assemblies interconnect port data transmit and receive signals and when available modem control signals. The test will not execute correctly without the proper loopback connector assembly installed on the port(s) being tested. Table 7.1 summarizes the loopback connector assembly to use in order to test the available ports in the 2070 loopback tests.

Port to be Tested Board Slot Connector

Loopback P/N

SP1 2070-7A A2 C21S 10493-2000 SP1S 2070-7B A2 TBD TBD SP2 2070-7A A2 C22S 10493-2000 SP2S 2070-7B A2 TBD TBD SP3 2070-7A A1 C21S 10493-2000 SP3S 2070-2A/2B A3 C12S 10496-2000 SP4 FPA C50S 10495-2000 SP5S 2070-2A/2B A3 C12S 10496-2000 SP8 2070-1B A5 C13S 10498-2000 SP8S 2070-1B A5 C13S 10498-2000 SP1-SP2 2070-7A A2 C21S & C22S 10494-2000 SP3-SP5 2070-2A/2B A3 C12S 10494-2000 SP1S-SP2S 2070-7B A2 TBD TBD SP3S-SP5S 2070-2A/2B A3 C12S 10497-2000

Table 7.1

7.1.1 Individual Port Loopback Test Selections 1-9, A and B from the Loopback Test sub-menu are all individual port loopback tests. Before running any of these tests, be sure to disconnect any device already connected to the port being tested and connect the proper loopback connector assembly from Table 7.1. When the test is initiated, a screen similarly formatted to Figure 7.3 is displayed on the Front Panel Assemble display. The screen contents may differ only in that ports that do not have RTS/CTS/DCD modem control signals exclude the signal status from those signals on the display.

Port Loopback Test Port: /sp1 RTS:OFF CTS:OFF DCD:OFF FCM: 0 Pass: Port Loopback Test Complete /sp1

Figure 7.3 This test begins by first opening a path to the port under test and setting it to the preset flow control mode (see 7.2). If any other program is currently using the port, the test fails. This is to insure no conflicts exist for the hardware resource on the 2070. If the port has modem control signals available, the RTS line is then turned off. The status of the CTS and DCD lines is then tested to be sure they also have been turned off. If either signal is on, the test fails. The RTS line is then turned on. The status of the CTS and DCD lines is again tested to be sure they have also been turned on. If either signal is off, the test fails. A 256-byte test message is then written from the transmitter on the device to the receiver on the device. A 256-byte read is then attempted on the receiver of the device. If the read does not complete within one second, the test fails. The test message received is then compared against the message that was sent. If they do not match, the test fails.

Finally, the RTS line on the port is turned off. The status of the CTS and DCD lines is once again tested to be sure they have also been turned off. If both signals have been turned off, the test passes and a message is generated. The Validation Suite has default settings for testing each port using modem control when available. A variation in the hardware configuration could make testing with modem control signals impossible. An –m option is available when running this test from a terminal to override the default setting for the port. For example, enter the following command at the OS-9 Shell $ prompt to test port SP1 without performing any modem control, enter the following command: vs_sploop1 /sp1 -m0 -t

7.1.2 Port-Port Loopback Test Selections C, D, E, and F from the Loopback Test sub-menu are all port to port loopback tests. Before running any of these tests, be sure to disconnect any device already connected to the port being tested and connect the proper loopback connector assembly from Table 7.1. When the test is initiated, a screen similarly formatted to Figure 7.4 is displayed on the Front Panel Assemble display. The screen contents may differ only in that ports that do not have RTS/CTS/DCD modem control signals exclude the signal status from those signals on the display.

Port-Port Loopback Test Port1:/sp1 RTS: CTS: DCD: Port2:/sp2 RTS: CTS: DCD: Pass: Loopback /sp1<->/sp2

Figure 7.4 This test begins by first opening a path to the each port under test. If any other program is currently using either port, the test fails. This is to insure no conflicts exist for the hardware resources on the 2070. While performing port to port tests, the control signal portions of the tests are performed only if both ports are control capable. If the ports being tested have control signals available, the RTS on the first port is then turned off. The status of the CTS signal on the first port is then tested to be sure it has also been turned off. The DCD line on the second port is also tested to be sure it has also been turned off. If either signal is on, the test fails and an appropriate message is generated. The RTS line on the first port is then turned on. The status of the CTS signal on the first port and DCD signal on the second port are again tested to be sure they have also been turned on. If either signal is off, the test fails and an appropriate message is generated. A 256 byte test message is then written from the transmitter on the first port to the receiver on the second port. A 256 byte read is then attempted from the receiver of the second port. If the read does not complete within one second, the test fails and an appropriate message is generated.

The test message received is then compared against the message that was sent. If they do not match, the test fails and an appropriate message is generated. Finally, the RTS line on the first port is turned off. The status of the CTS signal on the first port and DCD signal on the second port are once again tested to be sure they have also been turned off. If either signal remains on, the test fails and an appropriate message is generated. The test then repeats in the opposite direction. The RTS on the second port is turned off. The status of the CTS signal on the second port is then tested to be sure it has also been turned off. The DCD line on the first port is also tested to be sure it has also been turned off. If either signal is on, the test fails and an appropriate message is generated. The RTS line on the second port is then turned on. The status of the CTS signal on the second port and DCD signal on the first port are again tested to be sure they have also been turned on. If either signal is off, the test fails and an appropriate message is generated. A 256-byte test message is then written from the transmitter on the second port to the receiver on the first port. A 256-byte read is then attempted from the receiver of the first port. If the read does not complete within one second, the test fails and an appropriate message is generated. The test message received is then compared against the message that was sent. If they do not match, the test fails and an appropriate message is generated. Finally, the RTS control signal on the second port is turned off. The status of the CTS signal on the second port and DCD signal on the first port are once again tested to be sure they have also been turned off. If both signals have been turned off, the test passes and a message is generated.

7.2 Changing Asynchronous Port Parameters The port settings may be viewed by selecting the A) Port Settings options from the 2070 Async Loopback Test sub-menu. The display in figure 7.5 will be presented on the Front Panel Display Assembly display.

2070 Async Port Settings 1) SP1 2) SP2 3) SP3 4) SP4 5) SP5 6) SP8 0) Previous Menu Select Port:

Figure 7.5 Selecting from the menu, the Flow Control mode, baud rate, parity, stop bit, and data bit port settings are displayed along with the pause, echo, and Xoff function status as in the example in figure 7.6.

/sp2 Port Parameters 1) FC Mode: 0 0) Previous Menu Baud: 9600 Pause: NO Parity: NONE Echo: NO Stop: 1 X-Off: NO Data: 8 bit Select Option:

Figure 7.5 Pressing the ‘1’ key on the Front Panel Assembly keypad can change the flow control mode. Each time the key is pressed, the mode will increment up to flow control mode 5 and then reset to flow control mode zero. NOTE: To change port baud rate, parity, stop bit, data bit, pause, echo, and X-Off settings, use the OS-9 xmode facility from the OS-9 shell prompt.

7.3 SP1/SP2 Port Tests Selections 2 and 3 from the Port Tests sub-menu cause the validation suite to begin execution of the vs_sptest program as a background task on ports SP1 or SP2. Before running either of these tests, you should have an asynchronous terminal device connected to the port under test configured at the proper settings for the port. vs_sptest writes the current OS-9 Clock Time to the specified port once a second. Each key typed on the keyboard of the terminal device causes vs_sptest to delay one second. It will delay as long as characters are typed less than one second apart. After one second has elapsed since the last key is pressed, vs_sptest begins displaying the OS-9 Clock Time to the terminal device again. A sample output listing from vs_sptest might appear as follows: Port /sp1 16:00:23 Port /sp1 16:00:24 Port /sp1 16:00:25 Test message typed at terminal keyboard Port /sp1 16:00:28 Port /sp1 16:00:29 You must manually stop this test before attempting to perform any other test that requires use of the port. vs_sptest can be terminated by either typing a ctl-C from the terminal device keyboard or by killing the process started by the Validation Suite using the OS-9 kill command at the OS-9 Shell $ prompt. NOTE: Be sure to remove any port loopback plugs attached to the port under test prior to starting this test. Since this test echoes everything received on the input back to the output, it cannot be run with an individual port loopback plug installed on the port. The result of doing so is that the output fed back into the input continues to grow until the system becomes overloaded processing interrupts.

8 Other Testing using the OS-9 Shell Many tests can be performed using standard functions provided by OS-9. The following sections outline some common test procedures using a few of the available modules supplied with the Naztec 2070. 8.1 Setting the OS-9 Time of Day Clock The OS-9 TOD Clock can be set using the OS-9 setime command. Setime can set the time either to an operator specified value or to the value in the Hardware RTC. To set the clock to an operator specified time, type the following command at the OS-9 Shell $ prompt: setime The OS-9 shell will respond with the following prompt:

yy/mm/dd hh:mm:ss [am/pm] Time:

Entering the date and time formatted as indicated sets the OS-9 internal clock to the specified date and time. The OS-9 TOD Clock can also be set from the Hardware TOD Clock by issuing the following command: setime –s The OS-9 TOD Clock will be set from the Hardware TOD Clock. The two clocks are synchronized by OS-9 to within 10 milliseconds. 8.2 Setting the Hardware Time of Day Clock The Hardware Time of Day clock is set by first setting the OS-9 TOD Clock as documented in Section 8.1 and then executing the following command: echo >/clockupdate The Hardware Time of Day Clock will be set from the OS-9 TOD Clock. The two clocks are synchronized by OS-9 to within 10 milliseconds.

8.3 Testing Daylight Savings Time Correct operation of the daylight savings time function in OS-9 can be tested by first enabling the DST flag using the Validation Suite TOD Clocks test as shown in Section 4.6. The spring date can be tested by setting the OS-9 TOD Clock (Section 8.1) to a time just before any spring daylight savings time date and time (i.e. April 2, 2000 @ 1:59:00). The clock can then be checked using the OS-9 date program or by observing the clocks in the Validation Suite TOD Clocks test to verify that the clock is reset to 3:00:00 when it would normally cross over to 2:00:00. The fall date can similarly be tested by setting the OS-9 TOD Clock (Section 8.1) to a time just before the fall daylight savings date and time (i.e. October 29, 2000 @ 1:59:00). The clock can again be monitored using the OS-9 date program or by observing the clocks in the Validation Suite TOD Clocks test to verify that the clock is reset to 1:00:00 when it would normally cross over to 2:00:00. Additionally, the clock should roll over to 2:00 on the subsequent 1:59:59 to 2:00:00 crossing. NOTE: Because of the nature of testing for the fall daylight savings time change, the system must have first crossed into the spring daylight savings time change before it will recognize it is in daylight savings time before it can return to standard time.

8.4 Testing for Installed Software The Validation Suite Processor CPU/OS Test (Section 4.1) indicates the current version of OS-9 installed. Additional software provided along with OS-9 can be listed using the OS-9 mdir program from the OS-9 Shell $ prompt as follows: mdir mdir responds with a list of installed software modules similar to the following example:

Module Directory at 02:30:55 kernel ioman init fpu acfail tk2070nz rtclock scf null nil pipeman pipe scsmcnz sp4 sp6 scsccnz sp1 sp2 sp3 sp5 sclednz led scclknz clockupdate scdkeynz CPUDatakey nullfm tmrnz timer1 timer2 timer3 timer4 timer12 timer34 rbf ram r0 r0fmt r2 rbflash f0 f0fmt dd sysgo shell csl cio math attr break build copy date dcheck deiniz del deldir devs dir dump echo edt events free ident iniz irqs kermit link list lmm load mdir mfree pd makdir procs rename save setime sleep tmode unlink xmode tsmon umacs tar cpureset eeprom ftool sysinfo warmboot sysmbuf pkman pkdvr pk pks spf spf_rx spsdlnz sp1s sp2s sp3s sp5s sockman sockdvr tcp udp af_ether af_unix inet ip ifman ifloop lo0 ftp ftpd ftpdc ispcfg ispstart telnet telnetd telnetdc dlan es0 netdb socket valsuite vs_dmod

A more detailed report of installed software including module sizes, checksums, editions, and attributes can be obtained by appending the –e option to the mdir command. More information about mdir can be found in the OS-9 Utilities Reference manual available from Microware.

8.5 Testing Warmboot Trap The warmboot feature of the system (TEES 9.2.7.3.3) can be tested by entering the following command at the OS-9 Shell $ prompt: reboot The result will be that OS-9 will reboot as if the power were just turned on. NOTE: If the system is configured with OPEXEC installed, the result of performing a warmboot will be that OPEXEC will be executed as it does when the power is first applied to the Naztec 2070. If OPEXEC is not installed, the Validation Suite will be executed on the FPA and the Shell will be executed on the FPA console port (C50S). 8.6 Running FLRESTORE The FLRESTORE program (TEES 9.2.7.2.10) can be run from the OS-9 Shell Prompt by entering the following command: flrestore [-s=delay] The optional delay parameter can be specified indicating the amount of time to delay prior to restoring the backup sector copy of the Flash drive can be specified from 0 to 600 seconds. This value defaults to 30 seconds if no delay parameter is specified.

8.7 Running OS-9 xmode The OS-9 xmode utility can be used to change the operating parameters of serial ports defined in the board support package. It specifically can be used to change the baud rate the port is operating at, the number of data bits, the parity or the number of stop bits. As an example, the following command changes the characteristics for serial port /sp1 to 9600 baud, no parity, 8 data bits, 1 stop bit: xmode /sp1 baud=9600 parity=none cs=8 stop=1 There are many parameters available in the xmode command. Some help is available by typing “xmode -?” at the OS-9 Shell $ prompt. A complete reference can be found in the OS-9 Utilities Reference manual available from Microware.

8.8 Error Logging In order to demonstrate the error logging capabilities of the Naztec 2070, the single port loopback test, vs_sploop1 (Section 7.1.1), has been programmed with an option to send the results of testing to the OS-9 error handling routine. An error can easily be generated and logged by the Validation Suite by executing a port loopback test without the correct loopback test plug installed on /sp1 from the OS-9 Shell $ prompt as follows: load –d /f0/naztec/vs_sploop1 vs_sploop1 /sp1 -t -e The error log file “ErrorReport” is created on the SRAM RBF drive /r0 and can be listed using the standard OS-9 list utility by typing the following command at the OS-9 Shell $ prompt: list /r0/ErrorReport NOTE: The ErrorReport file grows as errors are reported by the Validation Suite and should periodically be reviewed and deleted to prevent /r0 from running out of storage.

8.9 Buffering Mode Demonstration The buffering mode requirements in TEES 9.2.7.2.6 and 9.2.7.2.7 have been demonstrated in vs_buff. vs_buff is an OS-9 Shell utility executed from the OS-9 Shell $ prompt. The format of the command line for the program is as follows: vs_buff [-m<mode>] [-e<eol>] [-l<len>] [-t<time>] As indicated, all of the calling parameters are optional and have assigned default values as indicated below. Parameter Description Default

-m Buffering modes fall into basic modes as follows: 0 = Raw Mode 1 = Line Mode 2 = Fixed Mode 4 = Timed Mode

They may be combined to form composite modes as follows:

3 = Fixed & Line Mode 5 = Line & Timed Mode 6 = Fixed & Timed Mode 7 = Line & Fixed & Timed Mode

-m0 (Raw)

-e End of line character used in Line Mode (modes 1, 3, 5, and 7). For example, to make the end of line character the character ‘z’, type –ez.

<CR>

-l Fixed buffer length used in Fixed Modes (modes 2, 3, 6, and 7).

-l16 bytes

-t Timeout used in modes 4, 5, 6, and 7. -t60 60 Sec.

vs_buff begins by first identifying the parameters it is using to execute. Only the parameters that apply to the mode(s) invoked are indicated. The most complete example is mode 7 where all basic modes are being used. Parameter verification might appear as follows:

Mode = 7 (Line/Fixed/Timed) End of Line Character = 0d Number of Characters = 16 Character Timeout = 5

vs_buff then displays the following prompt:

Enter characters (ESC or Ctl-C to exit) Characters are then entered based on the mode being demonstrated. The following table outlines the inputs and expected response for each mode.

Mode Entry/Response Raw Each character typed is echoed back to the screen on a separate line

as follows:

Key received a

Line Each character typed is echoed back to the screen and buffered by OS-9. When the end of line character is encountered, the entire line buffer is returned to the program and displayed on the screen as follows:

Line received: abcde

Fixed Each character typed is echoed back to the screen and buffered by OS-9. When the specified buffer length has been received, the entire buffer is returned to the program and displayed on the screen as follows:

Buffer Length (16) Received: 0 1 2 3 4 5 6 7 8 9 A B C D E F 00/ 31 32 33 34 35 36 37 38 39 30 31 32 33 34 35 36

Timed Each character typed is echoed back to the screen on a separate line. If a timeout occurs, it is indicated on the screen and the program waits on the next entry.

Key received d Key received e Timed Out Key received f

Line/ Fixed

Each character typed is echoed back to the screen and buffered by OS-9. When the end of line character is encountered, the program outputs the entire line buffer. Characters typed after the indicated buffer length has been received prior to the end of line character are lost.

Line received: abcde

Line/ Timed

Each character typed is echoed back to the screen and buffered by OS-9. If the end of line character is encountered before the timer expires, the program outputs the entire line buffer. If the timer expires, a timeout message is displayed.

Line received: abcde Timed Out

Fixed/ Timed

Each character typed is echoed back to the screen and buffer by OS-9. If the specified length is received, the entire buffer is returned to the program and displayed on the screen. If the timer expires before the buffer is filled, a timeout is returned and displayed on the screen.

Buffer Length (16) Received: 0 1 2 3 4 5 6 7 8 9 A B C D E F 00/ 31 32 33 34 35 36 37 38 39 30 31 32 33 34 35 36 Timed Out

Line/ Fixed/ Timed

Up to the specified buffer length, each character typed is echoed and buffered by OS-9. If the specified end of line character is received before the timer expires, it is displayed to the screen. If the timer expires, the timeout is displayed to the screen. Note that characters prior to the end of line character after the buffer has been filled are lost.

Line received: abcde Timed Out