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http://www.studyigniter.com/subject/university/Anna%20University/B.E%20-%20Electronics%20And%20Communication%20Engineering/EC2050%20-%20Mobile%20Adhoc%20Networks/1/50/429
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http://www.studyigniter.com/lecturenote/university/Anna%20University/B.E%20-%20Electronics%20And%20Communication%20Engineering/EC2354%20-%20Vlsi%20Design/vlsi%20design/1/50/470/1170
1. Draw the IV characteristics of CMOS.
2. Write the types of layout Design Rules.
3. What is logical effort.
4. Explain Scaling.
5. What is mean by latches.
6. Define synchronizers.
7. Why we need testing.
8. What is boundary scan.
9. Define RTL.
10.What is the purpose of latch.
11.A)Explain DC characteristics of CMOS inverter. (or)
B)Explain with diagrams CMOS process enhancements.
12.A)Explain the terms Design Margin,interconnect,Scaling.
B).Explain Device and circuit Characterisations.
13.A)Compare the circuit families . (or)
B)Draw and explain the Static and dynamic sequencing element
methodologies.
14. A)Draw and explain Testers and boundary scan (or)
B)Explain any one of testing principle.
15. A)Write about Desingn hierarchies and modeling.
B)Write the programs for the following,comparator,half adder
,full adder, D latch
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May June 2014 Important Questions
1. Derive the CMOS inverter DC characteristics and obtain the
relationship for o
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utput voltage at
different region in the transfer characteristics.
2. Explain with neat diagrams the various CMOS fabrication
technology
3. Explain the latch up prevention techniques.
4. Explain the silicon semiconductor fabrication process.
5. Explain various CAD tool sets
UNIT 2
1. Explain the operation of PMOS Enhancement transistor
2. Explain the threshold voltage equation
3. Explain the operation of NMOS Enhancement transistor.
4. Explain the Transmission gate and the tristate inverter
briefly.
5. Explain about the various non ideal conditions in MOS device
model.
UNIT 3
1. Explain the concept of MOSFET as switches
2. Explain the ASIC design flow with a neat diagram
3. Explain the concept of Delay estimation, logical effort and
sizing of MOSFET
UNIT 4
1.Explain fault models
a.stuck-At Faults
b.Explain ATPG
2.Briefly explain
a.fault grading and fault simulationb.delay fault
testingc.statistical fault analysis
3.explain scan based test techniques
4.explain self test techniques and IDDQ testing
5.explain system-level test techniques.
UNIT 5
1.Explain with neat diagram the multiplexer and latches using
transmission gate.
2.explain the concept of gate delay in verilog with example.
3.explain the concept of MOSFET as switches and also bring the
various logic gates using the switching concept.
