MIxed Signal Simulation Lab Manual I M.tech II Sem

7/24/2019 MIxed Signal Simulation Lab Manual I M.tech II Sem

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I M. Tech II Semester (VLSI) Mixed Signal Simulation Lab

Department of Electronics and Communication EngineeringRamachandra College of Engineering: ELURU

Exp No: 1

CMOS INVERTER

Aim:

a) To construct the CMOS Inverter in Tanner EDA v13.1 and to do the Transient

Analysis.

b) To analyze the response with appropriate wave forms and to verify the Spice code.

Tools used:

1. Tanner Tools v13.1

2. Schematic-Edit

3. Layout -Edit

4. Wave- Edit

5. Tanner Spice

Procedure:

1. Open S-Edit window.

2. Go to FileNewNew design

3. Go to CellNew View

4. Add libraries file to the New Cell.

5. Instance the devices by using appropriate library files.6. Save the design and setup the simulation.

7. Run design and observe waveforms.

8. Observe DC inputs and outputs by giving appropriate inputs.


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Schematic Diagram:

Fig (a): CMOS Inverter


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Tanner Spice Code:

* SPICE export by: SEDIT 13.12

* Export time: Fri Apr 16 11:43:07 2010

* Design: adm705-1* Cell: Cell3

* View: view0* Export as: top-level cell

* Export mode: hierarchical

* Exclude .model: no* Exclude .end: no

* Expand paths: yes

* Wrap lines: no

* Root path: C:\Documents and Settings\Administrator\Desktop\adm705-1* Exclude global pins: no

* Control property name: SPICE

********* Simulation Settings - General section *********

.lib "C:\Documents and Settings\Administrator\My Documents\Tanner EDA\Tanner Tools

v13.1\Libraries\Models\Generic_025.lib" TT

********* Simulation Settings - Parameters and SPICE Options *********

*-------- Devices: SPICE.ORDER > 0 --------

MNMOS_1 Out N_2 Gnd N_1 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p

PD=6.8u

MPMOS_1 Out N_2 Vdd N_3 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25pPD=6.8u

VVoltageSource_1 Vdd Gnd DC 5

VVoltageSource_2 N_2 Gnd PULSE(0 5 0 5n 5n 95n 200n).PRINT TRAN V(Out)

.PRINT TRAN V(N_2)

********* Simulation Settings - Analysis section *********

.tran 350ns 500ns

.dc lin source VVoltageSource_1 0 5 0.5

.print dc v(MNMOS_1,Gnd)

********* Simulation Settings - Additional SPICE commands *********

.end


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Output responses:

Fig (b): CMOS Inverter Waveforms


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DC Analysis:

Result:

The CMOS Inverter is constructed in Tanner EDA v13.1, the spice code is

generated and waveforms are verified.


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Exp No: 2

LOGIC GATES

Aim:

a) To construct the following Logic Gates in Tanner EDA v13.1 and to do the

Transient Analysis.

b) To analyze the response with appropriate wave forms. And to verify the Spice.

(i) NAND (ii) NOR (iii) OR (iv) AND (v) Ex-OR (vi) Ex-NOR

Tools used:


2. Schematic-Edit

3. Layout -Edit

4. Wave- Edit

5. Tanner Spice

Procedure:





5. Instance the devices by using appropriate library files.

6. Save the design and setup the simulation.




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Schematic Diagram:

(i) NAND Gate:

Fig : NAND Gate Schematic


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Tanner Spice Code:


* Export time: Fri Mar 26 11:08:22 2010* Design: Prasad

* Cell: Cell0




* Expand paths: yes

* Wrap lines: no

* Root path: C:\Documents and Settings\user\Desktop\705\Prasad* Exclude global pins: no


********* Simulation Settings - General section *********.lib "C:\Documents and Settings\user\My Documents\Tanner EDA\Tanner Tools



*-------- Devices: SPICE.ORDER > 0 --------MNMOS_1 Out In1 N_4 N_3 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p

PD=6.8u

MNMOS_2 N_4 In Gnd N_5 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25pPD=6.8u

MPMOS_1 Out In Vdd N_1 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25pPD=6.8uMPMOS_2 Out In1 Vdd N_2 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p

PD=6.8u

VVoltageSource_1 Vdd Gnd DC 5VVoltageSource_3 In Gnd PULSE(0 5 0 5n 5n 95n 200n)

VVoltageSource_2 In1 Gnd PULSE(0 5 0 5n 5n 95n 200n)

.PRINT TRAN V(In)

.PRINT TRAN V(In1)

.PRINT TRAN V(Out)

********* Simulation Settings - Analysis section *********.tran 350ns 500ns

.dc lin source VVoltageSource_2 0 5 0.5 sweep lin source VVoltageSource_3 0 5 0.5

.print dc v(MPMOS_1,Gnd)


.end


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Output responses:

INPUT A

INPUT B

OUTPUT

Fig : NAND Gate Waveforms


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(ii) NOR Gate:

Fig :NOR Gate Schematic


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Tanner Spice Code:


* Export time: Fri Mar 26 12:26:28 2010* Design: Prasad

* Cell: Cell3

* View: view0* Export as: top-level cell* Export mode: hierarchical

* Exclude .model: no

* Exclude .end: no* Expand paths: yes

* Wrap lines: no






*-------- Devices: SPICE.ORDER > 0 --------MNMOS_1 Out In1 Gnd N_2 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p

PD=6.8u

MNMOS_2 Out In Gnd N_1 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p

PD=6.8u

MPMOS_1 N_4 In Vdd N_5 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25pPD=6.8u

MPMOS_2 Out In1 N_4 N_3 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25pPD=6.8u


VVoltageSource_2 In1 Gnd PULSE(0 5 0 5n 5n 25n 50n)VVoltageSource_3 In Gnd PULSE(0 5 0 5n 5n 50n 100n)

.PRINT TRAN V(In)

.PRINT TRAN V(In1)

.PRINT TRAN V(Out)

********* Simulation Settings - Analysis section *********.tran 350ns 500ns.dc lin source vvoltagesource_2 0 5 0.5 sweep lin source vvoltagesource_3 0 5 0.5

.print dc v(MPMOS_2,gnd)


.end


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Output responses:

Fig : NOR Gate Waveforms


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(iii) AND Gate:

Fig : AND Gate Schematic

Tanner Spice Code:

* SPICE export by: SEDIT 13.12* Export time: Fri Mar 26 11:32:44 2010

* Design: Prasad

* Cell: Cell1


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* Expand paths: yes

* Wrap lines: no







MNMOS_1 N_4 In1 N_2 N_3 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25pPD=6.8u

MNMOS_2 N_2 In Gnd N_1 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25pPD=6.8u

MNMOS_3 Out N_4 Gnd N_7 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25pPD=6.8u

MPMOS_1 N_4 In Vdd N_6 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p

PD=6.8uMPMOS_2 N_4 In1 Vdd N_5 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p

PD=6.8u



VVoltageSource_2 In1 Gnd PULSE(0 5 0 5n 5n 95n 200n)VVoltageSource_3 In Gnd PULSE(0 5 0 5n 5n 95n 200n).PRINT TRAN V(In)

.PRINT TRAN V(In1)

.PRINT TRAN V(Out)********* Simulation Settings - Analysis section *********

.tran 350ns 500ns

.dc lin source vvoltagesource_2 0 5 0.5 sweep lin source vvoltagesource_3 0 5 0.5

.print dc v(MPMOS_3,gnd)


.end


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Output responses:

Fig : AND Gate Waveforms


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Layout Diagram of AND gate:


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Layout Net list of AND:

* Circuit Extracted by Tanner Research's L-Edit Version 13.00 / Extract Version 13.00 ;* TDB File: Layout1

* Cell: Core Version 1.01* Extract Definition File: lights.ext

* Extract Date and Time: 07/27/2010 - 09:56

.include lights.md

* NODE NAME ALIASES

* 1 = Vdd (-50 , 4)

* 1 = U1/NAND2C_1/Vdd (0 , 70)

* 1 = U1/NAND2C_2/Vdd (34 , 70)* 2 = Gnd (41 , 4)

* 2 = U1/NAND2C_1/Gnd (0 , 12)* 2 = U1/NAND2C_2/Gnd (34 , 12)* 3 = Out (49 , 82.5)

* 3 = U1/NAND2C_2/Out1 (19 , 36)

* 4 = a (-50 , 82.5)* 4 = U1/NAND2C_1/A (-31 , 54)

* 5 = U1/NAND2C_1/Out1 (-15 , 36)

* 5 = U1/NAND2C_2/A (3 , 54)* 5 = U1/NAND2C_2/B (11 , 47)

* 6 = b (-50 , 4.5)

* 6 = U1/NAND2C_1/B (-23 , 47)

* 7 = U1/NAND2C_2/Out2 (27 , 38)* 8 = U1/NAND2C_1/Out2 (-7 , 38)

M1 Vdd U1/NAND2C_1/Out1 Out Vdd PMOS L=2u W=28u AD=84p PD=34u AS=84p

PS=34u

M2 Out U1/NAND2C_1/Out1 Vdd Vdd PMOS L=2u W=28u AD=84p PD=34u AS=144pPS=68u

M3 U1/NAND2C_2/Out2 Out Vdd Vdd PMOS L=2u W=28u AD=148p PD=68u AS=84p

PS=34u

M4 Vdd b U1/NAND2C_1/Out1 Vdd PMOS L=2u W=28u AD=84p PD=34u AS=84p

PS=34uM5 U1/NAND2C_1/Out1 a Vdd Vdd PMOS L=2u W=28u AD=84p PD=34u AS=144p

PS=68uM6 U1/NAND2C_1/Out2 U1/NAND2C_1/Out1 Vdd Vdd PMOS L=2u W=28u AD=148p

PD=68u AS=84p PS=34u

M7 Gnd U1/NAND2C_1/Out1 10 Gnd NMOS L=2u W=28u AD=122p PD=47u AS=28pPS=30u


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M8 10 U1/NAND2C_1/Out1 Out Gnd NMOS L=2u W=28u AD=28p PD=30u AS=148pPS=68u

M9 U1/NAND2C_2/Out2 Out Gnd Gnd NMOS L=2u W=28u AD=148p PD=68u AS=122p

PS=47uM10 Gnd b 9 Gnd NMOS L=2u W=28u AD=122p PD=47u AS=28p PS=30u

M11 9 a U1/NAND2C_1/Out1 Gnd NMOS L=2u W=28u AD=28p PD=30u AS=148p

PS=68u

M12 U1/NAND2C_1/Out2 U1/NAND2C_1/Out1 Gnd Gnd NMOS L=2u W=28u AD=148pPD=68u AS=122p PS=47u

* Total Nodes: 10* Total Elements: 12

* Total Number of Shorted Elements not written to the SPICE file: 4

* Output Generation Elapsed Time: 0.016 sec* Total Extract Elapsed Time: 2.328 sec

.END


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(iv) OR Gate:

Fig : OR Gate Schematic


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Tanner Spice Code:


* Export time: Fri Mar 26 12:18:24 2010

* Design: Prasad

* Cell: Cell2* View: view0

* Export as: top-level cell* Export mode: hierarchical





.lib "C:\Documents and Settings\user\My Documents\Tanner EDA\Tanner Toolsv13.1\Libraries\Models\Generic_025.lib" TT

********* Simulation Settings - Parameters and SPICE Options **********-------- Devices: SPICE.ORDER > 0 --------

MNMOS_1 N_4 In1 Gnd N_5 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p

PD=6.8uMNMOS_2 N_4 In Gnd N_6 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p

PD=6.8u

MNMOS_3 Out N_4 Gnd N_8 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25pPD=6.8u

MPMOS_1 N_2 In Vdd N_1 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p

PD=6.8u

MPMOS_2 N_4 In1 N_2 N_3 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25pPD=6.8u

MPMOS_3 Out N_4 Vdd N_7 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p

PD=6.8uVVoltageSource_1 Vdd Gnd DC 5


VVoltageSource_3 In Gnd PULSE(0 5 0 5n 5n 50n 100n).PRINT TRAN V(In)

.PRINT TRAN V(In1)

.PRINT TRAN V(Out)

********* Simulation Settings - Analysis section *********.tran 350ns 500ns

.dc lin source vvoltagesource_2 0 5 0.5 sweep lin source vvoltagesource_3 0 5 0.5

.print dc v(MNMOS_3,gnd)

********* Simulation Settings - Additional SPICE commands *********.end


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Output responses:

Fig : OR Gate Waveforms


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Layout Diagram of OR Gate:


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OR Layout Net List:

* Circuit Extracted by Tanner Research's L-Edit Version 13.00 / Extract Version 13.00 ;

* TDB File: Layout1



.include lights.md

* NODE NAME ALIASES* 1 = U1/NAND2C_3/Out2 (44 , 46)

* 2 = a (-67 , 90.5)

* 2 = U1/NAND2C_1/A (-48 , 62)* 2 = U1/NAND2C_1/B (-40 , 55)

* 3 = U1/NAND2C_1/Out1 (-32 , 44)

* 3 = U1/NAND2C_3/A (20 , 62)

* 4 = b (-67 , 4.5)* 4 = U1/NAND2C_2/A (-14 , 62)

* 4 = U1/NAND2C_2/B (-6 , 55)

* 5 = U1/NAND2C_2/Out2 (10 , 46)* 6 = U1/NAND2C_1/Out2 (-24 , 46)

* 7 = Out (66 , 90.5)

* 7 = U1/NAND2C_3/Out1 (36 , 44)* 8 = Vdd (-67 , 4)* 8 = U1/NAND2C_1/Vdd (-17 , 78)

* 8 = U1/NAND2C_2/Vdd (17 , 78)

* 8 = U1/NAND2C_3/Vdd (17 , 78)* 11 = Gnd (58 , 4)

* 11 = U1/NAND2C_1/Gnd (-17 , 20)

* 11 = U1/NAND2C_2/Gnd (17 , 20)* 11 = U1/NAND2C_3/Gnd (17 , 20)

* 12 = U1/NAND2C_2/Out1 (2 , 44)

* 12 = U1/NAND2C_3/B (28 , 55)

M1 Vdd U1/NAND2C_2/Out1 Out Vdd PMOS L=2u W=28u AD=84p PD=34u AS=84p

PS=34uM2 U1/NAND2C_3/Out2 Out Vdd Vdd PMOS L=2u W=28u AD=148p PD=68u AS=84p

PS=34u

M3 U1/NAND2C_3/Out2 Out Gnd Gnd NMOS L=2u W=28u AD=148p PD=68u AS=122pPS=47u

M4 Out U1/NAND2C_1/Out1 Vdd Vdd PMOS L=2u W=28u AD=84p PD=34u AS=144p

PS=68u


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M5 Vdd b U1/NAND2C_2/Out1 Vdd PMOS L=2u W=28u AD=84p PD=34u AS=84pPS=34u

M6 U1/NAND2C_2/Out1 b Vdd Vdd PMOS L=2u W=28u AD=84p PD=34u AS=144p

PS=68uM7 U1/NAND2C_2/Out2 U1/NAND2C_2/Out1 Vdd Vdd PMOS L=2u W=28u AD=148p


M8 Vdd a U1/NAND2C_1/Out1 Vdd PMOS L=2u W=28u AD=84p PD=34u AS=84p

PS=34uM9 U1/NAND2C_1/Out1 a Vdd Vdd PMOS L=2u W=28u AD=84p PD=34u AS=144p

PS=68u

M10 U1/NAND2C_1/Out2 U1/NAND2C_1/Out1 Vdd Vdd PMOS L=2u W=28u AD=148pPD=68u AS=84p PS=34u

M11 Gnd U1/NAND2C_2/Out1 13 Gnd NMOS L=2u W=28u AD=122p PD=47u AS=28p

PS=30uM12 13 U1/NAND2C_1/Out1 Out Gnd NMOS L=2u W=28u AD=28p PD=30u AS=148p

PS=68u

M13 Gnd b 10 Gnd NMOS L=2u W=28u AD=122p PD=47u AS=28p PS=30uM14 10 b U1/NAND2C_2/Out1 Gnd NMOS L=2u W=28u AD=28p PD=30u AS=148p

PS=68uM15 U1/NAND2C_2/Out2 U1/NAND2C_2/Out1 Gnd Gnd NMOS L=2u W=28u AD=148p

PD=68u AS=122p PS=47uM16 Gnd a 9 Gnd NMOS L=2u W=28u AD=122p PD=47u AS=28p PS=30u

M17 9 a U1/NAND2C_1/Out1 Gnd NMOS L=2u W=28u AD=28p PD=30u AS=148p

PS=68uM18 U1/NAND2C_1/Out2 U1/NAND2C_1/Out1 Gnd Gnd NMOS L=2u W=28u AD=148p


* Total Nodes: 13

* Total Elements: 18

* Total Number of Shorted Elements not written to the SPICE file: 6* Output Generation Elapsed Time: 0.000 sec* Total Extract Elapsed Time: 2.468 sec

.END


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(v) Ex-OR Gate:

Fig : Ex-OR Gate Schematic


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Tanner Spice Code:


*-------- Devices: SPICE.ORDER > 0 --------MNMOS_3 N_2 N_3 Gnd N_1 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p

PD=6.8u

MNMOS_4 N_3 In2 Gnd N_18 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25pPD=6.8uMNMOS_5 N_5 In2 Gnd N_4 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p

PD=6.8u

MNMOS_6 N_7 In1 N_2 N_6 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25pPD=6.8u

MNMOS_7 Out N_7 Gnd N_19 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p

PD=6.8uMNMOS_1 N_8 In1 Gnd N_16 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p

PD=6.8u

MNMOS_2 N_7 N_8 N_5 N_15 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p

PD=6.8uMPMOS_1 N_9 N_8 Vdd N_10 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p

PD=6.8u

MPMOS_2 N_3 In2 Vdd N_11 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25pPD=6.8u

MPMOS_3 N_7 In1 N_9 N_12 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p


PD=6.8u

MPMOS_5 N_7 N_3 N_9 N_14 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p

PD=6.8u




VVoltageSource_2 In2 Gnd PULSE(0 5 0 5n 5n 50n 25n)VVoltageSource_3 In1 Gnd PULSE(0 5 0 5n 5n 100n 50n)

.PRINT TRAN V(In1)

.PRINT TRAN V(In2)

.PRINT TRAN V(Out)


.tran 350ns 500ns




.end


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Output responses:INPUT A

INPUT B

OUTPUT

Fig : Ex-OR Gate Waveforms


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(vi) Ex-NOR Gate:

Fig : Ex-NOR Gate Schematic


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Tanner Spice Code:


.lib "C:\Documents and Settings\Administrator\My Documents\Tanner EDA\Tanner Toolsv13.1\Libraries\Models\Generic_025.lib" TT




PD=6.8uMNMOS_2 Out N_26 N_4 N_1 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p

PD=6.8u

MNMOS_3 N_19 N_14 Gnd N_11 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25pPD=6.8u


PD=6.8u

MNMOS_5 N_4 In2 Gnd N_10 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25pPD=6.8u

MNMOS_6 Out In1 N_19 N_9 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p

PD=6.8uMPMOS_1 N_3 N_26 Vdd N_8 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p

PD=6.8u


MPMOS_3 Out In1 N_3 N_6 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p

PD=6.8u

MPMOS_4 N_3 In2 Vdd N_5 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p

PD=6.8uMPMOS_5 Out N_14 N_3 N_2 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p


PD=6.8u

VVoltageSource_1 Vdd Gnd DC 5VVoltageSource_2 In2 Gnd PULSE(0 5 0 5n 5n 50n 25n)


.PRINT TRAN V(In1)

.PRINT TRAN V(In2)

.PRINT TRAN V(Out)

********* Simulation Settings - Analysis section *********.tran 350ns 500ns.dc lin source VVoltageSource_2 0 5 0.5 sweep lin source VVoltageSource_3 0 5 0.5



.end


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Output responses:

INPUT A

INPUT B

OUTPUT

Fig : Ex-NOR Gate Waveforms

Result:

The Logic Gates are constructed in Tanner EDA v13.1, the spice code is

generated and wave forms are verified.


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Exp No: 3

HALF ADDER

Aim:

a) To construct the Half Adder in Tanner EDA v13.1 and to do the Transient

Analysis.


Tools used:


2. Schematic-Edit

3. Layout -Edit

4. Wave- Edit

5. Tanner Spice

Procedure:





5.Instance the devices by using appropriate library files.





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Schematic Diagram:

Fig (a): Half Adder Schematic

Tanner Spice Code:

* SPICE export by: SEDIT 13.12* Export time: Fri Apr 16 11:24:00 2010

* Design: adm705-1


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* Cell: Cell2* View: view0

* Export as: top-level cell

* Export mode: hierarchical* Exclude .model: no

* Exclude .end: no

* Expand paths: yes

* Wrap lines: no* Root path: C:\Documents and Settings\Administrator\Desktop\adm705-1

* Exclude global pins: no


********* Simulation Settings - General section *********.lib "C:\Documents and Settings\Administrator\My Documents\Tanner EDA\Tanner Tools


*************** Subcircuits *****************.subckt INV A Out Gnd Vdd

*-------- Devices: SPICE.ORDER < 0 --------

* Design: LogicGates / Cell: INV / View: Main / Page:* Designed by: Tanner EDA Library Development Team

* Organization: Tanner EDA - Tanner Research, Inc.

* Info: Inverter* Date: 6/14/2007 1:47:11 AM

* Revision: 3


MN1 Out A Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8uMP1 Out A Vdd Vdd PMOS W=2.5u L=250n M=2 AS=1.5625p PS=3.75u AD=2.25p

PD=6.8u.ends

.subckt NAND2C A B Out1 Out2 Gnd Vdd*-------- Devices: SPICE.ORDER < 0 --------

* Design: LogicGates / Cell: NAND2C / View: Main / Page:

* Designed by: Tanner EDA Library Development Team* Organization: Tanner EDA - Tanner Research, Inc.

* Info: 2 Input NAND with complementary output.

* Date: 6/14/2007 1:47:11 AM* Revision: 2


MN1 Out1 A 1 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8uMN2 1 B Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u

MN3 Out2 Out1 Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u


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MP1 Out1 A Vdd Vdd PMOS W=2.5u L=250n M=2 AS=1.5625p PS=3.75u AD=2.25pPD=6.8u

MP2 Out1 B Vdd Vdd PMOS W=2.5u L=250n M=2 AS=1.5625p PS=3.75u AD=2.25p

PD=6.8uMP3 Out2 Out1 Vdd Vdd PMOS W=2.5u L=250n M=2 AS=1.5625p PS=3.75u AD=2.25p

PD=6.8u

.ends

.subckt XNOR2 A B Out Gnd Vdd


* Design: LogicGates / Cell: XNOR2 / View: Main / Page:* Designed by: Tanner EDA Library Development Team


* Info: 2 Input NOR* Date: 7/18/2008 3:58:48 AM

* Revision: 4


MM3n 1 A 2 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8uMM10n Out 1 5 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u

MM9n 5 A Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8uMM8n Out 1 4 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u

MM7n 4 B Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u

MM4n 2 B Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8uMM5p 3 B Vdd Vdd PMOS W=2.5u L=250n M=2 AS=1.5625p PS=3.75u AD=2.25p

PD=6.8u

MM11p Out 1 Vdd Vdd PMOS W=2.5u L=250n M=2 AS=1.5625p PS=3.75u AD=2.25pPD=6.8u

MM2p 1 B Vdd Vdd PMOS W=2.5u L=250n M=2 AS=1.5625p PS=3.75u AD=2.25p

PD=6.8uMM1p 1 A Vdd Vdd PMOS W=2.5u L=250n M=2 AS=1.5625p PS=3.75u AD=2.25pPD=6.8u

MM6p Out A 3 Vdd PMOS W=2.5u L=250n M=2 AS=1.5625p PS=3.75u AD=2.25p

PD=6.8u.ends

.subckt XOR2 A B Out Gnd Vdd*-------- Devices: SPICE.ORDER < 0 --------

* Design: LogicGates / Cell: XOR2 / View: Main / Page:

* Designed by: Tanner EDA Library Development Team

* Organization: Tanner EDA - Tanner Research, Inc.* Info: 2 Input NOR

* Date: 7/18/2008 1:30:51 AM

* Revision: 3

*-------- Devices: SPICE.ORDER == 0 --------

XXinv N_1 Out Gnd Vdd INV


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XXxnor A B N_1 Gnd Vdd XNOR2.ends



XINV_1 N_1 carry Gnd Vdd INVXNAND2C_1 In1 In2 N_1 N_2 Gnd Vdd NAND2C

XXOR2_1 In1 In2 sum Gnd Vdd XOR2

*-------- Devices: SPICE.ORDER > 0 --------VVoltageSource_3 Vdd Gnd DC 5


VVoltageSource_2 In2 Gnd PULSE(0 5 0 5n 5n 25n 50n).PRINT TRAN V(In1)

.PRINT TRAN V(In2)

.PRINT TRAN V(carry)

.PRINT TRAN V(sum)


.tran 350ns 500ns


.print dc v(XINV_1,GND)

.print dc v(XXOR2_1,GND)


.end


36/150



Output responses:

Result:

The Half Adder is constructed in Tanner EDA v13.1, the spice code is generated and

wave forms are verified.


37/150



Exp No: 4

FULL ADDER

Aim:

a) To construct the Full Adder in Tanner EDA v13.1 and to do the Transient

Analysis.


Tools used:


2. Schematic-Edit

3. Layout -Edit

4. Wave- Edit

5. Tanner Spice

Procedure:










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Schematic Diagram:

Fig (a): Full Adder Schematic1

Fig (b): Full Adder Schematic2


39/150



Tanner Spice Code:


.lib "C:\Documents and Settings\Administrator\My Documents\Tanner EDA\Tanner Tools


*************** Subcircuits *****************

.subckt INV A Out Gnd Vdd*-------- Devices: SPICE.ORDER < 0 --------* Design: LogicGates / Cell: INV / View: Main / Page:


* Organization: Tanner EDA - Tanner Research, Inc.* Info: Inverter

* Date: 6/14/2007 1:47:11 AM

* Revision: 3


MN1 Out A Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u

MP1 Out A Vdd Vdd PMOS W=2.5u L=250n M=2 AS=1.5625p PS=3.75u AD=2.25pPD=6.8u

.ends

.subckt NAND2C A B Out1 Out2 Gnd Vdd


* Design: LogicGates / Cell: NAND2C / View: Main / Page:* Designed by: Tanner EDA Library Development Team



* Date: 6/14/2007 1:47:11 AM

* Revision: 2

*-------- Devices: SPICE.ORDER > 0 --------MN1 Out1 A 1 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u

MN2 1 B Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u

MN3 Out2 Out1 Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8uMP1 Out1 A Vdd Vdd PMOS W=2.5u L=250n M=2 AS=1.5625p PS=3.75u AD=2.25p

PD=6.8u

MP2 Out1 B Vdd Vdd PMOS W=2.5u L=250n M=2 AS=1.5625p PS=3.75u AD=2.25pPD=6.8u

MP3 Out2 Out1 Vdd Vdd PMOS W=2.5u L=250n M=2 AS=1.5625p PS=3.75u AD=2.25p

PD=6.8u.ends

.subckt NAND3C A B C Out1 Out2 Gnd Vdd

*-------- Devices: SPICE.ORDER < 0 --------* Design: LogicGates / Cell: NAND3C / View: Main / Page:

* Designed by: Author

* Organization: Organization


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* Info: Info* Date: 6/14/2007 1:47:11 AM

* Revision: 3


MN1 Out1 C 1 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u

MN2 1 B 2 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u

MN3 2 A Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8uMN4 Out2 Out1 Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u

MP1 Out1 A Vdd Vdd PMOS W=2.5u L=250n M=2 AS=1.5625p PS=3.75u AD=2.25p

PD=6.8uMP2 Out1 B Vdd Vdd PMOS W=2.5u L=250n M=2 AS=1.5625p PS=3.75u AD=2.25p

PD=6.8u

MP3 Out1 C Vdd Vdd PMOS W=2.5u L=250n M=2 AS=1.5625p PS=3.75u AD=2.25pPD=6.8u

MP4 Out2 Out1 Vdd Vdd PMOS W=2.5u L=250n M=2 AS=1.5625p PS=3.75u AD=2.25p

PD=6.8u.ends

.subckt XNOR2 A B Out Gnd Vdd

*-------- Devices: SPICE.ORDER < 0 --------* Design: LogicGates / Cell: XNOR2 / View: Main / Page:


* Organization: Tanner EDA - Tanner Research, Inc.* Info: 2 Input NOR

* Date: 7/18/2008 3:58:48 AM

* Revision: 4


MM3n 1 A 2 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8uMM10n Out 1 5 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8uMM9n 5 A Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u

MM8n Out 1 4 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u

MM7n 4 B Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8uMM4n 2 B Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u


PD=6.8uMM11p Out 1 Vdd Vdd PMOS W=2.5u L=250n M=2 AS=1.5625p PS=3.75u AD=2.25p

PD=6.8u


PD=6.8uMM1p 1 A Vdd Vdd PMOS W=2.5u L=250n M=2 AS=1.5625p PS=3.75u AD=2.25p

PD=6.8u

MM6p Out A 3 Vdd PMOS W=2.5u L=250n M=2 AS=1.5625p PS=3.75u AD=2.25pPD=6.8u

.ends


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.subckt XOR2 A B Out Gnd Vdd*-------- Devices: SPICE.ORDER < 0 --------

* Design: LogicGates / Cell: XOR2 / View: Main / Page:

* Designed by: Tanner EDA Library Development Team* Organization: Tanner EDA - Tanner Research, Inc.

* Info: 2 Input NOR

* Date: 7/18/2008 1:30:51 AM

* Revision: 3


XXinv N_1 Out Gnd Vdd INVXXxnor A B N_1 Gnd Vdd XNOR2

.ends



XXOR2_2 N_8 In3 sum Gnd Vdd XOR2XNAND3C_1 N_1 N_2 N_3 carry N_4 Gnd Vdd NAND3C

XNAND2C_1 In1 In2 N_1 N_7 Gnd Vdd NAND2CXNAND2C_2 In2 In3 N_2 N_6 Gnd Vdd NAND2C

XNAND2C_3 In1 In3 N_3 N_5 Gnd Vdd NAND2C

XXOR2_1 In1 In2 N_8 Gnd Vdd XOR2*-------- Devices: SPICE.ORDER > 0 --------


VVoltageSource_1 In1 Gnd PULSE(0 5 0 5n 5n 100n 200n)VVoltageSource_2 In2 Gnd PULSE(0 5 0 5n 5n 50n 100n)


.PRINT TRAN V(In1)

.PRINT TRAN V(In2)

.PRINT TRAN V(In3)

.PRINT TRAN V(sum)

.PRINT TRAN V(carry)


.tran 350ns 500ns

.dc lin source VVOLTAGESOURCE_1 0 5 0.5 sweep lin source VVOLTAGESOURCE_2 0

5 0.5 sweep lin source VVOLTAGESOURCE_3 0 5 0.5

.print dc v(XXOR2_2,GND)

.print dc v(XXOR2_2,GND) v(XNAND3C_1,GND)


.end


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Output responses:INPUT V(A)

INPUT

V(B)

INPUT V(C)

OUTPUT V(SUM)

OUTPUT V(CARRY)

Fig (b): Full Adder wave forms

Layout Diagram of Full adder:


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Layout Net list:


* TDB File: Layout1



.include lights.md

* NODE NAME ALIASES


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* 1 = CARRY (125 , 142.5)* 1 = U2/NAND2C_9/Out1 (87 , 96)

* 2 = SUM (125 , 56.5)

* 2 = U2/NAND2C_8/Out1 (53 , 96)* 3 = U2/NAND2C_7/Out1 (19 , 96)

* 3 = U2/NAND2C_8/B (45 , 107)

* 4 = U2/NAND2C_9/Out2 (95 , 98)


* 10 = U2/NAND2C_6/Out1 (-15 , 96)

* 10 = U2/NAND2C_8/A (37 , 114)* 11 = U2/NAND2C_5/Out1 (-49 , 96)

* 11 = U2/NAND2C_6/B (-23 , 107)

* 11 = U2/NAND2C_7/A (3 , 114)* 11 = U2/NAND2C_9/B (79 , 107)

* 12 = U2/NAND2C_5/A (-65 , 114)

* 12 = U2/NAND2C_6/A (-31 , 114)* 12 = U3/NAND2C_4/Out1 (53 , -22)

* 13 = U2/NAND2C_6/Out2 (-7 , 98)* 14 = U2/NAND2C_5/Out2 (-41 , 98)

* 17 = U3/NAND2C_3/Out1 (19 , -22)* 17 = U3/NAND2C_4/B (45 , -11)

* 18 = U3/NAND2C_4/Out2 (61 , -20)

* 19 = U3/NAND2C_3/Out2 (27 , -20)* 22 = Vdd (-100 , -62)

* 22 = U2/A/Vdd (-68 , 130)

* 22 = U2/NAND2C_5/Vdd (-34 , 130)* 22 = U2/NAND2C_6/Vdd (-34 , 130)

* 22 = U2/NAND2C_7/Vdd (34 , 130)

* 22 = U2/NAND2C_8/Vdd (68 , 130)* 22 = U2/NAND2C_9/Vdd (68 , 130)* 22 = U3/Cin/Vdd (-34 , 12)

* 22 = U3/NAND2C_1/Vdd (-42 , 12)

* 22 = U3/NAND2C_2/Vdd (-34 , 12)* 22 = U3/NAND2C_3/Vdd (34 , 12)

* 22 = U3/NAND2C_4/Vdd (68 , 12)

* 23 = Gnd (109 , -62)* 23 = U2/A/Gnd (-68 , 72)

* 23 = U2/NAND2C_5/Gnd (-34 , 72)

* 23 = U2/NAND2C_6/Gnd (-34 , 72)

* 23 = U2/NAND2C_7/Gnd (34 , 72)* 23 = U2/NAND2C_8/Gnd (68 , 72)

* 23 = U2/NAND2C_9/Gnd (68 , 72)

* 23 = U3/Cin/Gnd (-34 , -46)* 23 = U3/NAND2C_1/Gnd (-42 , -46)

* 23 = U3/NAND2C_2/Gnd (-34 , -46)

* 23 = U3/NAND2C_3/Gnd (34 , -46)


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* 23 = U3/NAND2C_4/Gnd (68 , -46)* 24 = U2/NAND2C_9/A (71 , 114)

* 24 = U3/NAND2C_1/Out1 (-57 , -22)

* 24 = U3/NAND2C_2/B (-23 , -11)* 24 = U3/NAND2C_3/A (3 , -4)

* 25 = A (-100 , 142.5)

* 25 = U3/NAND2C_1/A (-73 , -4)

* 25 = U3/NAND2C_2/A (-31 , -4)* 26 = Cin (-100 , -61.5)

* 26 = U2/NAND2C_5/B (-57 , 107)

* 26 = U2/NAND2C_7/B (11 , 107)* 27 = B (-100 , 32.5)

* 27 = U3/NAND2C_1/B (-65 , -11)

* 27 = U3/NAND2C_3/B (11 , -11)* 28 = U3/NAND2C_2/Out1 (-15 , -22)

* 28 = U3/NAND2C_4/A (37 , -4)

* 29 = U3/NAND2C_2/Out2 (-7 , -20)* 30 = U3/NAND2C_1/Out2 (-49 , -20)

M1 Vdd U2/NAND2C_5/Out1 CARRY Vdd PMOS L=2u W=28u AD=84p PD=34u

AS=84p PS=34uM2 CARRY U2/NAND2C_9/A Vdd Vdd PMOS L=2u W=28u AD=84p PD=34u AS=144p

PS=68u

M3 U2/NAND2C_9/Out2 CARRY Vdd Vdd PMOS L=2u W=28u AD=148p PD=68uAS=84p PS=34u

M4 Vdd U2/NAND2C_7/Out1 SUM Vdd PMOS L=2u W=28u AD=84p PD=34u AS=84p

PS=34uM5 SUM U2/NAND2C_6/Out1 Vdd Vdd PMOS L=2u W=28u AD=84p PD=34u AS=144p

PS=68u

M6 U2/NAND2C_8/Out2 SUM Vdd Vdd PMOS L=2u W=28u AD=148p PD=68u AS=84pPS=34uM7 Vdd Cin U2/NAND2C_7/Out1 Vdd PMOS L=2u W=28u AD=84p PD=34u AS=84p

PS=34u


M9 U2/NAND2C_7/Out2 U2/NAND2C_7/Out1 Vdd Vdd PMOS L=2u W=28u AD=148p

PD=68u AS=84p PS=34uM10 Gnd U2/NAND2C_5/Out1 9 Gnd NMOS L=2u W=28u AD=122p PD=47u AS=28p

PS=30u

M11 9 U2/NAND2C_9/A CARRY Gnd NMOS L=2u W=28u AD=28p PD=30u AS=148p

PS=68uM12 U2/NAND2C_9/Out2 CARRY Gnd Gnd NMOS L=2u W=28u AD=148p PD=68u

AS=122p PS=47u

M13 Gnd U2/NAND2C_7/Out1 8 Gnd NMOS L=2u W=28u AD=122p PD=47u AS=28pPS=30u

M14 8 U2/NAND2C_6/Out1 SUM Gnd NMOS L=2u W=28u AD=28p PD=30u AS=148p

PS=68u


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M15 U2/NAND2C_8/Out2 SUM Gnd Gnd NMOS L=2u W=28u AD=148p PD=68uAS=122p PS=47u

M16 Gnd Cin 7 Gnd NMOS L=2u W=28u AD=122p PD=47u AS=28p PS=30u

M17 7 U2/NAND2C_5/Out1 U2/NAND2C_7/Out1 Gnd NMOS L=2u W=28u AD=28pPD=30u AS=148p PS=68u

M18 U2/NAND2C_7/Out2 U2/NAND2C_7/Out1 Gnd Gnd NMOS L=2u W=28u AD=148p


M19 Vdd U2/NAND2C_5/Out1 U2/NAND2C_6/Out1 Vdd PMOS L=2u W=28u AD=84pPD=34u AS=84p PS=34u

M20 U2/NAND2C_6/Out1 U2/NAND2C_5/A Vdd Vdd PMOS L=2u W=28u AD=84p

PD=34u AS=144p PS=68uM21 U2/NAND2C_6/Out2 U2/NAND2C_6/Out1 Vdd Vdd PMOS L=2u W=28u AD=148p


M22 Vdd Cin U2/NAND2C_5/Out1 Vdd PMOS L=2u W=28u AD=84p PD=34u AS=84pPS=34u


PD=34u AS=144p PS=68uM24 U2/NAND2C_5/Out2 U2/NAND2C_5/Out1 Vdd Vdd PMOS L=2u W=28u AD=148p


PS=30uM26 16 U2/NAND2C_5/A U2/NAND2C_6/Out1 Gnd NMOS L=2u W=28u AD=28p



M28 Gnd Cin 15 Gnd NMOS L=2u W=28u AD=122p PD=47u AS=28p PS=30u

M29 15 U2/NAND2C_5/A U2/NAND2C_5/Out1 Gnd NMOS L=2u W=28u AD=28pPD=30u AS=148p PS=68u


PD=68u AS=122p PS=47uM31 Vdd U3/NAND2C_3/Out1 U2/NAND2C_5/A Vdd PMOS L=2u W=28u AD=84pPD=34u AS=84p PS=34u

M32 U2/NAND2C_5/A U3/NAND2C_2/Out1 Vdd Vdd PMOS L=2u W=28u AD=84p

PD=34u AS=144p PS=68uM33 U3/NAND2C_4/Out2 U2/NAND2C_5/A Vdd Vdd PMOS L=2u W=28u AD=148p


M34 Vdd B U3/NAND2C_3/Out1 Vdd PMOS L=2u W=28u AD=84p PD=34u AS=84pM35 U3/NAND2C_3/Out1 U2/NAND2C_9/A Vdd Vdd PMOS L=2u W=28u AD=84p M36

U3/NAND2C_3/Out2 U3/NAND2C_3/Out1 Vdd Vdd PMOS L=2u W=28u M37 Gnd

U3/NAND2C_3/Out1 21 Gnd NMOS L=2u W=28u AD=122p PD=47u AS=28p

M38 21 U3/NAND2C_2/Out1 U2/NAND2C_5/A Gnd NMOS L=2u W=28u AD=28pPD=30u AS=148p PS=68u

M39 U3/NAND2C_4/Out2 U2/NAND2C_5/A Gnd Gnd NMOS L=2u W=28u AD=148p

PD=68u AS=122p PS=47uM40 Gnd B 20 Gnd NMOS L=2u W=28u AD=122p PD=47u AS=28p PS=30u

M41 20 U2/NAND2C_9/A U3/NAND2C_3/Out1 Gnd NMOS L=2u W=28u AD=28p



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M43 Vdd U2/NAND2C_9/A U3/NAND2C_2/Out1 Vdd PMOS L=2u W=28u AD=84p

PD=34u AS=84p PS=34uM44 U3/NAND2C_2/Out1 A Vdd Vdd PMOS L=2u W=28u AD=84p PD=34u AS=144p

PS=68u

M45 U3/NAND2C_2/Out2 U3/NAND2C_2/Out1 Vdd Vdd PMOS L=2u W=28u AD=148p

PD=68u AS=84p PS=34uM46 Vdd B U2/NAND2C_9/A Vdd PMOS L=2u W=28u AD=84p PD=34u AS=84p

PS=34u

M47 U2/NAND2C_9/A A Vdd Vdd PMOS L=2u W=28u AD=84p PD=34u AS=144pPS=68u


PD=68u AS=84p PS=34uM49 Gnd U2/NAND2C_9/A 32 Gnd NMOS L=2u W=28u AD=122p PD=47u AS=28p

PS=30u

M50 32 A U3/NAND2C_2/Out1 Gnd NMOS L=2u W=28u AD=28p PD=30u AS=148pPS=68u


M52 Gnd B 31 Gnd NMOS L=2u W=28u AD=122p PD=47u AS=28p PS=30uM53 31 A U2/NAND2C_9/A Gnd NMOS L=2u W=28u AD=28p PD=30u AS=148p M54

U3/NAND2C_1/Out2 U2/NAND2C_9/A Gnd Gnd NMOS L=2u W=28u AD=148p PD=68u

AS=122p PS=47u* Total Nodes: 32

* Total Elements: 54

* Total Number of Shorted Elements not written to the SPICE file: 18* Output Generation Elapsed Time: 0.000 sec

* Total Extract Elapsed Time: 2.422 sec

.END

Result:

The Full Adder is constructed in Tanner EDA v13.1, the spice code is generated and

wave forms are verified


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Exp No: 5

D - FLIP FLOP

Aim:

a) To construct the D-Flip flop in Tanner EDA v13.1 and to do the Transient

Analysis.


Tools used:


2. Schematic-Edit

3. Layout -Edit

4. Wave- Edit

5. Tanner Spice

Procedure:





5.Instance the devices by using appropriate library files.





49/150



Schematic Diagram:

Fig : D - Flip Flop Schematic


50/150



Tanner Spice Code:


* Export time: Fri Apr 23 10:38:02 2010* Design: Prasad1

* Cell: Cell1

* View: view0* Export as: top-level cell* Export mode: hierarchical


* Exclude .end: no* Expand paths: yes

* Wrap lines: no

* Root path: C:\Documents and Settings\Administrator\Desktop\Prasad1* Exclude global pins: no


********* Simulation Settings - General section *********.lib "C:\Documents and Settings\Administrator\My Documents\Tanner EDA\Tanner Tools


*************** Subcircuits *****************

.subckt NAND2C A B Out1 Out2 Gnd Vdd

*-------- Devices: SPICE.ORDER < 0 --------* Design: LogicGates / Cell: NAND2C / View: Main / Page:




* Date: 6/14/2007 1:47:11 AM* Revision: 2


MN1 Out1 A 1 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u

MN2 1 B Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8uMN3 Out2 Out1 Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u

MP1 Out1 A Vdd Vdd PMOS W=2.5u L=250n M=2 AS=1.5625p PS=3.75u AD=2.25p

PD=6.8uMP2 Out1 B Vdd Vdd PMOS W=2.5u L=250n M=2 AS=1.5625p PS=3.75u AD=2.25p

PD=6.8u

MP3 Out2 Out1 Vdd Vdd PMOS W=2.5u L=250n M=2 AS=1.5625p PS=3.75u AD=2.25pPD=6.8u.ends


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XNAND2C_1 D Clk N_5 N_8 Gnd Vdd NAND2C

XNAND2C_2 Clk N_1 N_3 N_7 Gnd Vdd NAND2C

XNAND2C_3 N_5 QBar Q N_6 Gnd Vdd NAND2CXNAND2C_4 Q N_3 QBar N_4 Gnd Vdd NAND2C

XNAND2C_5 D D N_1 N_2 Gnd Vdd NAND2C

*-------- Devices: SPICE.ORDER > 0 --------VVoltageSource_3 Vdd Gnd DC 5

VVoltageSource_2 Clk Gnd PULSE(0 5 0 5n 5n 95n 200n)

VVoltageSource_1 D Gnd BIT({0100101111} ).PRINT TRAN V(D)

.PRINT TRAN V(Clk)

.PRINT TRAN V(Q)

.PRINT TRAN V(QBar)


.tran 350ns 500ns

.dc lin source VVoltageSource_2 0 5 0.5

.print dc v(Q,Gnd)


.end


52/150



Output responses:

Fig (b): D-Flip flop waveforms


53/150



Layout Diagram:

Layout Net list:


54/150




* TDB File: Layout1



.include lights.md

* NODE NAME ALIASES


* 3 = U1/NAND2C_3/Out2 (10 , 54)

* 6 = q (100 , 12.5)* 6 = U1/NAND2C_3/Out1 (2 , 52)

* 6 = U1/NAND2C_4/A (20 , 70)

* 7 = Vdd (-101 , 4)

* 7 = U1/NAND2C_1/Vdd (-51 , 86)* 7 = U1/NAND2C_2/Vdd (-17 , 86)

* 7 = U1/NAND2C_3/Vdd (-17 , 86)

* 7 = U1/NAND2C_4/Vdd (51 , 86)* 7 = U1/NAND2C_5/Vdd (85 , 86)

* 8 = d (-101 , 106.5)

* 8 = U1/NAND2C_1/A (-82 , 70)* 8 = U1/NAND2C_5/A (54 , 70)

* 8 = U1/NAND2C_5/B (62 , 63)

* 9 = U1/NAND2C_1/Out1 (-66 , 52)

* 9 = U1/NAND2C_3/A (-14 , 70)

* 10 = U1/NAND2C_2/Out1 (-32 , 52)* 10 = U1/NAND2C_4/B (28 , 63)

* 11 = U1/NAND2C_2/B (-40 , 63)* 11 = U1/NAND2C_5/Out1 (70 , 52)

* 12 = clk (-101 , 4.5)

* 12 = U1/NAND2C_1/B (-74 , 63)* 12 = U1/NAND2C_2/A (-48 , 70)

* 13 = U1/NAND2C_2/Out2 (-24 , 54)

* 14 = U1/NAND2C_1/Out2 (-58 , 54)* 17 = Gnd (92 , 4)

* 17 = U1/NAND2C_1/Gnd (-51 , 28)

* 17 = U1/NAND2C_2/Gnd (-17 , 28)* 17 = U1/NAND2C_3/Gnd (-17 , 28)* 17 = U1/NAND2C_4/Gnd (51 , 28)

* 17 = U1/NAND2C_5/Gnd (85 , 28)

* 18 = qbar (100 , 98.5)* 18 = U1/NAND2C_3/B (-6 , 63)

* 18 = U1/NAND2C_4/Out1 (36 , 52)


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M1 Vdd d U1/NAND2C_2/B Vdd PMOS L=2u W=28u AD=84p PD=34u AS=84p PS=34u

M2 U1/NAND2C_2/B d Vdd Vdd PMOS L=2u W=28u AD=84p PD=34u AS=144p PS=68u

M3 U1/NAND2C_5/Out2 U1/NAND2C_2/B Vdd Vdd PMOS L=2u W=28u AD=148pPD=68u AS=84p PS=34u

M4 Vdd U1/NAND2C_2/Out1 qbar Vdd PMOS L=2u W=28u AD=84p PD=34u AS=84p

PS=34u

M5 qbar q Vdd Vdd PMOS L=2u W=28u AD=84p PD=34u AS=144p PS=68uM6 U1/NAND2C_4/Out2 qbar Vdd Vdd PMOS L=2u W=28u AD=148p PD=68u AS=84p

PS=34u

M7 Vdd qbar q Vdd PMOS L=2u W=28u AD=84p PD=34u AS=84p PS=34uM8 U1/NAND2C_3/Out2 q Vdd Vdd PMOS L=2u W=28u AD=148p PD=68u AS=84p

PS=34u

M9 Gnd d 5 Gnd NMOS L=2u W=28u AD=122p PD=47u AS=28p PS=30uM10 5 d U1/NAND2C_2/B Gnd NMOS L=2u W=28u AD=28p PD=30u AS=148p PS=68u

M11 U1/NAND2C_5/Out2 U1/NAND2C_2/B Gnd Gnd NMOS L=2u W=28u AD=148p


PS=30uM13 4 q qbar Gnd NMOS L=2u W=28u AD=28p PD=30u AS=148p PS=68u

M14 U1/NAND2C_4/Out2 qbar Gnd Gnd NMOS L=2u W=28u AD=148p PD=68uAS=122p PS=47u

M15 U1/NAND2C_3/Out2 q Gnd Gnd NMOS L=2u W=28u AD=148p PD=68u AS=122p

PS=47uM16 q U1/NAND2C_1/Out1 Vdd Vdd PMOS L=2u W=28u AD=84p PD=34u AS=144p

PS=68u

M17 Vdd U1/NAND2C_2/B U1/NAND2C_2/Out1 Vdd PMOS L=2u W=28u AD=84pPD=34u AS=84p PS=34u

M18 U1/NAND2C_2/Out1 clk Vdd Vdd PMOS L=2u W=28u AD=84p PD=34u AS=144p

PS=68uM19 U1/NAND2C_2/Out2 U1/NAND2C_2/Out1 Vdd Vdd PMOS L=2u W=28u AD=148pPD=68u AS=84p PS=34u

M20 Vdd clk U1/NAND2C_1/Out1 Vdd PMOS L=2u W=28u AD=84p PD=34u AS=84p

PS=34uM21 U1/NAND2C_1/Out1 d Vdd Vdd PMOS L=2u W=28u AD=84p PD=34u AS=144p

PS=68u


M23 Gnd qbar 19 Gnd NMOS L=2u W=28u AD=122p PD=47u AS=28p PS=30u

M24 19 U1/NAND2C_1/Out1 q Gnd NMOS L=2u W=28u AD=28p PD=30u AS=148p

PS=68uM25 Gnd U1/NAND2C_2/B 16 Gnd NMOS L=2u W=28u AD=122p PD=47u AS=28p

PS=30u

M26 16 clk U1/NAND2C_2/Out1 Gnd NMOS L=2u W=28u AD=28p PD=30u AS=148pPS=68u




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M28 Gnd clk 15 Gnd NMOS L=2u W=28u AD=122p PD=47u AS=28p PS=30uM29 15 d U1/NAND2C_1/Out1 Gnd NMOS L=2u W=28u AD=28p PD=30u AS=148p

PS=68u


* Total Nodes: 19

* Total Elements: 30* Total Number of Shorted Elements not written to the SPICE file: 10

* Output Generation Elapsed Time: 0.000 sec

* Total Extract Elapsed Time: 1.875 sec.END

Result:The D-Flip flop is constructed in Tanner EDA v13.1, the spice code is generated and

waveforms are verified.


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Exp No: 6

CURRENT MIRROR

Aim:

a) To construct the Current Mirror in Tanner EDA v13.1 and to do the

Voltage Analysis.

b) To analyze the response with appropriate wave forms. And to verify the Spice

code of the designed circuit.

Tools used:


2. Schematic-Edit

3. Layout -Edit

4. Wave- Edit

5. Tanner Spice

Procedure:










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Schematic Diagram:

Fig (a): Current Mirror Schematic

Tanner Spice Code:


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* SPICE export by: SEDIT 13.00* Export time: Fri Jun 11 12:15:48 2010

* Design: msl

* Cell: Cell8

* View: view0

* Export as: top-level cell* Export mode: hierarchical


* Expand paths: yes

* Wrap lines: no* Root path: C:\Documents and Settings\user11\Desktop\msl

* Exclude global pins: no



.lib "C:\Documents and Settings\user11\My Documents\Tanner EDA\Tanner Toolsv13.0\Libraries\Models\Generic_025.lib " TT



MNMOS_2 Out N_2 Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p

PD=6.8uMNMOS_1 N_2 N_2 Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p

PD=6.8u

MNMOS_3 Vdd Vdd N_2 Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p

PD=6.8uMNMOS_4 In Vdd Out Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p

PD=6.8u

VVoltageSource_1 Vdd Gnd DC 5VVoltageSource_2 In Gnd SIN(2.5 500m 500k 0 0 0)

.PRINT TRAN V(Out)

.PRINT TRAN V(In)


*.tran 5ns 500ns

.dc lin source vvoltagesource_2 0 5 1

.print dc v(n_2,gnd)


.end

Output responses:


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NMOS_3_S

NMOS_1_S

Fig (b): Current Mirror Waveforms

Result:

The Current Mirror is constructed in Tanner EDA v13.1, the spice code is

generated and wave forms are verified


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Exp No: 7

DIFFERENTIAL AMPLIFIER

Aim:

a) To construct the differential amplifier in Tanner EDA v13.1 and to do the

voltage analysis.

b) To analyze the response with appropriate wave forms. And to verify the Spice

code of the designed circuit.

Tools used:


2. Schematic-Edit

3. Layout -Edit

4. Wave- Edit

5. Tanner Spice

Procedure:










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Schematic Diagram:

Fig(a): Differential Amplifier Schematic


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Tanner Spice Code:

********* Simulation Settings - General section *********.lib "C:\Documents and Settings\user11\My Documents\Tanner EDA\Tanner Tools

v13.0\Libraries\Models\Generic_025.lib " TT


*-------- Devices: SPICE.ORDER > 0 --------RResistor_1 Vdd N_5 R=50

RResistor_2 Vdd N_7 R=50


PD=6.8uMNMOS_2 N_7 N_1 N_3 N_6 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p

PD=6.8u

VVoltageSource_2 Vdd Gnd DC 5VVoltageSource_3 N_2 Gnd PULSE(0 5 0 5n 5n 95n 200n)

VVoltageSource_5 Gnd pos_PortNotFound_0 PULSE(0 5 0 5n 5n 95n 200n)

ICurrentSource_1 N_3 Gnd DC 5u.PRINT TRAN V(N_2)

.PRINT TRAN V(N_7)

.PRINT TRAN V(N_1)

.PRINT TRAN V(N_5)


*.tran 5ns 500ns.dc lin source vvoltagesource_3 -3 3 1

.print dc i(mnmos_2,n_7) i(mnmos_1,n_5)


.end


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Output responses:

Fig (b): Differential Amplifier Waveforms

Result:

The differential amplifier is constructed in Tanner EDA v13.1, the spice code

is generated and wave forms are verified.


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Exp No: 8

OPERATIONAL AMPLIFIER

Aim:

a) To construct the Operational Amplifier in Tanner EDA v13.1 and to do the

AC analysis.


Tools used:


2. Schematic-Edit

3. Layout -Edit

4. Wave- Edit

5. Tanner Spice

Procedure:



3.Go to Cell

New View4. Add libraries file to the New Cell.






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Schematic Diagram:

Fig (a): Operational Amplifier Schematic


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Tanner Spice Code:


.lib "C:\Documents and Settings\user11\My Documents\Tanner EDA\Tanner Toolsv13.0\Libraries\Models\Generic_025.lib " TT



CCapacitor_1 N_3 Out 1pCCapacitor_2 Out Gnd 1p


PD=6.8uMNMOS_2 N_3 N_5 N_11 N_4 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p

PD=6.8u

MNMOS_3 N_11 N_10 Gnd N_7 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p

PD=6.8uMNMOS_4 N_9 N_10 Gnd N_8 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p

PD=6.8u

MPMOS_1 N_3 N_2 Vdd N_12 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25pPD=6.8u

MPMOS_2 N_2 N_2 Vdd N_13 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p

PD=6.8uMPMOS_3 N_9 N_3 Vdd N_14 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25pPD=6.8u

VVoltageSource_2 N_6 Gnd DC 5

VVoltageSource_3 N_10 Gnd DC 5VVoltageSource_4 N_5 N_6 DC 0 AC 1 0

********* Simulation Settings - Analysis section **********.tran 5ns 500ns

.ac lin 10 0 10

.print ac vm(out,gnd) vp(out,gnd)


.end


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Output responses:

VP(OUT)

Vdb(OUT)

V(OUT)

Fig (b): Operational Amplifier Waveforms

Result:

The Operational Amplifier is constructed in Tanner EDA v13.1, the spice

code is generated and wave forms are verified.


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Exp No: 09

TRANS CONDUCTANCE AMPLIFIER

Aim:

a) To construct the Trans Conductance Amplifier in Tanner EDA v13.1 and todo the DC analysis.


Tools used:


2. Schematic-Edit

3. Layout -Edit

4. Wave- Edit

5. Tanner Spice

Procedure:










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Schematic Diagram:

Fig (a): Trans Conductance Amplifier Schematic


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Tanner Spice Code:


*-------- Devices: SPICE.ORDER > 0 --------MNMOS_1 N_1 N_2 N_3 Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p

PD=6.8uMNMOS_2 Out N_4 N_3 Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p

PD=6.8u

MNMOS_3 N_3 N_5 Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25pPD=6.8u

MPMOS_1 N_1 N_1 Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p

PD=6.8u

MPMOS_2 Out N_1 Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25pPD=6.8u

VVoltageSource_1 Vdd Gnd DC 5VVoltageSource_2 N_2 Gnd DC 2VVoltageSource_3 N_5 Gnd DC 700m

VVoltageSource_4 Out Gnd DC 2.5

VVoltageSource_5 N_4 N_2 DC 0


.dc lin source VVOLTAGESOURCE_5 -1 1 0.01

.print dc id(MNMOS_1) id(MNMOS_2)

.print dc i(vvoltagesource_4,out)

*.tran 350ns 500ns


.end


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Output responses:

i(VPMOS_1)

i1(VNMOS_3)

i1(VNMOS_2)

Fig (b) Trans Conductance Amplifier Waveforms

Result:

The Trans Conductance Amplifier is constructed in Tanner EDA v13.1, the spice

code is generated and wave forms are verified.


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Setup Guide for Taneer Tools V13.0

1. Extract the Taneer Tools

Right Click Extract Here

2. Go to Taneer Tools_V13_LND

3. Click Setup

4. Setup will Continue without any Modifications

5. Click Finish

6. Select only when License manager shows the message select local License

7. Go on to Next to Continue When the Message Taneer Tools are successfully installed

8. Go to Taneer Tools_V13_LND (where is been Extracted)

9. Go to Legend Folder Copy the Following

TannerTools_13_Calculator

TannerTools_13_Corrector

10. Go to Below Steps C:Program Files:Taneer Eda:

11. Paste the Selected Items

12. Double Click on TannerTools_13_Corrector

13. After receiving message Press any Key

14. Go to Below Steps: C:Program Files:Taneer Eda:

15. Double Click on TannerTools_13_Calculator

16. Go to Start: Programs: Taneer Eda: Utitlities: Computer Id:Copy the Ethernet

Value(not available copy IP Address)

17. Write down the Copied value into TannerTools_13_Calculator Editor

18. After receiving the License (Lservrc) file press any key

19. Go to C:Program Files:Taneer Eda: copy the Lservrc file

20. Paste the Lservrc file in following Paths

1) C:Program Files:Taneer Eda: Taneer Tolls V13.0:

2) C:Program Files:Taneer Eda: Taneer Tolls V13.0:px:

WIN 32.2-I686:bin:

3) C:Program Files:Taneer Eda: Taneer Tolls V13.0: VerilogA: Vacomp:

bin:

21. Close all opened Files

22. Click on L-Edit shortcut on Desktop


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23. Click Setup on Dailog Box

24. Continue to Next steps without any Modifications

25. Click finish button

26. Setup successfully Installed


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INSTRUCTION MANUAL

DESIGN AND SIMULATION OF INVERTER WITH

TANNER TOOL

Under The Guidance

of

Dr. Manisha Pattanaik

Designed by

Basanta BhowmikJayveer Singh Bhadauriya


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Contents:

Schematic design..03-19

Pre layout simulation..20-26

Layout design.27-50

Design rule check(DRC).51-53

Extraction54-56

Layout Vs schematic(LVS).57-62

Post layout simulation63-65

Generation of GDS II file(MASK)..66-72

Appendix .73-76

MOSIS Design rule .73

Extracted file/Layout Netlist74

GDSII Export file.....................75

GDSII Import file..76


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Schematic design of Inverter

What is schematic Design: There are many phases or progressions of a design. A common term you will

hear when working with a Designer is Schematic Design. This phase is early in the design process.

Schematic Design establishes the general scope, conceptual ideas, the scale and relationship of the

various program elements. The primary objective of schematic design is to arrive at a clearly defined

feasible concept based on the most promising design solut ions.

Opening S-edit platform:

First of all double click on the icon of s-edit on the desktop

or

Go to the start menu >>All Programs >>Tanner EDA >>Tanner Tool v 13.0 >> S-Edit v 13.0


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A new window will open:


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Go to >>file >> New >> New Design

Select New Design


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One dialog box will appear

Design Name : Give the name your design as you wish

Create a Folder : Give the path where you want to save the S-Edit Files.

Then Click on OK


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Now to add libraries in your work click on Add ,left on the library window.

Give the path where Libraries are stored . As for example

C:\Documents and Settings\Bhowmik.IIIT-3AC288AD0A\My Documents\Tanner EDA\Tanner

Tools v13.0\Libraries\All\ All.tanner


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Now to create new cell

Go to cell menu >> New view --

Select New view


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The new cell will appear like below:Design = your design name

Cell = cell no. ( cell no you can change but your design name inv will be same for different cell.

Design name should be changed only when you are going to design another circuit)

View type = schematic

Interface name = by default

View name = by default

Then press OK.


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Then a cell wil l be appeared where we can draw the schematic of any circuit .

In the black window you have seen some white bubble arranged in specific order. This is called

grid. You can change grid distance by clicking on black screen and then scroll the mouse.

If you want your screen big enough for design space , then you can close the Find& command

window. You can again bring these window from viewmenu bar.


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To make any circuit schematic .

for example inverter

a) Go to >>libraries & click on device then all device will be open.


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b) Select any device

e.g. :- NMOS Device, then click on , instance

(then the dailog box instance cell will appear.)


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In instance cell

You can change the values of various device parameters according to your

requirements.

Go to properties >> change the parameter values as your requirement.

Now before clicking DONE you have to DRAG the selected device into the celland drop it where you want it to FIX .

Then click DONE or pressESC.


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Similarly you can DRAG & DROP any device into the cell for draw your schematic circuit.

For inverter we need another Pmos.


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Now connect two device with wire.

Go to tool bar and select wire.


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Similarly to give input & output port in the circuit , select input port that shown by red ellipse.


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Now you can give Port name as you wish in the dailog box.

Then click OK

Similarly give Output Port name.

NOTE: you can rotate the port (short cut key R).


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Now, after completed these steps, you should give the supply (VDD) & ground (GND).

For that Go to liberaries >> MISC >>Select VDD or GND


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Now you have to create a source of VDD. For that go to libraries >>spice_element >> and then

select voltage source of type DC . you can give any value in vdd .lets take vdd =5v.

By doing all the above steps you have completed schematic of Inverter


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Pre layout simulation

After schematic design you have to check whether your design match with the

specification required or not . Thats why you need to simulate the design which

is called Pre layout simulation.

For simulation go to>> tools>> T-spice>> ok


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A T-spice window will open.

Then click on the bar shown by red ellipse


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A T-spice command Tool dialog box will open as shown beow.

On the T-spice command you can see in the left hand side

Analysis,

Current source

FilesInitialization,

Output

Settings

Table

Voltage source

Optimization


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Lets start doing transient analysis of Inverter.

Step 1 : You have to include TSMC 0.18 m Technology file .

For thatGo to >> T-spice command tool >> Files >> Include >> browse TSMC .18m files

>> Insert command.

C:\Documents and Settings\Bhowmik.IIIT-3AC288AD0A\Desktop\TSMC

0.18um\MODEL_0.18.md


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File is included shown by highlight.

Step2 : Then to give Input

T-spice command tool >> Voltage source >> select type of input you want to give(lets

take bit) >> Insert command

Step 3: Analysis

T-spice command tool >> Analysis >> select type of analysis you want to give(lets take

transient) >> Insert command

step 4: Output

T-spice command tool >> Output >> which output you want to see >> Insert

Command


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The total spice netlist will come like this.

Now save it .

Then Run by clicking red ellipse shown on left above corner.


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Output of Pre layout simulation of Inverter


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Layout Design

What is Layout Design:A layout-design of an IC refers essentially to the 3-dimensional character of the

elements and interconnections of an IC. There is a continuing need for the creation of new layout-

designs which reduce the dimensions of existing integrated circuits and simultaneously increase their

functions.

Procedure of Layout Design in 0.18m CMOS Technology(MOSIS>>

Mamin08)

Opening L-edit platform:

First of all double click on the icon of L-edit on the desktop

or

Go to the start menu >>All Programs >>Tanner EDA >>Tanner Tool v 13.0 >> L-Edit v 13.0


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A window will come like below.

We will start the layout of Inverter with

NMOS w= 1.5 m L =2.75 mPMOS w= 1.5 m L= 3.50 m


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For inverter layout

Go to f ile>> new.>> select

A dialog box will come as shown in fig

Select layout and then press ok.


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A new layout window will open


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Carefully observe the Red ellipse which will be frequently used for your Design.


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Before starting layout design you have to set the Technology you want to used.

In TSMC .18 m Technology, available Technology are

CharterdChina_hj

Generic0_25 m

Mosis

Orbit

So to set the Technology

Go to >> File >> Replace setup and then select


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A dialog box will come.

Click on browse >> Tanner EDA >> Tanner Tools v13.0 >>L-edit and LVS >> TECH >> Mosis >>

mamin08 or mamin12 or or>> press ok

After pressing ok ,A small dialog box will come and it tells you ,Technology are going to be

changes. In that stage press ok.

Lets take in the above set up you set Mosis ->Mamin08 Technology. That means you have to

follow Mosis design rule in your entire design.

Mosis design rule are given in appendix.


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Now lets recheck your technology set up.

For that

Go to >> set up >> Design >> then select

In the Set up design layout2dialog box you have seen there are many technology units.you

can choose any one of them for your design. I have choosen Lambda rule for convenience. Also

for Technology to micron mapping I have taken 1 lambda=0.5 micron . You can choose your

own for better understandig and drawing the design.


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In the same way select grid

For design convenience and properly maintain the DRC , I have taken

Major diplayed grid=10 lambdaMinor diplayed grid=1 lambda (You put according to your calculation)

Like that many other parameter you can change thats depends upto you.

Atlast press ok .

Now you properly create the environment for design.


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You have two option for any Design .Lets take example of Inverter

First: For inverter design first of all you have to create a PMOS and a NMOS in the same

window.

Or

Second:You can bring a PMOS and NMOS from the Library ,which is already available.For that Go to Cell >> Instance >> browse the Technology what you are using (e.g

mamin08) >> press ok >> a series of devices which are available in the library will come >>

seect