Mixed PLB and Interconnect BIST for FPGAs Without Fault-Free

Assumptions

Vishal Suthar and Shantanu Dutt

Electrical and Computer Engineering University of Illinois at Chicago.

OutlineOutline

The problem of fault-free assumptions & other The problem of fault-free assumptions & other storiesstoriesIterative Bootstrapping (IB) – A general solutionIterative Bootstrapping (IB) – A general solutionMixed BIST: Combining PLB & interconnect Mixed BIST: Combining PLB & interconnect testing with IB—no fault-free assumptionstesting with IB—no fault-free assumptions– Recent work in PLB BIST (HD-BIST)Recent work in PLB BIST (HD-BIST)– Recent work in interconnect BIST (I-BIST)Recent work in interconnect BIST (I-BIST)

Simulation ResultsSimulation ResultsConclusionsConclusions

Built-In Self-Test in FPGAs—Basic Concepts

TPG - Test Pattern GeneratorORA - Output Response

Analyser CUT - Cells Under Test

Comparison based BIST:

WUT - Wires Under Test

WUT

WUT

• In each session diff. PLBs act as CUTs, TPG and ORA.

TPG CUT

CUT ORA

Pass / fail

WUT

WUTGross syndrome (GS):

The gross syndrome of a session is the overall fail/pass (X/√ ) result of a session. Match in all CUT outputs => ORA output = 0 => GS = pass (√ )Else ORA output = 1 => GS = fail (X)

(V. Verma, S. Dutt, V. Suthar, DAC 2004)BISTer-1:

ORA CUT

TPG CUT

CUT CUT

ORA TPG

TPG ORA

CUT CUT

A

B C

D AA

BB CC

D DCUT TPG

CUT ORA

A D

B C

(S1) (S2) (S3) (S4)

Theorem: BISTer-1 is 1/4 diagnosable

405060708090

100

1 2 5 7 10 15 20 25 30 35 40

Fault density (%)

Faul

t cov

erag

e (%

)

BISTer-1 BISTer-0

30405060708090

100

8.8 (1) 16.9 (2) 26.6 (3)

Fault density (cluster density) (%)

Faul

t cov

erag

e (%

)

BISTer-1 BISTer-0

(a) Random faults (b) Clustered faults

Drawbacks in deterministic BIST techniques

Fallacy of Fault-Free Assumptions

1. Limited / Incorrect diagnosability in presence of multiple faults

in the BISTer area. Unrealistic assumptions: a) The test circuit (TPG & ORA) is fault-free.

b) No fault masking; c) no more than 1-2 faults in BISTer area

TPGCUT

CUT

ORAGS= pass(non-det.)

BISTer

2. Absence of BIST techniques that can diagnose faults present in PLBs as well as interconnects. Unrealistic assumption: while testing PLBs the interconnects used in the BISTer area are fault-free and similarly, while testing interconnects the PLBs forming the test circuit are fault-free.

GS= fail(false +ve)

Iterative Bootstrapping (IB)

Test circuit with f-free prob. = Use redundancy (e.g. TMR) to increase

Ti q i

Test PLBs conf. for ORA and TPG functions & reqd. interconnects using Ti

q i

T Ti i 1

Ti1

q qi i 1

o/p = Test circuit with f-free prob.

q qi thres 1

Test circuit

No

Yes

Final test circuit

Need: An ability to detect and diagnose faults in presence of multiple faults and/or clustered fault patterns in both PLBs and interconnects, with high probability.Solution: Iterative bootstrapping for obtaining fault-free test circuits (w/ fault-free PLBs & interconnects)

Iterative Bootstrapping (IB)• Does it always work?• If not, are there conditions under which it works?• Are these conditions realistic?

• Consider TMR as the redundant circuit: p = prob. of a faulty PLB,q1 (q2) = prob of fault-free TMR TPG/ORA (1 PLB impl.) in 1st (2nd) iter of IB

•

• Theorem: If prob. of correct oper. f(q) [q=fault-free prob. of component] is monotonically non-decreasing, and f(q0=1-p) >= 1-p, then IB provides us w/ s sequence of redundant test circuits with monotonically non-decreasing fault-free probabilities q1, q2, ….., qk.

NoYes

Yes

Mixed PLB and Interconnect BIST

• Two high-diagnosability BIST techniques used.1. HD-BIST (High-Diagnosability BIST) – PLB testing [GLSVLSI’05]2. I-BIST (Interconnect BIST) – Interconnect testing [DATE’06]

• Reqmt for reliable mixed testing w/ faults in PLBs & interconnects:

PLB testing

Interconnect testing

F-free interconnect

F-free TPGs/ORAs

requires

requires

obtained fromobtained from

• A classic chicken-&-egg problem (which comes first).

• Solution: Break the cycle via Iterative Bootstrapping

Mixed PLB and Interconnect BIST (contd)

• Solution: Break the cycle via IB and then interleave the various stages of HD-BIST and I-BIST so that fault-free components (w/ high prob.) are available to test the next stage.

Our approach:First phase – IB w/ TMR

Phase

test ckt. rqd. for phase

test ckt. rqd. for phase

Pi

Pi

Pi1

Non TMR’ed

Fault state unknown

Mixed-BIST: PLB BIST StagesMixed-BIST: PLB BIST Stages

TPG shuffling scheme(instead of TMR) to reduce test vector skipping probability

Bootstrapping phases (2)

o/p = faulty PLBs

Global testing – Fault detection & gross diagnosis phase

Detailed testing: Adaptive diagnosis phase

o/p = suspect PLBs & fault-free sticks

o/p = fault-freeORA / stick (if exists)

END

START

TPGD

CUTC

CUTB

TPGA

TPGF

ORAE

Testee Stick

Tester Stick

TPGD

TPGC

CUTB

CUTA

TPGF

ORAE

TPGD

CUTC

TPGB

CUTA

TPGF

ORAE

HD-BIST [Suthar & Dutt, GLSVLSI’05]

Theorem: P p Pshuffled tpg

Pshu ffled = prob. of shuffled TPG skipping a test vector.

Ptpg = prob. of normal TPG skipping a test vector.

p = prob. of a PLB being faulty.

• HD-BISTer is compared with previous best online BIST techniques: STAR BISTer proposed by [M. Abramovici et. al., ITC’00] and BISTer-1 • HD_3 -> HD-BISTer with TPG shuffling HD_1 -> HD-BISTer without TPG shuffling.

FAULT COVERAGE:

40

50

60

70

80

90

100

1 2 5 7 10 15 20 25

HD_3

HD_1

BISTer-1

STAR

30

40

50

60

70

80

90

100

8.8 16.9 26.6

HD_3/1

BISTer-1

STAR

Fault density (%)

Fa

ult

co

ve

rag

e (

%)

Random faults Clustered faults

(1.0) (2.0) (3.0)

Cluster density (%)

Fa

ult

co

ve

rag

e (

%)

HD-BIST Experimental ResultsHD-BIST Experimental Results

Mixed-BIST: Interconnect BIST StagesMixed-BIST: Interconnect BIST Stages

I-BIST [Suthar & Dutt, DATE’06]

Approach:1. Global Testing: First isolate the

possible fault locations to a small set of interconnects in very few configurations -> Suspect Set

2. Detailed Testing: Then diagnose interconnects of suspect set for faults using divide-&-conquer and in the final iteration by comparison to known fault-free interconnects

1n2n3n 1l2l3l

),( 21 nnA

),( 32 nnA ),( 11 lnO

),( 22 lnOSpanning

SwitchStuck-closed

),( 21 llA

Test vector 2:Test vector 3:

0 1 00 1 01 0 11 0 1Test vector 1:

0 0 00 0 0

Global Testing (1/5 configs)

I-BIST: ResultsI-BIST: Results

Fault coverage (diagnosability) versus fault density

Theoretical Results:• TheoremTheorem: I-BIST has : I-BIST has 100% guaranteed 100% guaranteed fault detectabilityfault detectability in the presence of in the presence of multiple faults – multiple faults – a firsta first• I-BIST has the I-BIST has the fewest configurations—5—fewest configurations—5—per WUT-setper WUT-set in global testing in global testing• I-BIST has the I-BIST has the fewest # of test vectors—3—fewest # of test vectors—3—per WUT-setper WUT-set testing phase testing phase

Empirical Results:

Mixed-BIST– Summary of TechniquesMixed-BIST– Summary of Techniques

Our Mixed-BIST (M-BIST) approach attempts to Our Mixed-BIST (M-BIST) approach attempts to significantly reduce these negative effects viasignificantly reduce these negative effects via– a careful application of iterative bootstrappinga careful application of iterative bootstrapping– interleaving of various stages of I-BIST and HD-BISTinterleaving of various stages of I-BIST and HD-BIST

First phase – IB w/ TMR

Phase

Test ckt. rqd. for phase

Test ckt. rqd. for phase

Pi

Pi

Pi1

Non TMR’ed

PLB bootstrapping: detect {IO-FF sticks} using r ff tracks

Interconnect global testing: test {s tracks / (r < s < t)} using TMR

o/p = T-FF -> {ff tracks} non-T-FF -> {suspect tracks}

Interconnect detailed testingPLB fault detection and adaptive diagnosis

o/p = I-FF -> {ff interconnects} non-I-FF -> {faulty interconnects}

o/p = PLB-FF -> {ff PLBs} non-PLB-FF -> {faulty PLBs}

Non

TMR’

ed

r fault-free tracks found ?NO

YES

o/p = IO-FF and non-IO-FF sticks

Interconnect global testing: test {(t - s) tracks} using IO-FF set

PLB bootstrapping: detect {ff ORAs / stick} using T-FF set

o/p = ORA-FF -> {ff ORA PLBs}

TMR’ed

Mixed BIST: Combining & Interleaving IB, I-BIST & HD-BISTMixed BIST: Combining & Interleaving IB, I-BIST & HD-BIST

• Comparison of PLB and interconnect testing in M-BIST (without fault-free assumptions) v/s HD-BIST (with fault-free assumptions) & I-BIST (with fault-free assumptions)

Simulation Results – Fault CoverageSimulation Results – Fault Coverage

97.5

98

98.5

99

99.5

100

1 2 3 4 5 6 7 8 9 10Fault density (%)

Fault

Cov

erag

e (%

)

Without fault-free assumptions With fault-free assumptions

97.5

98

98.5

99

99.5

100

1 2 3 4 5 6 7 8 9 10Fault density (%)

Fault

cove

rage

(%)

Without fault-free assumptions With fault-free assumptions

Fault coverage – random faults

M-BIST v/s HD-BIST (w/ f-free assumptions) M-BIST v/s I-BIST (w/ f-free assumptions)

2 % difference1.5 % difference

False positive results – random faults

False positives – fault-free components incorrectly diagnosed as faulty. -- measured as a percentage of faults inserted.

Simulation Results – False PositivesSimulation Results – False Positives

0.005.00

10.0015.0020.0025.0030.0035.0040.0045.00

1 2 3 4 5 6 7 8 9 10

Fault density (%)

Fals

e po

sitiv

es (%

)

Without fault-free assumptionsWith fault-free assumptions

020406080

100120140160180200

1 2 3 4 5 6 7 8 9 10

Fault density (%)

Fals

e po

sitiv

es (%

)

Without fault-free assumptionsWith fault-free assumptions

40%200%

5 %0%

M-BIST v/s HD-BIST (w/ f-free assumptions) M-BIST v/s I-BIST (w/ f-free assumptions)

ConclusionsConclusionsGoal: Mixed PLB and Interconnect BIST that does not require any fault-free assumptions in order to:– improve diagnosability and reduce false positives– in the presence of in the presence of clustered and high density faultsclustered and high density faults in both PLBs in both PLBs

and interconnectsand interconnectsIntroduced the novel concept of general iterative bootstrapping for this purpose that can be used in different in different test and fault tolerance domainstest and fault tolerance domainsAnalyzed the Analyzed the mathematical conditions for improved mathematical conditions for improved diagnosisdiagnosis using iterative bootstrapping using iterative bootstrappingApplied iterative bootstrapping in novel ways (TMR, shuffled Applied iterative bootstrapping in novel ways (TMR, shuffled TPGs, TPGs w/o i/o faults) to develop a TPGs, TPGs w/o i/o faults) to develop a Mixed BISTer M-Mixed BISTer M-BIST sans fault-free assumptionsBIST sans fault-free assumptionsAchieved our aim of Achieved our aim of accurate PLB and interconnect accurate PLB and interconnect diagnosisdiagnosisFuture Work: Built-in controller for diagnosis and reconfiguration

THANK YOU

Built-In Self-Test in FPGAs—On-Line & Off-Line

CIRCUIT

ROTE (ROving TEster)

• Two column left spare for ROTE; one for fault reconfiguration• ROTE roves across the FPGA

SPAR

E C

OLU

MN

CIRCUIT CIRCUITSPA

RE

CO

LUM

N

TPG - Test Pattern GeneratorORA - Output Response

Analyser CUT - Cells Under Test

BISTer:

WUT - Wires Under Test

WUT

WUT

T C

C O

C T

O C

• In each session diff. PLBs act as CUTs, TPG and ORA.

TPG CUT

CUT ORA

Pass / fail

WUT

WUT

Mixed-BIST: Interconnect BIST Stages (contd)Mixed-BIST: Interconnect BIST Stages (contd)

1n2n 1l2lan2

bn2

al2

bl2

Global testing Detailed testing—Divide-&-Conquer

Switch stuck-closed

A

O O

O

O

O

TPG

ORA

Suspect interconnect

Fault-free interconnect

PLB bootstrapping: detect {ORAs, TPGs} using T-FF set

Interconnect global testing: detect {tracks} using TMR

o/p = T-FF -> {ff tracks} non-T-FF -> {suspect tracks}

o/p = ORA-FF -> {ff ORA + TPG PLBs}Interconnect detailed testing: diagnose {interconnects of non-T-FF}

using ORA-FF set.

o/p = I-FF -> {ff interconnects} non-I-FF -> {faulty interconnects}

PLB Fault detection: detect {suspect PLBs} using ORA-FF set and I-FF set.

o/p = PLB-FF -> {ff PLBs} non-PLB-FF -> {faulty PLBs}

PLB adaptive fault diagnosis: diagnose {faulty PLBs among suspect set}using ORA-FF set and I-FF set.

o/p = suspect set = {PLBs suspected of being faulty}

TMR’ed

No

n TM

R’e

d

M-BISTer (Mixed-BISTer):