MIS 6010: IT INFRASTRUCTURE ASSIGNMENT #3Given on: 27th March 2015 Due: 3rd April 2015

Lecturer: Dr. G. Chege (gchege@usiu.ac.ke;

Answer all four Questions.

Question 1In this question we examine how latencies of individual components of the datapath affect the clock cycle time of the entire datapath, and how these components are utilized by instructions. For three problems in this exercise, assume the following latencies for logic blocks in the datapath:

a) What is the clock cycle time if the only types of instructions we need to support are ALU instructions (ADD, AND, etc.)?

i) 200 + 90 + 20 + 90 + 20 = 420psii) 750 + 300 + 50 + 250 + 50 = 1400ps

b) What is the clock cycle time if we only have to support LW instructions?

i) 200 + 90 + 20 + 90 + 250 + 20 = 670psii) 750 + 300 + 50 + 250 + 500 + 50 = 1900ps

c) What is the clock cycle time if we must support ADD, BEQ, LW, and SW instructions?

In this question the answer applies as in b above. The critical path taken by the lw instruction is the longest as lw unlike store word will need to write the value retrieved from memory to the register. Store word on the other hand will only need to write to memory but not returning any values to register hence it is shorter by a Mux. The longest path for add and bne is shorter by D-Mem.

Question 2The Problems in Question 2 and Question 3 refer to the following instruction sequences:

a) Find all data dependences in each of the two instruction sequences (a) & (b).

Instruction Sequence

RAW WAR WAW

a) I1: ADD R1,R2,R1I2: LW R2,0(R1)I3: LW R1,4(R1)I4: OR R3,R1,R2

(R1) I1 to I2, I3(R2) I2 to I4(R1) I3 to I4

(R2) I1 to I2(R1) I1, I2 to I3

(R1) I1 to I3

b) I1: LW R1,0(R1)I2: AND R1,R1,R2I3: LW R2,0(R1)I4: LW R1,0(R3)

(R1) I1 to I2(R1) I2 to I3

(R1) I1 to I2(R2) I2 to I3(R1) I3 to I4

(R1) I1 to I2(R1) I2 to I4

b)Find all hazards in each of the instruction sequences (a) & (b) for a 5-stage pipelinewith and then without forwarding.

Only RAW dependences can become data hazards. With forwarding, only RAW dependences from a load to the very next instruction become hazards. Without forwarding, any RAW dependence from an instruction to one of thefollowing 3 instructions becomes a hazard:

Instruction Sequence

With Forwarding Without Forwarding

a) I1: ADD R1,R2,R1I2: LW R2,0(R1)I3: LW R1,4(R1)I4: OR R3,R1,R2

(R1) I3 to I4 (R1) I1 to I2, I3(R2) I2 to I4(R1) I3 to I4

b) I1: LW R1,0(R1)I2: AND R1,R1,R2I3: LW R2,0(R1)I4: LW R1,0(R3)

(R1) I1 to I2 (R1) I1 to I2(R1) I2 to I3

Question 3Assume that, before any of the two sequences in Question 2 above is executed, all values in data memory are zeroes and that registers R0 through R3 have the following initial values:

a) Which value is the first one to be forwarded and what is the value it overrides?

Instruction Sequence RAWI1: ADD R1,R2,R1I2: LW R2,0(R1)I3: LW R1,4(R1)I4: OR R3,R1,R2

(R1) I1 to I2 (30 overrides –1)

b) If we assume forwarding will be implemented when we design the hazard detection unit, but then we forget to actually implement forwarding, what are the final register values after this instruction sequence?

A register modification becomes “visible” to the EX stage of the following instructions only two cycles after the instruction that produces the register value leaves the EX stage. Our forwarding-assuming hazard detection unit only adds a one-cycle stall if the instruction that immediately follows a load is dependent on the load. We have:

Instruction sequencewith forwarding stalls

Execution withoutforwarding

Values after execution

I1: ADD R1,R2,R1I2: LW R2,0(R1)I3: LW R1,4(R1)StallI4: OR R3,R1,R2

R1 = 30 (Stall and after)R2 = 0 (I4 and after)R1 = 0 (after I4)R3 = 30 (after I4)

R0 = 0R1 = 0R2 = 0R3 = 30

Question 4This question is intended to help you understand the relationship between delay slots, control hazards, and branch execution in a pipelined processor. In this exercise, we assume that the following MIPS code is executed on a pipelined processor with a 5-stage pipeline, full forwarding, and a predict-taken branch predictor:

a) Draw the pipeline execution diagram for this code, assuming there are no delay slots and that branches execute in the EX stage.

Executed Instructions Pipeline Cycles1 2 3 4 5 6 7 8 9 10 11 12 13 14

a)LW R2,0(R2)BEQ R2,R0,Label (T)LW R2,0(R2)BEQ R2,R0,Label (NT)OR R2,R2,R3SW R2,0(R5)

IF ID EX MEM WB IF ID *** EX MEM WB IF *** ID EX MEB WB IF ID *** EX MEM WB IF ID EX MEM WB IF ID EX MEM WB

b)LW R2,0(R1)BEQ R2,R0,Label2 (NT)LW R3,0(R2)BEQ R3,R0,Label1 (T)BEQ R2,R0,Label2 (T)SW R1,0(R2)

IF ID EX MEM WB IF ID *** EX MEB WB IF ID EX MEB WB IF ID *** EX MEB WB IF *** ID EX MEB WB IF ID EX MEB WB

b) Repeat 4(a) above, but assume that delay slots are used. In the given code, the instruction that follows the branch is now the delay slot instruction for that branch.

Executed Instructions Pipeline Cycles1 2 3 4 5 6 7 8 9 10 11 12 13 14

a)LW R2,0(R2)BEQ R2,R0,Label (T)OR R2,R2,R3LW R2,0(R2)BEQ R2,R0,Label (NT)OR R2,R2,R3SW R2,0(R5)

IF ID EX MEM WB IF ID *** EX MEB WB IF *** ID EX MEB WB IF ID *** EX MEM WB IF *** ID EX MEM WB IF ID EX MEM WB IF ID EX MEM WB

b)LW R2,0(R1)BEQ R2,R0,Label2 (NT)LW R3,0(R2)BEQ R3,R0,Label1 (T)ADD R1,R3,R1BEQ R2,R0,Label2 (T)LW R3,0(R2)SW R1,0(R2)

IF ID EX MEM WB IF ID *** EX MEM WB IF *** ID EX MEB WB IF ID EX MEM WB IF ID EX MEM WB IF ID EX MEM WB IF ID EX MEB WB