MIPS - Pipeline

Por Wilson Ruggiero

Estágio: Instruction Fetch - IF

cPC

PCin(31:0)

PCout(31:0)

PC

U1

NPC(31:0)

inst(31:0)

RIout(63:0)

ckri

RI

U2

in1(31:0)

in2(31:0)

sai(31:0)

Soma4

U3

ckICEnd1(31:0)

Dout(31:0)

ICache

U4

pcsrc

in1(31:0)

in2(31:0)

out3(31:0)

Mxpc

U5

pcsrc

cPC

ckIC ckri

Ctc4(31:0)

NPCJ(31:0)

RIout(63:0)

Ctc4(31:0)

PCa(31:0)

instrucao(31:0)

NPC(31:0)

NPCJ(31:0)

library IEEE;use IEEE.std_logic_1164.all;use IEEE.numeric_std.all;

Design Unit Header

newpc(31:0)

Composição do RIout

Riout(63:0)

Riout(63:32) Riout(31:0)

Inst(31:0) NPC(31:0)

Tipo Formato das Instruções do MIPS - [inst(31:0)]

R opcode rs rt rd shamt Funct

6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

bits (31:26) (25:21) (20:16) (15:11) (10:6) (5:0)

RIout (63:58) (57:53) (52:48) (47:43) (42:38) (37:32)

I Opcode rs rt Address

6 bits 5 bits 5 bits 16 bits

bits (31:26) (25:21) (20:16) (15:0)

RIout (63:58) (57:53) (52:48) (47:32)

Multiplexador - MxPC

library IEEE;use IEEE.STD_LOGIC_1164.all;use ieee.numeric_std.all;entity Mxpc is

port(spc : in STD_LOGIC;in1 : in signed(31 downto 0);in2 : in signed(31 downto 0);out3 : out signed(31 downto 0)

);end Mxpc;

architecture Mxpc of Mxpc isbegin

out3 <= in1 when spc = '0' else in2;end Mxpc;

Program Counter - PClibrary IEEE;use IEEE.STD_LOGIC_1164.all;use ieee.numeric_std.all;entity PC is

port(cPC : in STD_LOGIC;PCin : in signed(31 downto 0);PCout : out signed(31 downto 0)

);end PC;

architecture PC of PC isbegin

PCout <= PCin when (rising_edge(cPC));

end PC;

Somador de 4 – Soma4library IEEE;use IEEE.STD_LOGIC_1164.all;use ieee.numeric_std.all;

entity Soma4 isport(

in1 : in signed(31 downto 0);in2 : in signed(31 downto 0);sai : out signed(31 downto 0)

);end Soma4;

architecture Soma4 of Soma4 isbegin

sai <= in1 + in2;

end Soma4;

Cache de Instruções - ICachelibrary IEEE;use IEEE.STD_LOGIC_1164.all;use ieee.numeric_std.all;

entity ICache isport(

ckIC : in STD_LOGIC;End1 : in signed(31 downto 0);Dout : out signed(31 downto 0)

);end ICache;

architecture ICache of ICache istype mcache is array (0 to 255) of signed(31 downto 0);signal icache: mcache;begin

Dout <= icache(to_integer(End1)) when rising_edge(ckIC);end ICache;

Registrador de Instrução - RIlibrary IEEE;use IEEE.STD_LOGIC_1164.all;use ieee.numeric_std.all;

entity RI isport(

NPC : in signed(31 downto 0);inst : in signed(31 downto 0);ckri : in STD_LOGIC;RIout : out signed(63 downto 0)

);end RI;

architecture RI of RI isbegin

RIout(63 downto 32) <= inst when rising_edge(ckri);RIout(31 downto 00) <= NPC when rising_edge(ckri);

end RI;

Estágio Instruction Decode - ID

enda(4:0)

endb(4:0)

endw(4:0)

dataw(31:0)

dataa(31:0)

datab(31:0)

ph1

ph2 rw

MemReg

U1

rega(31:0)

NPC(31:0)

ID_EXout(137:0)

ckID_EX

regb(31:0)

r1(4:0)

rt(4:0)

sext(31:0)

cEX(3:0)

cM(2:0)

cWB(1:0)

cEXo(3:0)

cMo(2:0)

cWBo(1:0)

ID_EX

U3

in1(15:0) out1(31:0)

Sign_ext

U4

RIout(63:0)

contin(7:0)

cEX(3:0)

cM(2:0)

cWB(1:0)

UC1

U2

ph1

ph2

rw

ckID_EX

ID_EXout(137:0)

dataw(31:0)

RIout(63:58)

RIout(31:0)

RIout(57:53)RIout(52:48)

RIout(52:48)RIout(47:43)

RIout(47:32)

enderw(4:0)

contWB(1:0)

contM(2:0)

contEX(3:0)

cWBo(1:0)

cMo(2:0)

cEXo(3:0)

GREG

ID_EX

CONT

library IEEE;use IEEE.std_logic_1164.all;use IEEE.numeric_std.all;

Design Unit Header

Composição do ID_Exout(137:0)

ID_Exout(137:0)

(137:132) (132:128) (127:96) (95:64) (63:32) (31:0)

rt rd sext Regb Rega NPC

Sinais de Controle – Estágio de Decodificação -ID

cEXo(3:0) MC(8:5) cMo(2:0) MC(4:2) cWBo(1:0) MC(1:0)

0 RegDst 0 Branch 0 RegWrite

1 ULAop1 1 MemRead 1 MemtoReg

2 ULAop2 2 MemWrite

3 ULAsrc

Estágio Instruction Execution - EXcWBo(1:0)

cMo(2:0)

cEXo(3:0)

ID_EXout(137:0)

In2(4:0)

In1(4:0)

Out1(4:0)Smx1

Mux1

U1

In2(31:10)

In1(31:10)

Out1(31:0)Smx2

U2

Out1(31:0)In1(31:0)

SL2

U3In2(31:0)

In1(31:0)

Res(31:0)

Somador

U4

In2(31:0)

In1(31:0)

Out1(31:0)

Zero

ULA

U5

Reg(31:0)

ULAo(31:0)

NPCJ(31:0)

endreg(4:0)

cMo(2:0)

cWBo(1:0)

Zero

ckEX_M

cWBo1(1:0)

cMo1(2:0)

Zeroo

EX_Mo(101:0)

EX_M

U6

In1(5:0)out1(3:0)ulaop(1:0) C_ULA

U7

ID_EXout(137:106)

ID_EXout(105:74)

ID_EXout(41:10)

ID_EXout(41:10)

ID_EXout(15:10)

ID_EXout(9:5)

ID_EXout(4:0)

Mux2ID_EXout(73:42)

cEXo(0)

cEXo(3)cEXo(2:1)

ULA

C_ULA

SL2

SOMA

EX_M

MX

MX

Zero

cWBo(1:0)cMo(2:0)

EX_Mo(101:0)

Zeroo

ckEX_M

ID_EXout(73:42)

library IEEE;use IEEE.std_logic_1164.all;use IEEE.numeric_std.all;

Design Unit Header

Composição do EX_Mo

EX_Mo(101:0)

EX_Mo(100:96) EX_Mo(95:64) EX_Mo(63:32) EX_Mo(31:0)

EndReg(4:0) Reg(31:0) ULA(31:0) NPCJ(31:0)

Sinais de Controle – Estágio de Execução - EX

cMo(2:0) cWBo(1:0)

0 Branch 0 RegWrite

1 MemRead 1 MemtoReg

2 MemWrite

Estágio Memória de Dado - MEM

endr(31:0)

endw(31:0)

dataw(31:0)

datao(31:0)

ph1

ph2

mem

read

mem

write

D_MEM

U1

cWBc(2:0)

dmout(31:0)

regout(31:0)

endw(4:0)

cWBo(2:0)

M_WBo(68:0)

ckM_W

B

M_WB

U2

EX_Mo(100:0)

cWBo(1:0)cMo(2:0)

Zeroo I0O

I1

NPCJ(31:0)

cWBo(1:0)

M_WBo(68:0)

ph1ph2

ckM_WB

pcsrc

EX_Mo(62:32)

EX_Mo(63:32)

EX_Mo(31:0)

EX_Mo(95:64)

EX_Mo(95:64)

EX_Mo(100:96)

DMout(31:0)

M_WB

DMEM

cMo(1)

cMo(2)

cMo(0)

Composição do M_WBo

M_Wbo(68:0)

M_Wbo(68:64) M_Wbo(63:32) M_Wbo(31:0)

Enderw(4:0) Reg(31:0) ULAo(31:0)

cWBo(1:0)

cWBo(1) cWBo(0)

MemtoReg RegWrite

‘0’ ULAo ‘0’ ler GPR

‘1’ Reg ‘1’ Escrever GPR

Estágio Write back - WB

cWBo(1:0)

M_WBo(68:0)

enderw(4:0)

dataw(31:0)

regwrite

In0(31:0)

In1(31:0)

sai(31:0)

smx3

MX3

U1

M_WBo(68:64)

M_WB0(63:32)

M_WBo(31:0)

cWB0(0)

cWBo(1)

MUX