INTRODUCTIONThe evolution of integrated circuit technology demands that designers in this fi eld

adapt to ever-changing manufacturing techniques driven by performance, cost,

benefi t, and risk considerations. Today’s power amplifi er (PA) designer working in solid-

state technologies must navigate a plethora of available processes, including gallium

arsenide (GaAs), gallium nitride (GaN) and silicon carbide (SiC) pseudomorphic high

electron mobility transistor (PHEMT), radio-frequency complementary metal oxide

semiconductor (RF CMOS), and GaAs or silicon germanium (SiGe) heterojunction

bipolar transistor (HBT), to name just a few. Similarly, different design challenges

demand different amplifi er classes and/or topologies like Class AB, Darlingtons,

switch-mode PAs, and digital predistortion. Moving from one technology to another

implies that certain skills and knowledge are transportable and transferable.

The most basic of these skills is the effective use of electronic design automation

(EDA) tools for designing the monolithic microwave IC (MMIC) itself. More exactly,

it is a strategy, design fl ow, or guidelines for how to start from requirements

and a process design kit (PDK) and get to a point where the more complicated

requirements can be tackled. In this white paper, a GaAs pHEMT PA design

approach is examined from a systems perspective. It further highlights the design

fl ow and its essential features for most PA design projects by illustrating the design

of a simple, Class A GaAs pHEMT MMIC PA done with AWR’s Microwave Offi ce®

high-frequency design software. Before illustrating a detailed approach to the

design, the concepts of design closure and parametric design are described as key

concepts to understanding each step of the PA design process.

THE DESIGN FLOW IN GENERALDesign fl ows, or how a design gets done, can sometimes appear to be a chaotic affair,

but there is a logic and order to walking a design through a process from concept to

completion. Design fl ows can be viewed in several different ways, and perhaps this is

what causes some of the confusion. If viewed as a series of steps that are repeated or

iterated until the simulated performance converges on the desired requirements,

it’s easy to miss much of the underlying structure of the design that makes

it a repeatable, reliable methodology. Top-down design fl ows are highly

desirable as they provide predictability. By relating design parameters to

overall performance, engineering teams can drill down into the com-

ponents with cause-and-effect relationships clearly defi ned. Bottom-up

design, on the other hand, assures to some degree that each

individual piece of the design contributes its necessary functionality as

imagined by the engineering team. By showing that each component

does this from a micro-to-macro, netlist-to-behavioral, layout-to-

schematic, etc. perspective, the engineering team demonstrates that

its design converges to the requirements; they’ve achieved “design

closure.” These, then, are two of the more substantial hallmarks of the

engineering process: parametric design and design closure. This and what

follows is a very succinct treatment of design fl ow that has been elaborated on

many times elsewhere for microwave [1-4,6] and analog mixed-signal [5] designs.

Microwave Offi ce®

White Paper

RF/Microwave EDA Software Design Flow Considerations for PA MMIC Design

Layout

CircuitDesign

SystemDesign

Simulation& Analysis

LVS/DRC

Extraction

LVS/DRC

Simulation

Circuit

SystemDesign

ExtractionExtractionExtraction

LayoutLayout

THE DESIGN FLOW AS APPLIED TO A GAAS MMIC PAFor the typical GaAs PA design, the design fl ow plays itself out in Figure 1. Required

performance leads to a sequentially more detailed design step (dotted outline box),

where the design team strives to defi ne more and more of the PA’s behavior as

more complex phenomena are explored. The detailed understanding of the circuit

gleaned in each substep of the design ultimately secures a complete picture of the

PA’s complex performance—a sort of “walk before you run” approach.

The fi rst iteration may only be selection of the bias point, but even here there can be

a substantial amount of complexity, such as load-pull or thermal considerations. The

second pass through the design fl ow will focus on linear performance and stability

in terms of input and output network design. Again, this should not be trivialized, as

a large linear array of devices must be fed with manifolds that not only provide good

matching to the source and load impedances but also feed all the individual fi eld effect

transistors (FETs) in the array in-phase. Linear design is followed by nonlinear per-

formance, and this is where the design really gets down to business; saturation and

effi ciency are examined in detail while still assuring linear gain and stability. Trade-offs

must be made and then fi ne-tuned as the layout is produced and then extracted back

into the simulation for the fourth and fi nal design substep. The analysis follows the

design to assure that assumptions are justifi ed and second order effects understood.

Issues commonly dealt with here include a full electromagnetic (EM) analysis to assure

layout standards and minimized couplings, and an iterative electro-thermal analysis to

guarantee that the channel temperature has been adequately modelled. The fi nal step,

verifi cation, is used to prepare the design for manufacturing with design rule checks

(DRC) and provide one fi nal opportunity to ensure that the design is compliant with

performance, manufacturing, test, and packaging requirements before tape-out.

The remainder of this paper illustrates an example of this design process, executed

for a simple PA example using AWR’s Microwave Offi ce circuit design software.

PA DESIGN EXAMPLEStep 1: Requirements

Turning to the GaAs PHEMT PA design fl ow, this example examines the role of various

design considerations and shows how parametric design and design closure manifest

themselves. The assumed specifi cations are for a Class A amplifi er powered by a VDC

source that is summarized by maximized power added effi ciency (PAE) for a given linear

antenna output power, Pant, slightly backed off from the PA’s P1dB with moderate (single

stage) gain (G), and some antenna mismatch.

Figure 1: Generalized incremental design fl ow with iterated analysis.Figure 1: Generalized incremental design fl ow with iterated analysis.

Verification

Extracted Layout

Nonlinear Design

Linear Design

Bias Selection

AnalysisRequirements

Step 2: Bias Selection

Substep 1: Power Dissipation

To realize this design, users can immediately dive into the bias selection (fi rst design

substep) with some quick calculations. In this step, as in all steps, it is necessary to

clearly articulate what design requirement is to be achieved, identify the design param-

eters that dominate in determining how the design meets this requirement, and then

show that the selected values for these parameters satisfy the requirement.

Without selecting a proper bias point and associated FET periphery, there is no gain

(G), the amplifi er may not support enough output power (Pant), and it may be far from

linear (P1dB). In short, if the PAE is used as a design requirement and the pHEMT

DC Ids and Vds are viewed as design parameters, then this fi rst step can be viewed in

terms of parametric design.

For the actual PA output power, the other components in the design may need

to be considered. Sometimes, PA design requirements are not given solely with

regard to the PA itself, but instead are specifi ed with regard to the system, or both

the system and the PA. Figure 2 shows a reasonable system diagram from the PA

to the antenna and highlights several additional components that may need to be

considered in translating the system requirements into those for the PA.

The inclusion of switches and a consideration of the antenna impedance create a

relationship between the power at the antenna or the system power output and that

which is required of the PA.

Pout= Pant + Lossswitches + Lossmatch + margin (1)

Lossswitches is assumed as the loss through a transmit-receiver (TR) switch and/

or diversity switches (Figure 2), Lossmatch as the mismatch at the antenna, and

margin as a combined design and back-off margin. While in the ideal world of

computer-aided design (CAD) simulations the PA will deliver all the power it simu-

lates, in reality, when built, users would expect there to be device-to-device or

lot-to-lot variation in Pout for which they would wish to account in the margin.

From (1), the power dissipation (PDC) within the PA can be determined from the PAE

PDC = exp(Pout/10) * 1/PAE (2)

With a reactive load, the drain-source voltage and VDC are roughly identical—in other

words, in the absence of a drain (load) resistor, the DC drain bias is dropped entirely

across the transistor drain source.

IQ = PDC/VDC = IQ(Vgs, Temp) (3)

Figure 2: System diagram showing components contributing to specifi cation of power amplifi er based on performance at the antenna.

From IQ, the quiescent drain-source current, the IV curves for the device, and the

corresponding gate-source voltage (Vgs) at which the PHEMT should be biased as

a function of temperature can be consulted. The FET periphery is sized such that

selection of Ids as a function of Vds is approximately halfway between VDC and the

“knee” of the IV characteristics at the channel temperature. The choice of “halfway”

is determined by the desire to have a Class A amplifi er and will change depending on

whether an AB, B, etc. topology is chosen. This gives the essential aspect of the fi rst

substep in the design.

This entire substep can be accomplished quickly and effi ciently with Microwave Offi ce.

A DC IV sweep can be set up using either one of the two IVCURVE elements to simu-

late a nested DC sweep (voltage over current for bipolars or voltage over voltage for

FETs). Most well-supported MMIC processes include FET models with DC bias over

temperature, so the IV curves can be further explored through tuning/sweep. A graph

of classic FET IV curves cast as IDS versus temperature (shown in Figure 3) can also be

helpful to see the current gradient and whether it is substantial.

Step 2: Bias Selection

Substep 2: Thermal Dissipation

Before actually moving on to the small-signal design, it is not a bad idea to pause and

refl ect on the thermal implications, especially since there is a temperature dependence

in Equation (3). FET devices like GaAs PHEMTs are majority carrier devices with

the control terminal dominated by a voltage determining the current at the output.

Thermal sensitivity to this physical process comes from increases in the majority

concentration, which are more than offset by additional scattering mechanisms that

in aggregate manifest themselves as a decrease in output current with increasing

operating temperature. This is a negative feedback process. The balance between

these two effects is clearly illustrated in Figure 3. At lower currents, the warmer

device has more carriers in the channel and the resulting current is higher than for

the room temperature device. As self-heating becomes a dominant factor, the elevated

temperature increases the scattering, making it more diffi cult for carriers to traverse

from source to drain, thereby reducing the current fl ow.

In practice, the pHEMT current changes relatively slightly [6] and, aside from very real

reliability considerations, temperature is less of a factor in the pHEMT design than in

the electrical design of a PA using a bipolar junction transistor (BJT), where thermal

runaway is a very real concern. From a design fl ow perspective, since the bias is sensi-

tive to temperature and the temperature in the FET channel will tend to “pull” the bias

Figure 3: IV characteristics at ambient (blue, 25 degC) and elevated (red, 100 degC) operating temperatures.

one way or the other as compared to room and/or baseplate, it is prudent but not

necessarily essential to consider temperature as part of this initial bias design step.

The integrated electro-thermal design fl ow in the AWR Design Environment™

(AWRDE) speeds this substep by providing a “mini-fl ow”—the FET stage can actu-

ally be simulated, a layout just of the FETs done, and a thermal simulation done with

the AWR Connected™ CapeSym SYMMIC design solution, all in an hour or less. This

enables the designer to zero in on a more precise understanding of the interplay

between temperature and IDS not only in this step, but also as a design closure con-

straint easily checked at each of the subsequent steps.

Step 2: Bias Selection

Substep 3: Load Pull

Another consideration in bias selection of power amplifi ers is load pull, or the shifting

of the effective output impedance of the FET in its nonlinear operation. This implies

that as the input signal power is varied, the FET will operate in a linear fashion at

lower powers, but then shift as the power is altered. In reality, the load impedance is

altered while measuring a particular performance parameter so that the impedance

presented to the FET can be advantageously chosen. Alternatively, given that the

FET operates with some degree of nonlinearity, how is this nonlinearity altered by the

load impedance? This is clearly a parametric design fl ow issue as there is a specifi ed

performance criteria tied to a design parameter—the load as seen by the FET.

Thus, when considering load pull it is not enough to say that a bias was selected based on

load-pull considerations—what nonlinear output characteristics are being “pulled” by what

load impedance must also be stated. For this reason, load-pull data is often presented as

circles on a Smith Chart. PAE or saturated output power are typical values, but second-

or third-harmonic cancellation can also be important. In more detailed approaches to PA

design, such as waveform engineering, the entire FET model is essentially the load-pull

data for the FET using a close facsimile of the desired input signal. For these reasons, this

step might be considered as part of Step 3, linear design, since the performance criteria

being monitored is something other than the IV curves.

The Microwave Offi ce Load-Pull utility is a great script to invoke for doing this in the

context of the design. Figure 4 shows load-pull contours for the device used in Figure

3—contours of the PAE are plotted against two different bias conditions. This allows

the designer to check the effi ciencies available given the DC dissipated power (i.e.,

different bias conditions) and different (load) impedances presented to the transistor

(i.e., the load-pull contours themselves). Perhaps more important from the design

perspective is the use of the simulated load-pull capability simultaneously with the

conjugate small-signal output match of the transistor versus gate bias (Figure 5).

Since maximal power transfer requires the conjugate output match of the transistor,

this graph is of key importance for the design fl ow as the cross section of maximal

power transfer and PAE make for a very good power amplifi er. One note: Since this

PA has been specifi ed to operate in a mode “backed off” from P1dB, the small-signal

S22 can be used in lieu of a measurement that gives the large-signal equivalent.

Again, as with the thermal “mini-fl ow,” if the time is taken to set up a load-pull

analysis of just the FET stage, this can be used as a design closure condition for the

remaining steps. It can also be expanded later on to look at nonlinear performance

as well as confi rm FET stage performance when the impedance of the output match-

ing network is better understood.

Figure 4: Simulated PAE load-pull contours using Microwave Offi ce’s Load-Pull script to compare two different gate bias conditions with constant drain bias.

Figure 5: Simulated PAE load-pull contours versus conjugate S22 match.

Step 3: Linear Design

Without oversimplifying, the next step is to get the bias and linear performance in

order by adjusting the parameters defi ning the input and output networks presented

to the pHEMT. In other words, the parametric design aspect of the fl ow enables the

user to control the linear performance by adjusting the input and output impedances

seen by the FET. In advanced fl ows, this may mean designing the input and/or output

network at not only the fundamental frequency of the PA, but at the harmonics as

well. Design closure, the other fl ow criteria, is reached by maintaining the perfor-

mance in substep 1 (essentially a DC bias that stays close to achieving PAE and Pout)

while obtaining the gain and match as required.

Typically the pHEMT periphery obtained from getting the correct bias and meeting the

output power constraints gives input and output impedances near 50ohms, but per-

haps not close enough, so impedance matching to some degree may still be required.

With a large FET, the input gate-source capacitance can be fairly large (Figure 6), so

as the frequency of operation goes up, the input impedance will start to vary more

substantially with frequency and the input match becomes more challenging.

The input match should be implemented with an eye to stability and temperature is a

minimal consideration in this substep. Specifi cally, if the DC bias network for the gate

of the PA FET is properly designed with chokes and by-pass capacitors, there is the

possibility for creating low frequency resonators, which could lead to oscillations. So,

in addition to having the gain, G, as the design requirement for this step, linear sta-

bility indicators, such as K and B1, should also be included. In more advanced design

fl ows stability would also be included as a nonlinear design goal [8].

As important as the input match is to “playing nice” with the earlier components in

the transmitter chain, the bread-and-butter of the PA is the output side of things.

First and foremost, without the output network being properly designed to give gain,

this won’t be an amplifi er, let alone a power amplifi er. To get the most voltage swing,

and hence highest power out, an inductor for the load is used so that there is mini-

mal resistive loss limiting the Vdc voltage available from that which can be seen at the

FET drain. In other words,

Vd=Vdc-min(Vds(t))-IdsRe(ZL) (4)

or, the voltage available at the drain will be the DC source voltage less the minimum

Vds necessary to keep the FET from going over the knee and the voltage from drop-

ping due to any real impedance component in the load. At fi rst blush, the answer

would be a big MMIC inductor, however, big MMIC inductors normally come with

larger resistance, so there is a trade-off to be made. This trade-off must be con-

sidered whether the PA is fully monolithic (with load inductor on-chip) or provided

externally. The external, off-chip inductor can be quite attractive because of the

higher Q and lower loss available, but the extra parasitic capacitances and induc-

tances in getting to the off-chip device introduces further stability concerns.

As alluded to earlier in the discussion on load pull, a good output match is also

essential for staying within the margin specifi ed in (1) and should be identifi ed

through load-pull simulations or measurements [7] to identify the needed conjugate

match for maximum power transfer:

Zout = Z*d (5)

Figure 6: The PHEMT presents input and output impedances not matched to 50ohms and quite capacitive.

where Z*d is the complex conjugate of the impedance looking into the FET/load

circuit and Zout is the impedance looking into the output matching network from the

FET/load circuit and terminated at its output by the desired load (typically 50ohms).

This point in particular cannot be overemphasized as Pout gets more substantial. The

role of the PA is to get power to the antenna and the easiest way to miss this goal is

to have power being stored or dissipated between the PA FET and the pin or connector

representing the PA. The design of a proper matching network that transforms the “not

exactly” 50ohms at the FET drain to the “as close to” 50ohms as we can get at the pin/

connector can be the difference between marginal and extraordinary effi ciency.

Design closure for this step should confi rm that the DC bias still provides the

nominal DC power consumption for the expected PAE and that the linear gain,

G, and any input and output matching criteria (in terms of VSWR or S11 or S22,

respectively) has been achieved.

Implementing this in AWRDE is fairly simple and is no different from designing

small-signal amplifi ers or passive circuits. Create the schematic, implement the

desired measurements on several graphs and go. One hint to speed things along

for later steps: The circuit can be set up in hierarchy with “test benches” at the

top-level, especially for the nonlinear simulations, but be sure to keep the initial

schematics simple by using ideal components like an IND and reserve the MMIC

PDK spiral inductor models, for example, until the topology is more certain. This

tends to make the key design parameters easier to identify early on because

there’s no confusion of results by parasitic effects.

Working from Figure 6, it can be seen that the S22 for the transistor is nearly on the

real part of the impedance circle corresponding to 50ohms. (Figure 5 also shows

this value as the conjugate match in the upper half of the Smith Chart). This makes

a conjugate match appear to merely require adding an equivalent series inductance,

but this gets progressively more diffi cult at higher frequencies (since the length of the

interconnects turns the inductor into a transmission line) and the power output goes

up (since the lines will need to be thicker to handle the current in accordance with

the design rules). Normally this is more complicated and some stepped impedance

transformer is needed to get the real part of the impedance to be matched as well as

“matching out”—or conjugate matching—any of the imaginary part. For this design, an

equivalent inductance of a few nanohenries (Figure 7) suffi ces, but how to implement

this is a task for the layout, if it is to go on-chip, or for the packaging, if it’s just not

feasible given the size and current handling constraints already mentioned.

Figure 7: Matched output impedance using a lumped inductor to give the equivalent conjugate impedance to the transistor S22.

Referring back to Figure 5, note that the match for maximum power transfer does

not correspond to the match for optimal PAE. A trade-off will need to be made

when the nonlinear aspects of the design are considered, but at this point, we have

achieved design closure in the small signal by completing the small-signal design

criteria, namely the match that we would like.

Step 4: Nonlinear Design

This third trip through the design parameter/closure loop focuses on the nonlinear

performance, PAE, and P1dB by fi ne-tuning the bias and match. But just as in the

linear design step, in order to achieve design closure, what’s already been gained

should not be disturbed, so the nonlinear performance must be optimized without

sacrifi cing gain, match, and, perhaps most importantly in this step, stability. It will be

very tempting to boost the PAE in ways that undermine the stability of the design—

after all, what better way to get more power out with the same DC power than to

create an oscillator!

From the perspective of the design fl ow’s parametric design requirement, it may

seem like the design parameters controlling the performance of this step are the

same as the previous step, except the nonlinear simulator is used to look at PAE

and P1dB (or some other measure of nonlinearity). But this is also an ideal step to

expand the consideration of what actually comprises the input and output matching

networks to include bias lines, grounding, and bond wires or bumps that are off-

and on-chip. Typically, bounds on parasitic source inductance are monitored to give

guidance to layout (bound-pad number and placement) and packaging (bond-wire

count and length) in regard to not only degradation of the nonlinear performance

criteria but also to assuring that the requirements associated with the previous

substeps are still being met.

The focus of this design step is really to try to push out the compression of the

linear output power as the input power is ramped up, as well as to boost the PAE.

Strategies for doing this—thereby achieving this steps’ design closure—will focus on

minimizing parasitics and adjusting the bias conditions slightly. It can be tempting to

change the FET periphery, but this can be dangerous, especially if load pull has been

involved, since the linear part of the design has presumably been optimized based

on a detailed understanding of the FET input and output impedances. If the IQ from

(3) can be backed off to boost PAE without jeopardizing linearity, then some thermal

margin of sorts is created with the lower current.

One note should be emphasized in regard to FET modelling. A clear and detailed

understanding of the FETs’ nonlinear behaviour—and to what degree the models

being used capture those nonlinearities—is essential. For example, if the intent is to

minimize third-order harmonic generation by clever impedance matching as a way

to extend P1dB, then the model being used should not only be accurate in its ability to

generate the third harmonic via derivatives of gm (current-based nonlinearity) or Cgs/

Cgd (capacitance-based nonlinearity), but also should do so with the load impedance

being something other than 50ohms. Such demands on a model are not trivial, and,

conversely, trying to simulate and “design out” such behaviour without validating that

the model is so capable is a waste of time at best and foolhardy at worst.

If the “test bench” style of project organization (Figure 8) has been done, the

Microwave Offi ce nonlinear simulations can be reused with linear analysis simply by

changing the measurement being performed on the test bench—PORTs in AWR

(even nonlinear source ports) act as S-parameter terminations so dual use can be

obtained from a graph. In Microwave Offi ce, the PORT elements double as both

linear terminations and subcircuit/hierarchy elements. Reuse of the underlying

schematic across all analyses is important if the test bench’s underlying schematic(s)

begin(s) to include off-chip or bias-related parasitics. Furthermore, if the PA is Class

C or better, the designer can start using transient analysis with this same simulation

set up at the test bench schematic level.

For this particular design example, the nonlinear measurements of importance are the

PAE as well as the gain compression (Figure 9). The PAE is the parameter that needs

to be optimized, but the original constraint that was introduced for this design spoke of

having the PA “backed off” from P1dB. This means that the PA’s actual operating point

for some given output power must correspond to an output power that is lower by

some margin from the point where the amplifi er gain is seen to compress.

If this particular FET size and bias are used with the conjugate match for maximum

power transfer, then the PA compresses at lower output powers and it does not

deliver the optimal PAE. This can be understood from the load-pull contours in Figure

5, since the intersection of the conjugate S22 match with the load-pull results for this

bias point show that the PA will not achieve the PAE maximum. The load-pull contours

at this bias clearly show that both cannot be achieved simultaneously.

Figure 8: “Test bench” style of project developing where the subcircuit is shared among (left) linear and (right) nonlinear analyses to ensure consistent capture of parametric design and design closure criteria.

Figure 9: PAE (%) and output power (dBm) for the transistor optimally matched for maximum PAE versus the transistor conjugately matched for maximum power transfer.

In practice it is more often the case that the PA design will demand the conjugate

matching of the transistor at the expense of PAE. In this case, the load pull would

have been relative to maximum power transfer and not to PAE. This would have

yielded an optimal match that would not have corresponded to the small-signal S22,

but would have given an impedance that “pulled” away from the small-signal S22.

Step 5: Extracted Layout

Having completed the electrical design, the fi nal “design” step

is to actually lay out the PA. The parametric design require-

ment is somewhat lost at this point if the interconnects are

not captured on the schematic, so, to the greatest degree

possible, microstrip or coplanar waveguide elements should

be placed on the schematic so that lengths and widths can be

tied to maintaining the overall chip performance criteria. More

than a few MMIC designs, PAs included, have never made it

past this stage of product development simply because this

parametric design requirement was lost at this stage in the

design process in an endless series of “move a line, run the

EM solver, simulate the circuit….and repeat” ad infi nitum.

In the face of dozens or a hundred interconnects and an

extracted layout that does not achieve design closure, it is

essential that the design team ascertain which interconnects

control critical MMIC performance at the earliest possible

time. If the MMIC PDK supports bond pads, then these should

be included in the parametric design stage as well.

Design closure is achieved when the nominal simulations,

including all these effects, confi rm that the overall chip per-

formance criteria have been met. Small (less than chipscale)

EM analysis can be done locally to confi rm that the input and

output matching networks achieve their desired performance,

such as that defi ned by equation (5).

The fl ow in AWRDE is a bonus when it comes to this stage

of the PA design fl ow. Using EXTRACT™ along the lines of the

circuit partitioning that would normally be done—input match,

FET stage(s), and output match—enables the user to quickly

confi rm post-layout performance with schematic-based esti-

mates from earlier in the design. Don’t forget to include the

PDK’s bond pads as part of the schematic simulation, and if

possible, the EXTRACTed design.

As a case in point, Figure 10 shows a simple drain manifold

added as a transition from the drain structure of the FET

used in this example to a 100um-long section of 50um line on

50um-thick GaAs.

The resulting PAE and Pout simulation is also shown exhibiting

the nonlinear performance degradation induced by these rela-

tively minor but necessary features. In contrast, the bondpads

themselves (Figure 11) offer very little change.

Figure 10: (Top) drain manifold transition in layout and (bottom) comparison of pre- and post-EXTRACTED simulation using APLAC nonlinear simulation with AXIEM EM analysis.

Figure 11: Nonlinear performance of the ideal PA compared to adding three parallel bondpads at the PA output.

Step 6 - Final Analyses

The fi nal analysis step is where the design assumptions and simplifi cation taken while

creating the design can be revisited in the context of the whole design (now that it is

seemingly complete). This step enables the designer to ensure that the whole is at

least the sum of the parts and that in the process of focusing on parts of the design

(i.e., partitioning into smaller pieces), two of the pieces were not inadvertently coupled

together in such a way as to take away from the overall performance. From that

perspective, it’s desirable to try and view this step as going “up” one level, so that the

design parameters are the sub-blocks (input match, output match, FET/load, bias

circuit, etc.) rather then the individual components within the sub-blocks. The perfor-

mance criteria are the overall chip requirements and design closure is achieved when

the performance criteria are met relative to what that analysis explores: electrical

performance for EM, reliability for thermal, manufacturability for DRC, etc.

An analysis step is performed to ensure that second order effects like EM coupling

and thermal do not violate earlier design parametric constraints and assumptions.

EM analysis will verify assumptions on source inductance and interconnect parasitics

that can contribute to feedback paths, which may enhance instabilities. Although time

consuming and requiring memory-hungry workstations, the greater the detail of the

EM analysis, the greater the likelihood of fi nding potential oscillations or performance-

starving parasitic effects. An EM simulation such as AWR’s AXIEM® 3D planar EM

simulator with the EXTRACT fl ow should be run at the top-level chip now rather than

simply considering each design sub-block separately. Going back and forth between the

two is a great strategy for isolating any problems uncovered at this time.

Formalized fi nite element method (FEM) thermal analysis reconfi rms the channel

operating temperatures. In the last decade or so, EM analysis has become robust

enough to be included in the MMIC designer’s fl ow: the same is now coming true

with thermal analysis. Although new and different to the other substeps with which

an electrical engineer may be familiar, thermal analysis is just too simple within the

MMIC toolset and the payback too great NOT to do it. Underpinning many of the

assumptions of the PA design is the operating temperature of the FET channel.

With all the metallization in place after the layout is fi nalized, an electro-thermal

analysis can reaffi rm decisions made about FET channel spacing and DC bias.

SYMMIC integrated to AWRDE can help close this loop in a matter of hours (refer

to related application note(s) on SYMMIC and electro-thermal design on the AWR

website at www.awrcorp.com).

Should either the EM or thermal verifi cation step fail by not achieving design closure,

then interconnects can be made wider or shorter to minimize inductance or spaced

further apart to avoid capacitance, or pHEMT fi ngers can be spaced further apart

to relieve channel heating. In short, and without trivializing, for the GaAs pHEMT PA

designer the thermal consideration can in many cases be a secondary effect handled

as an analysis step during verifi cation. Of course, this is not withstanding aggressive

thermal specifi cations or reliability requirements.

The concern in this step is that the designer may actually succeed in fi nding a

problem with the design. Since the design parameters have been abstracted away,

the designer runs the risk of not knowing what to fi x (i.e., which interconnect to

move, which bond wire to shorten, etc.) if the analysis does not create closure with

the design requirements. The best guide here to addressing differences between

fi nal analysis and requirements is experience. The analysis tools will indicate that

there is a problem, but without the ability to directly tie cause and effect through

parametric models, the best guide is experience. Endless days or weeks of “move a

line, run an EM simulation” rarely provide the answer.

Last but certainly not least, design-to-manufacturing closure is needed: No design

should be shipped without foundry-based DRC. AWRDE includes both DRC and

layout-versus-schematic (LVS) tools, and some foundries will do it for designers in a

day or less.

CONCLUSIONMoving from one technology to another requires that certain skills and knowledge be

transportable and transferable. The most basic of these skills is the effective use of

EDA tools for designing the MMIC itself. In particular, PA designers need a strategy,

design fl ow, and guidelines for how to start with specifi cations and a PDK and get to

a point where the more complicated design requirements can be tackled.

In this whitepaper, the essential steps necessary for a typical PA design project have

been illustrated using AWR’s Microwave Offi ce to design a relatively basic Class A

GaAs pHEMT MMIC PA. The choice of a Class A amplifi er was made to emphasize

the fl ow itself and the need for designers to have a systematic approach to their

design and to the design fl ow. It has been shown that at each step in the design fl ow,

it’s important to clearly identify what it being designed, in terms of tying parameters

to performance, and how designers will know when they are done with that step.

Such an approach can be easily extended to more complicated classes of PAs and

other circuit types.

REFERENCES[1] M. Steer, Microwave and RF Design: A System Approach, SciTech Publishing, 2010.

[2] S. A. Maas, The RF and Microwave Circuit Design Cookbook, Artech House, 1998.

[3] D. Wu and S. Boumaiza, “Comprehensive First-Pass Design Methodology for High Effi ciency Mode Power

Amplifer,” IEEE Microwave Magazine, Vol 11. Issue 1, pp 116-121. February 2010.

[4] G. Gielen and R. Rutenbar, “Computer-Aided Design of Analog and Mixed-Signal Integrated Circuits,” Proc.

IEEE, vol. 88, no. 12, pp. 1825–1854, Dec. 2000.

[5] S. Nuttinck, B.K. Wagner, B. Banerjee, S Venkataraman, Ed. Gebara, J. Laskar, H.M. Harrais, “Thermal

Analysis of AlGaN-GaN Power HFETs,” IEEE Trans. Micro Theory Tech, Vol. 51, No. 12, pp 2445-2452, 2003.

[6] M. Alvaro, A. Caddemi, G. Crupi, N. Donato, “Temperature and bias investigation of self heating effect and

threshold voltage shift in pHMET’s,” Microelectronics Journal, Vol. 36, pp. 732-736, 2005.

[7] S. C. Cripps, RF Power Amplifi ers for Wireless Communications, 2nd edition, Artech House, 2006.

[8] A. Platzker and W. Struble, “Rigorous determination of the stability of linear n-node circuits from network

determinants and the appropriate role of the stability factor K of their reduced two-ports,” Third International

Workshop on Integrated Nonlinear Microwave and Millimeterwave Circuits, pp. 93-107, 1994.

Copyright © 2013 AWR Corporation. All rights reserved. AWR, Microwave Offi ce and AXIEM are registered trademarks and the AWR logo, EXTRACT, the AWR Design Environment, and AWR Connected are trademarks of AWR Corporation. Other product and company names listed are trademarks or trade names of their respective companies. WP-GAAS-2013.6.10

AWR Corporation | www.awrcorp.com info@awrcorp.com | +1 (310) 726-3000

Dr. Michael Heimlich, a well-known

member of the RF/microwave

industry, joined AWR in 2001.

Today he serves as a technical

consultant to AWR while also

teaching at Macquarie University.

Earlier in his career, Mike held

several positions at MA/COM

including CAE Manager for the IC

Business Unit and principal engineer

in IC product development. He also

designed GaAs MMICs for Pacifi c

Monolithics and designed space-

qualifi ed millimeter-wave mixers

at Watkins Johnson. Dr. Heimlich

earned his BSEE, MSEE, and

PhD EE degrees from Renssalear

Polytechnic.

Dr. Michael Heimlich

mike@awrcorp.com