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9-1510 Woodcock St.London, ONCanada N5H 5S1www.microtronix.com
MicrotronixQuad Link LVDS Interface
HDMC Daughter CardUser Manual
USER MANUALREVISION 1.3
Page 2 of 14
This user guide provides basic information about using the Microtronix Quad Link LVDS Interface HSMC Daughter Card. The following table shows the document revision history.
Date Rev Description
March 2011 1.0 First release
April 2011 1.1 Added Table 6
Nov. 2011 1.2 Added Hirose loopback cable
May 2012 1.3 Added Hirose Camera Link Transmitter cable
E-mailSales Information: [email protected]
Support Information: [email protected]
WebsiteSoftware updates to the HDMI Receiver / Transmitter HSMC Daughter Card and supporting Microtronix IP Cores are listed on the download page of our website and made available via an email request form. Some product upgrades are only available to customers who have purchased the ViClaro III kit.
The upload site is for sending files to Technical Support.
General Website: http://www.microtronix.com
Downloads Page: http://www.microtronix.com/downloads/
FTP Upload Site: http://microtronix.leapfile.com
Phone NumbersGeneral: (001) 519-690-0091
Fax: (001) 519-690-0092
Document Revision History
How to Contact Microtronix
Path/Filename A path/filename
[SOPC Builder]$ <cmd> A command that should be run from within the Cygwin Environment.
Code Sample code.
Indicates that there is no break between the current line and the next line.
Typographic Conventions
LVDS HSMC Daughter Card User Manual
Page 3 of 14
Table of Contents
Document Revision History .........................................................................................................2
How to Contact Microtronix..........................................................................................................2
E-mail ......................................................................................................................................2
Website ...................................................................................................................................2
Phone Numbers.......................................................................................................................2
Typographic Conventions............................................................................................................2
Introduction .................................................................................................................................4
Kit Contents ................................................................................................................................4
Overview.....................................................................................................................................5
Power Supply..............................................................................................................................5
Hirose Connectors.......................................................................................................................5
HSMC Connectors ......................................................................................................................8
Hirose DF13 – LVDS Loopback Cable.......................................................................................11
Hirose DF13 to MDR26M Camera Link Transmitter Cable .........................................................13
LVDS HSMC Daughter Card User Manual
Page 4 of 14
The Microtronix Quad Link LVDS Interface HSMC Daughter Card is targeted at the development of HD video systems incorporating LVDS interfaces. It is designed to interface video LVDS receivers and/ortransmitters to the Microtronix ViClaro III board using the HSMC expansion connector.
The key features of the board include:
Four Hirose DF13-40DP-1.25V connectors
Differential terminations on receive pairs
The Microtronix Quad Link LVDS Interface HSMC Daughter Card is includes the following hardware components:
Quad Link LVDS Interface HMSC Daughter Card (PN: 6253-01-01)
o Card mounting hardware
o Optional cables with Hirose mating connectors on one end and either Hirose or Camera Link (MDR26) connectors on the opposite end
Microtronix Quad Link LVDS Interface HSMC Daughter Card –Installation CD NOTE: The CD is not supplied when the LVDS card is purchased in conjunction with Microtronix ViClaro III Development Kit.
Introduction
Kit Contents
LVDS HSMC Daughter Card User Manual
Page 5 of 14
The Microtronix Quad Link LVDS Interface HSMC Daughter Cardcontains four Hirose DF13-40DP-1.25V connectors; two for transmit and two for receive. Each connector provides two links of five channels each. Each connector provides two clocks, one for each link (only one receive clock per connector supported by ViClaro III due to PLL requirements). The LVDS daughter board includes 100Ω differential terminations on all receive LVDS pairs.
A picture of the Quad Link LVDS Interface HSMC Daughter Card is shown below.
Figure 1: Quad Link LVDS Interface Daughter Card
The card contains only passive components and does not use any power.
The Microtronix Quad Link LVDS Interface HSMC Daughter Cardincorporates four Hirose DF13-40DP-1.25V for connecting the board to LVDS devices. J2 and J4 are for receiving LVDS data. Each signal pair connected to these headers is terminated with a 100 resistor. J3 and J5 are used for transmitting LVDS data. These signal pairs are not terminated as all Altera FPGA families support on-chip terminations for LVDS transmitters. The following tables describe their pin out, including the FPGA pin connection when the board is used on a Microtronix ViClaro III board on header J4.
Overview
Power Supply
Hirose Connectors
LVDS HSMC Daughter Card User Manual
Page 6 of 14
Table 1: J2 signals and pin assignments
ViClaro III Pin # Signal Name Pin # Pin # Signal Name ViClaro III
Pin #NC 1 2 NC
GND 3 4 GND
AD2 RXA_p0 5 6 RXB_p0 AC2AD1 RXA_n0 7 8 RXB_n0 AC1
GND 9 10 GND
AB2 RXA_p1 11 12 RXB_p1 AA4AB1 RXA_n1 13 14 RXB_n1 AA3
GND 15 16 GND
Y4 RXA_p2 17 18 RXB_p2 W2Y3 RXA_n2 19 20 RXB_n2 W1
GND 21 22 GND
W4 RXA_p3 23 24 RXB_p3 V4W3 RXA_n3 25 26 RXB_n3 V3
GND 27 28 GND
V2 RXA_p4 29 30 RXB_p4 U2V1 RXA_n4 31 32 RXB_n4 U1
GND 33 34 GND
U3 RXA_p5 35 36 RXB_p5 (clk_p) Y2U4 RXA_n5 37 38 RXB_n5 (clk_n) Y1
GND 39 40 GND
Table 2: J4 signals and pin assignments
ViClaro III Pin # Signal Name Pin # Pin # Signal Name ViClaro III
Pin #NC 1 2 NC
GND 3 4 GND
R2 RXC_p0 5 6 RXD_p0 T4R1 RXC_n0 7 8 RXD_n0 T3
GND 9 10 GND
L4 RXC_p1 11 12 RXD_p1 L2L3 RXC_n1 13 14 RXD_n1 L1
GND 15 16 GND
K4 RXC_p2 17 18 RXD_p2 K2K3 RXC_n2 19 20 RXD_n2 K1
LVDS HSMC Daughter Card User Manual
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GND 21 22 GND
J4 RXC_p3 23 24 RXD_p3 H4J3 RXC_n3 25 26 RXD_n3 H3
GND 27 28 GND
G2 RXC_p4 29 30 RXD_p4 F2G1 RXC_n4 31 32 RXD_n4 F1
GND 33 34 GND
E3 RXC_p5 35 36 RXD_p5 (clk_p) J2F3 RXC_n5 37 38 RXD_n5 (clk_n) J1
GND 39 40 GND
Table 3: J3 signals and pin assignments
ViClaro III Pin # Signal Name Pin # Pin # Signal Name ViClaro III
Pin #NC 1 2 NC
GND 3 4 GND
AE2 TXA_p0 5 6 TXB_p0 AE3AE1 TXA_n0 7 8 TXB_n0 AF2
GND 9 10 GND
AC3 TXA_p1 11 12 TXB_p1 AC5AD3 TXA_n1 13 14 TXB_n1 AC4
GND 15 16 GND
AB6 TXA_p2 17 18 TXB_p2 AA6AB5 TXA_n2 19 20 TXB_n2 AA5
GND 21 22 GND
Y6 TXA_p3 23 24 TXB_p3 W8Y5 TXA_n3 25 26 TXB_n3 Y7
GND 27 28 GND
V8 TXA_p4 29 30 TXB_p4 V6V7 TXA_n4 31 32 TXB_n4 V5
GND 33 34 GND
U6 TXA_p5 35 36 TXB_p5 R7U5 TXA_n5 37 38 TXB_n5 R6
GND 39 40 GND
LVDS HSMC Daughter Card User Manual
Page 8 of 14
Table 4: J5 signals and pin assignments
ViClaro III Pin # Signal Name Pin # Pin # Signal Name ViClaro III
Pin #NC 1 2 NC
GND 3 4 GND
M8 TXC_p0 5 6 TXD_p0 K8M7 TXC_n0 7 8 TXD_n0 L8
GND 9 10 GND
J7 TXC_p1 11 12 TXD_p1 M4K7 TXC_n1 13 14 TXD_n1 M3
GND 15 16 GND
P2 TXC_p2 17 18 TXD_p2 N4P1 TXC_n2 19 20 TXD_n2 N3
GND 21 22 GND
L7 TXC_p3 23 24 TXD_p3 J6L6 TXC_n3 25 26 TXD_n3 J5
GND 27 28 GND
M2 TXC_p4 29 30 TXD_p4 G6M1 TXC_n4 31 32 TXD_n4 G5
GND 33 34 GND
G4 TXC_p5 35 36 TXD_p5 D2G3 TXC_n5 37 38 TXD_n5 D1
GND 39 40 GND
Table 5 shows the pinout of the HSMC connector, along with the FPGA pin connection when the Quad Link LVDS Interface HSMC Daughter Card is used on a Microtronix ViClaro III board on header J4.
Table 5: HSMC Connector J1, signals and pin assignments
ViClaro III Cyclone III
Pin #Signal Name HSMC
Pin #HSMC Pin # Signal Name
ViClaro III Cyclone III
Pin #NC 1 2 NC
NC 3 4 NC
NC 5 6 NC
NC 7 8 NC
AE3 TXB_p0 9 10 TXA_p0 AE2AF2 TXB_n0 11 12 TXA_n0 AE1AC3 TXA_p1 13 14 RXA_p0 AD2
HSMC Connectors
LVDS HSMC Daughter Card User Manual
Page 9 of 14
AD3 TXA_n1 15 16 RXA_n0 AD1AC5 TXB_p1 17 18 RXB_p0 AC2AC4 TXB_n1 19 20 RXB_n0 AC1AB6 TXA_p2 21 22 RXA_p1 AB2AB5 TXA_n2 23 24 RXA_n1 AB1AA6 TXB_p2 25 26 RXB_p1 AA4AA5 TXB_n2 27 28 RXB_n1 AA3Y6 TXA_p3 29 30 RXA_p2 Y4Y5 TXA_n3 31 32 RXA_n2 Y3
Y10 NC 33 34 NC AA10NC 35 36 NC
NC 37 38 NC
NC 39 40 NC
T8 NC 41 42 NC T7M5 NC 43 44 NC L5
3.3V 45 46 12V
W8 TXB_p3 47 48 RXB_p2 W2Y7 TXB_n3 49 50 RXB_n2 W1
3.3V 51 52 12V
V8 TXA_p4 53 54 RXA_p3 W4V7 TXA_n4 55 56 RXA_n3 W3
3.3V 57 58 12V
V6 TXB_p4 59 60 RXB_p3 V4V5 TXB_n4 61 62 RXB_n3 V3
3.3V 63 64 12V
U6 TXA_p5 65 66 RXA_p4 V2U5 TXA_n5 67 68 RXA_n4 V1
3.3V 69 70 12V
R7 TXB_p5 71 72 RXB_p4 U2R6 TXB_n5 73 74 RXB_n4 U1
3.3V 75 76 12V
M8 TXC_p0 77 78 RXA_p5 U3M7 TXC_n0 79 80 RXA_n5 U4
3.3V 81 82 12V
K8 TXD_p0 83 84 RXD_p0 T4L8 TXD_n0 85 86 RXD_n0 T3
3.3V 87 88 12V
J7 TXC_p1 89 90 RXC_p0 R2K7 TXC_n1 91 92 RXC_n0 R1
LVDS HSMC Daughter Card User Manual
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3.3V 93 94 12V
R3 NC 95 96 RXB_p5 (clk_p) Y2R4 NC 97 98 RXB_n5 (clk_n) Y1
3.3V 99 100 12V
M4 TXD_p1 101 102 RXC_p1 L4M3 TXD_n1 103 104 RXC_n1 L3
3.3V 105 106 12V
P2 TXC_p2 107 108 RXD_p1 L2P1 TXC_n2 109 110 RXD_n1 L1
3.3V 111 112 12V
N4 TXD_p2 113 114 RXC_p2 K4N3 TXD_n2 115 116 RXC_n2 K3
3.3V 117 118 12V
L7 TXC_p3 119 120 RXD_p2 K2L6 TXC_n3 121 122 RXD_n2 K1
3.3V 123 124 12V
J6 TXD_p3 125 126 RXC_p3 J4J5 TXD_n3 127 128 RXC_n3 J3
3.3V 129 130 12V
M2 TXC_p4 131 132 RXD_p3 H4M1 TXC_n4 133 134 RXD_n3 H3
3.3V 135 136 12V
G6 TXD_p4 137 138 RXC_p4 G2G5 TXD_n4 139 140 RXC_n4 G1
3.3V 141 142 12V
G4 TXC_p5 143 144 RXD_p4 F2G3 TXC_n5 145 146 RXD_n4 F1
3.3V 147 148 12V
D2 TXD_p5 149 150 RXC_p5 E3D1 TXD_n5 151 152 RXC_n5 F3
3.3V 153 154 12V
D3 NC 155 156 RXD_p5 (clk_p) J2C2 NC 157 158 RXD_n5 (clk_n) J1
3.3V 159 160 Presence LED
LVDS HSMC Daughter Card User Manual
Page 11 of 14
The Hirose DF13 LVDS Loopback cable (PN: [811-DF1340) can be used to validate a LVDS Transmitter – Receiver interface. The cable is 18 minces long and uses twisted pairs for impedance matching and signal integrity. The cable connector is a Hirose DF13-40DS-1.25C which mates with the Hirose DF13-40DP-1.25V connector on the LVDS Interface board.
The pins assignments for the Hirose DF-13 LVDS Loopback cable are provided in the table below.
Table 6: Hirose DF13 LVDS Loopback Cable Pin Assignments
Hirose DF13 Connector Pin #
Hirose DF13 Connector Pin #
5 57 76 68 811 1113 1312 1214 1417 1719 1918 1820 2023 2325 2524 2426 2629 2931 3130 3032 3235 3537 37
36 3638 38
Note: Differential signal as connected using twisted pairs.
A picture of the Hirose DF13 LVDS Loopback Cable is shown below.
Hirose DF13 –LVDS Loopback Cable
LVDS HSMC Daughter Card User Manual
Page 12 of 14
Figure 2: Hirose DF13 LVDS Loopback Cable
LVDS HSMC Daughter Card User Manual
Page 13 of 14
The pins assignments for the 1 meter Hirose DF13 – MDR26M Camera Link Transmitter Cable (PN: [811-MDR26-1M) are provided in the table below.
Table 7: Hirose DF13 – MDR26-1M Camera Link Cable Pin Assignments
Hirose DF13 Connector Pin #
Camera Link Signal Name MDR26M Pin #
32 X0_n 2530 X0_p 1226 X1_n 2424 X1_p 1120 X2_n 2318 X2_p 107 Xclk_n 225 Xclk_p 9
14 X3_n 2112 X3_p 837 SerTC_n 735 SerTC_p 208 SerTFG_n 196 SerTFG_p 6
31 CC1_n 1829 CC1_p 525 CC2_n 423 CC2_p 1719 CC3_n 1617 CC3_p 313 CC4_n 211 CC4_p 1528 GND 1433 GND 139 GND 26
16 GND 1Note: Differential signal are connected using shielded twisted pairs.
A picture of the Hirose DF13 – MDR26-1M Camera Link Transmitter Cable is shown below.
Hirose DF13 to MDR26M Camera Link TransmitterCable
LVDS HSMC Daughter Card User Manual
Page 14 of 14
Figure 3: Hirose DF13 – MDR26-1M Camera Link Transmitter Cable
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