Micron Engineering ClinicFall ‘08 – Spring ‘09 Welcome to Micron Engineering Clinic Analysis and Optimization of Multi Gb/s Chip- to-Chip Communication

Micron Engineering Clinic Fall ‘08 – Spring ‘09

Welcome to

Micron Engineering Clinic

Analysis and Optimization of Multi Gb/s Chip-to-Chip Communication


Team Members

Documentation Lead Raheem Alhamdani - CE

Technical Leads

Bryson Kent - EEJordan Kemp - EELucas Loero - EE

Team LeadBen Meakin – CE


Introduction and Motivation for Modeling and Verification of Interconnects

Raheem Alhamdani

Documentation LeadComputer Engineer

[email protected]


Introduction

The Sponsor:

• Manufacturer of DRAM, Flash Memory, and Image Sensor Integrated Circuits

What Have They Asked Us To Do?

• Design a software application for modeling and verification of chip-to-chip interconnects


Introduction

What is Verification?

• Proving through tests and formal methods that a design does what it is intended to do

What are Chip-to-Chip Interconnects?

• Electrical systems for communication between two integrated circuits

hardwaresecrets.com


Motivation

Background

Memory and I/O Devices Operate Much Slower than CPU

Access to Off-Chip Resources is Expensive ~ 300 cycles- Usually Cycles are Wasted

Demand for Low-Power yet High-Performance- Can’t Have Wasted Cycles!

Goal: Speed Up Devices and Speed Up Interconnect


As Devices Move Towards Being Smaller, Faster, Lower PowerInterconnects Become Slower, Noisier, and Unreliable

Issues: Inter-Symbol Interference (ISI) Co-Channel Interference Timing Jitter Voltage Noise

Problem

Conventional Testing Methodologies are not Feasible or Sufficient


Eye Diagram

Voltage

Time

•What is an eye diagram?A useful tool for the qualitative analysis of signal used in digital transmission.


Eye Diagram

Time

Voltage

Voltage

Time

BitsSuperimposed

1 Unit Interval (UI)

How is it created?


Eye Diagram (Noise)

Time

Voltage

Voltage

Time

BitsSuperimposed


Bit-stream Voltage

Noise

What Causes Noise?

• Interference from neighboring wires (Co-Channel Interference)

• Electromagnetic Interference

•Link resistance, capacitance, and inductance


Eye Diagram (Jitter)

Time

Voltage

Voltage

Time

BitsSuperimposed


Bit-stream

Jitter

What Causes Jitter?

• Clock Variation (Skew)

• Reflection

• General Timing Uncertainty


Real Eye Diagram

Data Jitter

Clock Jitter

Signal Noise

Vref

Data Signal

Clock Signal

Vref Noise+

ReceiverSensitiv

ity

How to interpret it?


Solution

Our Objective is Not to Solve These Problems Through Better Design, but toProvide Designers with a Tool That Correctly Models and Verifies Interconnects With These Problems

Deliverables:

Cross Platform App with Graphical User Interface

Provide Worst-Case and Statistical Based Link Analysis

Spice Compatible

Correctly Model Co-Channel Interference and Tx/Rx Jitter


Project Documentation

Meeting minutes, Time-line, Progress Report , Presentations, Proposal and links are all on the team’s website: www.eng.utah.edu/~alhamdan/Micron/Micron.html

My Roles

Graphical User Interface and Software Development

GUISoftware skeletonPlotting code Code documentation


Team’s website


Meeting Minutes


Bibliography

B. K. Casper, M. Haycock, and R. Mooney, “An accurate and efficient analysis method for multi-Gb/s chip-to-chip signaling scheme”, in Digest of Technical Papers from the IEEE Symposium on VLSI Circuits, June

2002, pp. 54–57.

B. K. Casper , G. Balamurugan, J. E. Jaussi, J. Kennedy, M. Mansuri, “Future microprocessor interfaces: Analysis, design and optimization”, in Proceedings of the IEEE Custom Integrated Circuits Conference,

Sept. 2007, pp. 479-486.

P. K. Hanumolu, B. K. Casper, R. Mooney, G. Y. Wei, and U. K. Moon, “Jitter in high-speed serial and parallel links”, in Proceedings of the IEEE International Symposium on Circuits and Systems, May 2004, pp.

425–428.

Pavan Kumar Hanumolu, Bryan Casper, Randy Mooney, Gu-Yeon Wei, and Un-Ku Moon, “Analysis of PLL Clock Jitter in High-Speed Serial Links”, in IEEE Transactions on Circuits and Systems, November 2003,

pp.879-886


Questions?


Worst Case Verification of High Speed Interconnects

Bryson Kent

Technical Lead

Electrical Engineer

[email protected]


Introduction

•What is Worst Case analysis•Why is the Worst Case important•How to calculate the Worst Case•What are the results•Conclusion and implementation


Worst Case Analysis

•Summation of all negative effects•Good representation of what can happen if certain conditions arise•Verification of error free transmission •Classic analysis of 1 trillion bits

•(1*10^12 bits) * (10^-6sec) = over 10 days


Worst Case Eye Diagram

WC1 WC2 WC3

•Voltage Vs one period of time•Distortion sources add to close the eye•From the eye diagram we can calculate a system pass fail

Tim Hollis, Micron Senior Project Proposal

Pass/Fail


Inter-Symbol Interference

•Inter-Symbol interference is the main source of interference

•Data dependent jitter and Co-channel interference add to signal degradation



•C(t) = transmitter symbol response•P(t) = impulse response of the channel

Worst-Case Computation

•Worst case eye diagram due to Inter-symbol interference

•Worst case eye diagram due to Inter-symbol interference and cochannel interference

J. G. Proakis, “Digital Communication”, McGraw-Hill, 3rd Ed., 1995.B. K. Casper, M. Haycock, and R. Mooney, “An accurate and efficient analysis method for multi-Gb/s chip-to-chip signaling schemes”, in Digest of Technical Papers from the IEEE Symposium on VLSI Circuits, June 2002, pp. 54–57.


891 1091 1291 1491 1691 1891 2091 2291 2491 2691 2891 30910

0.5

1

Picoseconds

Vo

ltag

eWorst Case Eye Due to Inter-symbol Interference

Data-Rate = 10 Gb/s

-100 -50 0 50 1000

0.5

1

ISIpp

= 815.9948 mV

DDJpp

= 34.3117 ps

Picoseconds

Vo

ltag

e

Pulse Response

Pre-CursorCursor

Post-Cursor

Calculating the eye diagram

891 1091 1291 1491 1691 1891 2091 2291 2491 2691 2891 30910

0.5

1

Picoseconds

Vo

ltag


Data-Rate = 10 Gb/s

-100 -50 0 50 1000

0.5

1

ISIpp

= 815.9948 mV

DDJpp

= 34.3117 ps

Picoseconds

Vo

ltag

e

Pulse Response

Pre-CursorCursor

Post-Cursor

891 1091 1291 1491 1691 1891 2091 2291 2491 2691 2891 30910

0.5

1

Picoseconds

Vo

ltag


Data-Rate = 10 Gb/s

-100 -50 0 50 1000

0.5

1

ISIpp

= 815.9948 mV

DDJpp

= 34.3117 ps

Picoseconds

Vo

ltag

e

Pulse Response

Pre-CursorCursor

Post-Cursor

891 1091 1291 1491 1691 1891 2091 2291 2491 2691 2891 30910

0.5

1

Picoseconds

Vo

ltag


Data-Rate = 10 Gb/s

-100 -50 0 50 1000

0.5

1

ISIpp

= 815.9948 mV

DDJpp

= 34.3117 ps

Picoseconds

Vo

ltag

e

Pulse Response

Pre-CursorCursor

Post-Cursor

891 1091 1291 1491 1691 1891 2091 2291 2491 2691 2891 30910

0.5

1

Picoseconds

Vo

ltag


Data-Rate = 10 Gb/s

-100 -50 0 50 1000

0.5

1

ISIpp

= 815.9948 mV

DDJpp

= 34.3117 ps

Picoseconds

Vo

ltag

e

Pulse Response

Pre-CursorCursor

Post-Cursor

891 1091 1291 1491 1691 1891 2091 2291 2491 2691 2891 30910

0.5

1

Picoseconds

Vo

ltag


Data-Rate = 10 Gb/s

-100 -50 0 50 1000

0.5

1

ISIpp

= 815.9948 mV

DDJpp

= 34.3117 ps

Picoseconds

Vo

ltag

e

Pulse Response

Pre-CursorCursor

Post-Cursor

891 1091 1291 1491 1691 1891 2091 2291 2491 2691 2891 30910

0.5

1

Picoseconds

Vo

ltag


Data-Rate = 10 Gb/s

-100 -50 0 50 1000

0.5

1

ISIpp

= 815.9948 mV

DDJpp

= 34.3117 ps

Picoseconds

Vo

ltag

e

Pulse Response

Pre-CursorCursor

Post-Cursor



Results

•Calculated performance Vs given performance

-1 -0.5 0 0.5 1

x 10-10

0

0.2

0.4

0.6

0.8

1


Conclusion

•Worst case analysis is beneficial•Computation is pulse based analysis•User can define and add any distortion as desired•Results of worst case analysis match results of given test case


Questions?


Statistical Analysis ofElectrical Signaling

Jordan Kemp

Technical LeadElectrical Engineering

[email protected]


• Introduction

• How

• Why• What

• Summary


Introduction

• Worst Case Eye good for Pass/Fail Mask, but doesn’t give details

• Need for probability of error, rather than rigid “Pass/Fail”

Pass/Fail Mask


• Use channel impulse response, p(t), and transmitter symbol response, c(t)

Introduction

( ) ( ) ( )y t c t p t

• Find PDF (Probability Density Function) & CDF (Cumulative Distribution Function) of the channel output


Introduction

• Shows BER of transmitted data given timing uncertainty (data jitter, clock jitter) and voltage uncertainty (VREF, Rx sensitivity, ISI)

• Plot BER eye-diagram as a function of sample time, sample voltage, and probability of error


Why

• Trends Increase: Speed, Capacity Decrease: Form-Factor, Power, Cost All above decrease Signal Integrity

• Theoretically impossible to send error-free data

# errors

# transmitted bitsBit Error Rate (BER) =

( ) 0110101001101000

( ) 0110101 011010001

x t

y t

• Certain number of errors per number of bits sent specified by user/system

• Usually specified below 1

1 trillion

• Would require a 1 TRILLION bit simulation!


What

• Probabilistic data eye using channel impulse response, p(t), and transmitter symbol response, c(t) to find the PDF & CDF of the channel output

• What is a PDF? - Probability Density Function - Shows the probability that a specific value is likely to happen - Integrates to 1

• What is a CDF? - Cumulative Distribution Function - Shows the probability is less than

or equal to a specific value - Integral of the PDF


How (1)

1st Way (from *Casper paper):Recursively convolve 1UI

sample terms assuming equal probability of a

transmitted ‘0’ or ‘1’[0 -0.01] [0 0.59][0 -0.07][0 0.015][0 0.055][0 0.2][0 0.5][0 0][0 0.7](Each step scaled by ½ to account for P(0) = P(1) )

0.59

0.0

1UI

y(t)


How (1)

• VERY hardware intensive (must compute multiple convolutions)

• Must maintain certain amount of resolution, slowing computations down even more

• Very quickly run out of memory performing calculations

Problems:

[0 -0.01] [0 0.59] [0 -0.07] [0 0.015] [0 0.055] [0 0.2] [0 0.5] [0 0] . . . .

1.452 1 (no decimal resolution)1.452 1.4 (one decimal resolution)1.452 1.45 (two decimal resolution)……

delta function @ 1: [0 1 0 …] 0 1 2 . . .

delta function @ 1.4: [0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 …] 0 .1 .2 .3 .4 .5 .6 .7 .8 .9 1 1.1 1.2 1.3 1.4 1.5 . . .


How (2)

Implemented Method (modified from previous):

[0 -0.01] + [0 0.59]+[0 -0.07]+[0 0.015]+[0 0.055]+[0 0.2]+[0 0.5]+[0 0]+[0 0.7]

• Same points taken as before, but add instead of convolve

• Keeps track of locations of delta functions

• Keeps track of heights of each delta

• Plot locations versus heights


How (2)

-.01 0

Height = 0.5

0 .59

Height = 0.5

Height = 0.25

-.01 0 .58 .59

• [0 -0.01] [0 0.59] = [0 -.01 (0+.59) (-.01+.59)] = [-.01 0 .58 .59]

• Instead of convolving, proposed method adds & concatenates


Advantages:

• VERY quick

• Easy to implement

• Infinite precision (in theory)

How (2)


Summary

• Use channel impulse response, p(t), and transmitter symbol response, c(t)

( ) ( ) ( )y t c t p t

• Shows BER of transmitted data given timing uncertainty (data jitter, clock jitter) and voltage uncertainty (VREF, Rx sensitivity, ISI)

• Find PDF (Probability Density Function) & CDF (Cumulative Distribution Function) of the channel

• Plot BER eye-diagram as a function of sample time, sample voltage, and probability of error


Questions?


MODELING JITTER IN CHIP-to-CHIP COMMUNICATION

M. Lucas Loero

Technical Lead

Electrical Engineer

[email protected]


PRESENTATION OBJECTIVES

• Defining Jitter

• Problems caused by Jitter

• Modeling Jitter

• Receiver Jitter

• Transmitter Jitter

• Total Jitter


DEFINING JITTER

Time

Voltage

Edge location shifted

Ideal edge location

Jitter


PROBLEMS CAUSED BY JITTER

• Power supply and environment noise causes Jitter.

• Jitter can lead to:

• Time uncertainty

• Suboptimal sampling time

• Reduce noise margin


PROBLEMS CAUSED BY JITTER


• Model the effects of Jitter in high-speed serial links

• Serial links are used for high-speed chip-to-chip

communications

MODELING JITTER


MODELING JITTER

Serial Links

Transmitter generates a train of pulses

Transmitter clock Sampler

Decision circuit


MODELING JITTER

• Traditional approach to modeling jitter

• There is two main problems with this approached

• First, simulation time

• Second, difficulty simulating serial links


Receiver Jitter

Independent and Identically Distributed

Transmitted bits

Step responseChannel impulse response

Jitter sequence

MODELING JITTER


Calculated eye diagram Simulated eye diagram

MODELING JITTER


Worst-case receiver jitter

MODELING JITTER


Worst-case ISI Worst-case receiver jitter

MODELING JITTER

Worst-case receiver eye

Time

Voltage

Voltage

Time


MODELING JITTER

Worst-case receiver eye


Transmitted bits

Step response Channel impulse response

Jitter sequence

MODELING JITTER

Transmitter Jitter


MODELING JITTER

Worst-case transmitter Jitter


Worst-case ISI Worst-case transmitter jitter

MODELING JITTER

Worst-case transmitter eye

Time

Time

VoltageVoltage


MODELING JITTER

Worst-case transmitter eye


MODELING JITTER

Total Jitter

Transmitter JitterReceiver Jitter


MODELING JITTER

Worst-case total Jitter


Worst-case ISI Worst-case total jitter

MODELING JITTER

Worst-case total eye

TimeTime

VoltageVoltage


MODELING JITTER

Worst-case total eye


CONCLUSION

Voltage

Time


Questions?


Project Software Engineering, Development, and Results

Ben MeakinTeam Lead

Computer [email protected]

Micron Engineering ClinicSpring '09


Introduction

Open Eye : A Formal Verification Tool for High Speed Electrical Signaling

What is Open Eye?

• Provides Software Infrastructure Required to Deliver a Useful Verification Platform Based on Existing State-of-the-Art Methods

Presentation Outline

• Requirements and Objectives

• Software Architecture

• Graphical User Interface (GUI)

• Software Infrastructure

• Use Case

• Summary and Conclusions


Product Requirements

Cross Platform (Windows, Linux, etc)

Graphical User Interface

No Proprietary Software License (i.e. Matlab License)

Correctly Implement Worst-Case and Statistical Link Analysis

Pass Fail Mask and Data Eye Visualization

Selectable Transmitter and Receiver Jitter

Multiple Sources of Co Channel Interference

Spice Data File Input


Product Release Status

Feature Phase Status

Worst-Case Analysis Release

Statistical Analysis Testing 25%

Static Analysis Release

Basic Plotting Release

Advanced Plotting Development 50%

Jitter Modeling Debug 75%

Co-Channel Interference Testing 75%

File Input Release

File Output Development 75%

Graphical User Interface Testing 50%

Multi-threading Testing 75%

Documentation Development 50%


Design Goals

Portability

Extensibility

Usability

View


Object Oriented Design

Model

Data IO

Signal Analysis

Parameters

Static Data

StatisticalData

Worst-CaseData

Range

MathUtility

SignalModify

Open EyeApp.

Open EyeView

OtherGUI

Classes

View

Status Q

ModelControlData Structures


Graphical User Interface Features


Graphical User Interface Features Continued


Data I/O Features

Input Data from SPICE or Any Other Column Formatted Text File

Simulation Data Objects Save State to Text FilesNo Need to Rerun To View Data

Simulation Data Output to Matlab Format Text File


Mathematical Utility Features

Discrete-Time Convolution Function

Random Number Generation over Gaussian Distribution Assortment of Vector Operations

MathUtil

+ convolution(List, List):List+ getRandom(double):double+ max(List):double+ maxAt(List):int+ min(List):double+ minAt(List):int+ indexOfClosest(List,double):int+ extendTimeScale(List):List+ getTimeUnit(List):double


Signal Analysis Features

Static Signal Analysis (Naive Method)

Data Sequence Bits Superimposed To Form Eye Diagram


Signal Analysis Features

Worst-Case Signal Analysis (Formal Method)

Mathematically Generated Worst-Case Eye Diagram

Pass/Fail Based on User Defined Sampling Window

Statistical Signal Analysis (Formal Method)

Generates a Scatter Plot of BER Diagram

Formal Methods Consider Multiple Sources of CCI and Tx/Rx Jitter

SignalAnalysis+ WCData : WorstCaseData+ StatData : StatisticalData+ EyeData : StaticData

+ doWorstCase(double,double):void+ doStatistical(double,double):void+ generateEye(double):void+ computeCCI(List,List,List,int,int):void+ passOrFail(double,double,double,double):boolean


Performance Enhancement Through Multi-Threading

Sequential Part Concurrent PartExecution Time

Convolution for Channel 0

Convolution for Channel 1

Convolution for Channel N

Convolution: Yn(t) = convolution( Pn(t), Cn(t) ), n = channel

Requires Significant Execution Time for Large Data Sets

Can Be Done Concurrently For Each Channel on Multi-Process Machines


Use Case (Worst-Case Analysis)

C(t) – Transmitter Symbol Response

P(t) – Channel Impulse Response

Data Rate: 4 Gbps

No CCI, No Jitter

Worst-Case Eye with User Defined Sampling Window


Use Case (Static Analysis)

V(t) – Data Stream{0, 1, 0, 0, 1, 1, 0, 1, 0, 1}

Data Rate: 1Gbps

Random Voltage Noise

No Jitter Added

V(t) Periods Superimposed to Get Data Eye Diagram


Summary and Conclusions

What Has Been Accomplished?

First Application to Correctly Perform Worst-Case and Statistical Link Analysis in the Public Domain

Development of a Flexible and Efficient Platform for Formal Verification of Electrical Signaling Systems

Why Does This Matter?

• Easy Verification of Aggressively Optimized Designs

• Off-Chip Memory Access Bottleneck is a Growing Problem

• Open Source Application Stimulates Academic Solutions


Questions?

Documents

Micron Engineering ClinicFall ‘08 – Spring ‘09 Welcome to Micron Engineering Clinic Analysis and Optimization of Multi Gb/s Chip- to-Chip Communication