Microelectronics System Design for Chronic Brain Implants

ECEN 5007S. Johnson, V. Ganesan

11-07-02

Motivation

• Research in the area of nueronal signaling is constrained by the test electronics readily available.

• Large, inflexible neural probes are implanted into test animals, requiring bulky cabling configurations to connect to the recording equipment.

• Such a test setup hampers the test subject's movement and thus greatly changes the way in which the test subject would normally interact with its environment.

• This change in normal behavior effects the way in which they learn and in turn can skew desired test results.

• A proposed solution is to place the microelectronics used for recording neural signals onto a small chip, which rides on top of the mechanical probe.

• Such a device would be small enough to be implanted, and allow the test animal to recover from the surgery and soon after interact normally with its environment.

Key System Requirements

• No chronic external wiring - External wiring interferes with the natural movement and hence behavior of the test subject

• The probe must be able to "float" with the tissue in which it is implanted - The brain moves inside the skull, an implant that is rigid and anchored to the skull does not allow for such movement, hampering normal function.

• The electronics must be integrated with the mechanical probe - Proximity to the acquired signal helps keep noise low (short transmission path) and aids in a higher resolution of data.

• Low power consumption - Must keep power consumption low to minimize energy storage (battery) 1mW goal.

• Low power dissipation - Must keep power dissipation low to reduce heat load on tissue. (A rise in temperature of 0.5C causes stress in the tissue disrupting normal function, a 2C rise causes tissue death).

• Small size - Chip must be small so as not to interfere with normal function. For this application the area of tissue is 3mm2, and the mechanical probe and acquisition electronics must fit within a 1mm2 footprint.

System Description

Dual Module ApproachProbe Module

Analog Front End

LNA IA

Multiplexer

Configuration& Control

Power Mgmt

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ADCProbeInterfaces

Surface Module

UserInterface(wired)

Initiation Signal(wireless)

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.Demultiplexer

SignalProcess

SignalStorage

Configuration& Control

Energy Storage

Rcvr.Clock

Power Mgmt

ClockSerial Interface

• For the purposes of this project, the focus will be the Probe Module.

• The Surface Module is a larger chip where the majority of signal processing will take place. It is attached to the outside of the scull of the test animal where constraints of size, power consumption and power dissipation are not as great.

• The Surface Module provides an interface to the researcher to access data, charge the on-chip battery cell, and send simple control commands to the electronics.

• A flexible wire tether bundle would provide the interconnections between the two modules . The Surface Module is shown only for completeness of the system.

Signal Acquisition

The signal acquisition portion of the Probe Module is comprised of an analog front end, a multiplexer, and an ADC. The analog front end interfaces with sixteen probe lines, and amplifies the incoming neural signals. The first amplification stage is the LNA (low noise amplifier) and is shown below.

Modulator Modulator

Rail-to-Rail OTAsupply=1.8V

Selective Amplifier2nd order Gm-C BPF(fc tracks fchop)

LPFVsig Vout

LNA (Low Noise Amplifier)

• An AM (amplitude modulation) block which shifts the low frequency, low voltage signal up in frequency above the flicker noise of the preamp,

• A low noise pre-amp

• A Selective Amplifier (acting as a bandpass filter with gain, which filters out the low frequency noise component, leaving the modulated signal component)

• A second AM block which demodulates the original signal back to its baseband frequency.

• An LPF filter which filters out the additional, high frequency, modulation components.

• The second amplification stage is the Instrumentation Amplifier. It's purpose is to further amplify the desired neural signal to a level required by the digital processing electronics, or ADC block.

Low Noise Pre-Amplifier and Selective Amplifier

• The Selective amplifier is realized by 2 amplifiers low noise rail-to-rail preamplifier followed by a 2nd order band pass (GmC) filter.

• The pre-amp amplifies both the noise and modulated input signal. It requires a minimum corner frequency equal to the chopper frequency, and a high CMRR

• The Gm-C (bandpass) filter reduces residual offset from charge injection of input modulator. It requires a matching oscillator to maintain a constant Gm.

Low Noise Pre-AmplifierMagnitude Plot Phase Plot

Gain = 26dbCorner Frequency (-3dB) = 80kHz

Matching Oscillator

• The Gm-C filters are sensitive to parasitic capacitances due to lack of low impedence nodes and this causes the variation in the time constant of the filter

• Frequency drift causes Gm to shift. Want a constant Gm value

• To get rid of the time constant variation we track it with on-chip chopper freqency.

• Tracking with off-chip reference clock will cause more variations due to temperature and process parameter changes

Bandpass Filter Magnitude Plot Phase Plot

Center Frequency = 40kHz

Multiplexer

• Once the signal is amplified, it is multiplexed with the other amplified probe lines.

• The multiplexer's purpose is to sample each of the lines at a minimum of 25kHz.

• This satisfies the Nyquist criterion where the sampling rate must be at least twice that of the signal being sampled.

• For this application, the neural signal bandwidth is less than 5kHz. Since the system can obtain good data from up to sixteen probes at one time, the switching frequency of the multiplexer must be a minimum of 400kHz to achieve a 25kHz sampling rate for each line.

• The ADC is the final block of the signal acquisition section of the Probe Module. It digitizes the multiplexed data stream for transport to the Surface Module.

Configuration and Control

• Upon initial power-up and data acquisition, the researcher will determine which probe signals are useful.

• The researcher sends a code to the Configuration and Control block on the Surface Module, telling it which channels are good.

• The "good" channel information is sent as a binary stream to the Configuration and Control block on the Probe Module. The Control block then powers down the amplifier stages whose signals are too weak or non-existent, thus saving on power consumption and lowering power dissipation.

• The multiplexer is directed to sample only those lines that are powered. The control block will be in control of the sequencing of the amplified probe lines, and the frequency at which they are sampled.

Project Scope

• The Analog Front-End will be composed of at least four input lines from the mechanical probe.

• A minimum signal level for each of these lines is expected to be 100uV. The circuit begins with all probe amplification lines powered on.

• The clocking for the modulator blocks is set to achieve a modulation frequency of approx. 40kHz.

• The Configuration and Control block will be given a command (binary bit stream) that it must interpret and power down those amplification stages that are not needed, shutting off particular probe lines. It then relays the sequence of probe lines to be sampled to the multiplexer.

• The switching frequency of the multiplexer is set knowing the number of probe lines to be sampled (25kHz minimum sampling per line).

• The output from the amplified lines is expected to have a 60dB voltage gain (100uV to 100mV). Power consumption for the system is targeted at 1mW.

System Overview - Ideal LNAsAnalog Front End (Chopper Amplifier Circuitry)

2 bit Binary Ctr

Enable Bits (Shift Register) Clk Enable

100kHz Clk

Ctr Init(Pulse)

Multiplexer

Mux switch control logic

Mux switches and output bus

Probes

00 01 10 11

Binary Counter

Simulation Results

LNA 2 (400Hz sinewave)

LNA 0 (100Hz sinewave)

LNA 1 (200Hz sinewave)

LNA 3 (800Hz sinewave)

All LNAs enabled

sw 0 - onLNA 0 signal

sw 2 - onLNA 2 signal

sw 1 - onLNA 1 signal

sw 3 - onLNA 3 signal

Simulation Results

LNAs 0 and 2 enabledLNA 2 (400Hz sinewave)

LNA 0 (100Hz sinewave)

LNA 1 (200Hz sinewave)LNA 3 (800Hz sinewave)

Chopper Amplifier

Modulator

SimulatedNoise

Amplifier

BPF

Demodulator

LPF

InputSignal

Chopper Amplifier

System Overview - CHopper

CHopperAmplifier(LNA 0)

SimulatedNoise

ModulatorClocks

InputSignal

Simulation Results

All LNAs enabled

CHopper LNA 0(4.5kHz sinewave)

LNA 3 (800Hz sinewave)

LNA 2 (400Hz sinewave) LNA 1 (200Hz sinewave)

CHopper LNAbefore and aftermultiplexer