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MICROELECTRONICS ACTIVITY
V B CHANDRATRE
Head Micro Electonics Sectionand
Project Manager CMEMs ECIL Electronics Division
Activities
• ASIC DESIGN FULL CUSTOM /MIXED
• TECHNOLOGY DESIGN (PROCESS/DEVICE/SENSOR)
• HYBRID MICROCIRCUITS
• DATA ACCQUSITION (CORE STRENGTH HW/SW)
• MEMS DESIGN
• DEVICE MODELLING AND PDK DESIGN KIT DEVLOPMENT
Facilities
CAD TOOLS : ASIC /HMC /MEMS DESIGN
TCAD TOOLS : TECHNOLOGY DEVELOPMENTPACKAGING TOOLS SEMICONDUCTOR PARAMETRIC MEASURMENT MODELLING ATE IC TESTING: CUSTOM BUILD
EDA CENTRE
10 SUN WORK-STATIONS 3 fast IBM PC lic serverMentor Graphics HDL flow FPGA/ASIC flow (ModelSim,
Leonardo)Full Mixed mode HDL/analog/glue logic simulation support.Full custom/ std cell ASIC backend layout tool SCL C1S/D design kit in Mentor Graphics Tanner Tools , 0.7/0.35/0.5SiGe , SITAR design KIT. ECIL CUSTOMER ID
NEW ADDITIONS : COMPUTING CLUSTER 16GB RAM 1. SUNFIRE V440 QUAD CPU SUN WORKSTATION : 2nos 2. QUAD XEON PROCESSOR WORK STATION : 2Nos 3. HP IBM PC workstations 2NOS CADENCE, MENTOR, COVENTRE, SOFTWARE
SUNFIREV440 Sparc Solaris 8Each QUAD processor 16Gb
QUAD XEON preprocessor16 GB MEM LINUX /Win
Mentor Graphics & cadence License servers WIN XP /Scientific Linux 3
10/100 LAN
COMPUTING SETUP
SUN ULTRA 10 [4] / BLADE [6] Solaris 8
~~ thin clients in new setup for lowering power consumption minimization & laptops for personal use
Packaging Lab at CMEMS
Facilities:• Manual Epoxy / Eutectic die bonder• Semi-automatic Wire bonder• Flip chip bonder• Wire pull tester• Plasma cleaner• Curing furnace
Upcoming Facility
CMEMS TCAD Lab Facilities:
•A versatile structure editor for specifying device geometries.
•Semiconductor process simulation tool, having support for Si, SiGe, strained Si, SiC, GaAs and SOI technologies.
•Semiconductor device simulation tool, having support for BJT, CMOS, BiCMOS, HBT, APD, FinFET, power devices, CCDs, solar cells etc.
•An efficient framework for seamless integration of data across the above mentioned tools
Upcoming Facility
Detector & technology development
SILICON DETECTORS
Silicon strip detectorsPIN diode detectorsPhotodiodesSilicon Drift Detectors
Applications: Radiation monitoring, Nuclear Physics & High Energy Physics experiments
CMS Preshower Detector
End caps of CMSdetector will have 4300 silicon strip detectorscovering area ofabout 17 m2 BARC is
delivering 1000 detector modules forthe CMS preshowerWeight -12500 T
Dia- 15mLength – 21.5mMagnetic field – 4 Tesla
Strip Detectors for CMS Experiment at LHC, CERN
Silicon detectors produced by BARC will cover an area of 39,000 cm2 in the CMS detector of LHC
Wafers designed and fabricated during various stages of development
1 2 3
Detector module
Strip Detector Specifications
Electrical
High breakdown voltage Breakdown voltage for all strips >= 300V/500VLow leakage:Total current of all strips <= 10 μA at 300VUniformity of all strips: Maximum 1 strip with leakagecurrent> 5 μA at 300V
Geometrical
Tight control over dimensionsLength 63.0 +- 0.1 mmWidth 63.0 +0.0, -0.1 mm
Silicon Drift Detectors (SDD) Expected Resolution ~100 eV (PIN diodes: ~2keV)
Low anode capacitance without reducing detector size SDD device and process development and integration of JFET on the detector completed Under fabrication in BEL
Layout of SDD on Wafer
SDDs
JFETsSDD Array
ASIC AND HYBRIDS
Critical for Total Channel Noise ~ 100 e- @ 6us shaping time
A novel scheme (Adaptive Bias) for Large
Linear Feedback Resistance, ~3G
to reduce noise Sizing optimization
allows low noise Radiation hard design to be implemented
Front end for SDD ASIC new concepts…
Linear resistor w/l < 0.1 ~ 0.01
DETECTOR(S) FROM BEL
Mixed full custom CMOS ASIC MPW: SCL process C1D 1.2u
OCTAL Charge PreampOCTPREM
8 CHANNEL SILICON STRIP PULSE PROCESSOR. SPAIR
FRONT END DOSIMETER ASIC. CODA
8 CHANNEL CURRENT PULSE PREAMPLIFIER MICON
High dynamic rangeFOR fission Fragmentscharge particle array
NUCLEARINSTRUMENTS
X-RAY/GAMMA RAY IMAGING MEDIUM DYNAMIC RANGE
RADIATION MONITORINGINSTRUMENTS
Octal Pre-amplifier ASIC
Die Area: 2.4 x 1.8 mm2
CHARGE GAIN 1-0.5 V/cC FALL TIME 100/50 uS LINEARITY 1 –0.5% NOISE 400e- SUPPLY 2.5V DRIVE 50 OHMSPOWER DISSIPATION 0.9mW OPEN LOOP GAIN 73dBPHASE MARGIN 60UNITY-GAIN-BANDWIDTH 45MHz
CODACo-chip for Dosimeter Application
SPAIR
MICON
Error amp
ref
in
I to V & SHAPER/
Buffer
out
bias
FICON
KEY FEATURESLEAKAGE CURRENT COMPENSATION
IDEAL FOR PROPORTIONAL CHAMBERS,GEM, PMTS
50 NS PEAKING TIME1800 e RMS noise
8 CHANNELS WITH SERIAL ANALOG READOUT
Indiplex and Singleplex ASICS Sub-micron 0.7u CMOS process
INDIPLEX: 16 channel pulse processing ASIC comprising CSA, PZ-block & Semi
Gaussian shaper.
SINGLEPLEX: Single pulse processing channel ASIC similar to INDIPLEX
SINGLEPLEX
High Dynamic Range (+/- 600fC) Low Noise with Low Noise Slope (600e @0pf , 7e/pf Noise slope)Output Signal Swing +/-2V Active DC pedestal cancellation.Optimized for Proportional pad detectors made BY VECC for ALICE experiment at CERN.
Block Diagram-Single Channel
CSA DCON SHAPER
DC-CAN
T&H+
-
Input
Charge SensitivePre-amplifier
De-convolution
Active Pedestal Cancellation
Track & Hold
Anu-Shikhar ASIC : CMOS Peak Detect & Hold Circuit With SOC Output Logic
Salient Features :* Single shaper & amplifier stage at the input with adjustable gain.* Minimized Pedestal due to Base Line Restoration.* Reduced Charge Injection by using Rectifying Current Mirror in place of diode in Peak Detector, also providing complete compatibility with standard CMOS process.•Built in Linear Gate for pulse pile-up rejection.
• Dynamic Pedestal correction ,
• check new concept
OTA Buffer
RCM
VSS
VDD
Shaper &Amplifier
Base Line Restorer
IN
Peak Detector
Dump Current
WindowComparator& Control
Logic
SOC
Anu-Shikhar ASIC
LLD ULD
Anu-Shikhar ASIC ( Pulse peak detector )
Peak Detect & Hold Circuit with “Start Of Convert” generation Logic for Nuclear ADC. Specifications
Dynamic Range -300mV to -1.8V Power supply +/- 2.5VPower Consumption 36mWDroop Rate 0.13V/s (Simulated)Die Size & Package 3.3 X 3.3 mm2 ; 44-pin CLCC
Anu-Shikhar:21/02/06
y = 1.0146x - 0.0082
-2.5
-2
-1.5
-1
-0.5
0
-2.5 -2 -1.5 -1 -0.5 0
in pulse
PD
_o
ut
Series1
Linear (Series1)
Nuclear CMOS ADC for Portable Spectrometer NuCAPS) ASIC
Design Specification :• Adjustable Resolution 8/10/12-bit
• Frequency of Operation External : 50MHz, Effective : 100MHz
• Conversion Time 2.56/10.24/40.96us
• Power Consumption 32mW
• Input Dynamic Range 20mV-2V(100/1)
• DNL 1% of LSB
• Die Size 3.5mmX3.5mm
GTD_CLK
Pedestal Adjust & BLH
Linear DischargeSource
Window Comp &
Control Logic
Gray Counter
Shift Register
I/P
D0-D11
SROUT
CLK
SOCDischargeCurrent
Peak Detect & Hold Ckt
OTA Buffer
RCM
VSS
VDD
SR CLK
Transient Analog Waveform memory @ 500MS
High-Speed Analog Waveform Sampler128-cell analog waveform sampler with sampling rate of 500MHz.Facilitates High resolution digitization at High
Sampling Rates.
Digital DELAY LOCK LOOP BASED
2 GHz design in progress
IN PIPELINE ………..
• TDC DLL (digital delay lock loop) based
Fast Comparator (Td & Tr)• Si PMT & APD • Radiation Hard Electronics (design & process ??)Waiting for the facility to be
UP
ASICS in 0.35 /.5 SiGe submicron
Extended & closed gate radiation hard MOSFET
HYBRIDS …. Production mode
CHARGE SENSITIVE AMPLIFIER BMC15211V/PC GAIN 2 keV NOISE FET EXTERNAL
O/P VOLTAGE SENSE AND LOAD CURRENT MEASUREMENT CIRCUITRY
ERROR AMPLIFIER OVERLOAD / OVER VOLTAGE PROTECTION CIRCUITRY AND SHUT DOWN LOGIC
HIGH VOLTAGE HYBRIDS for Grace Experiments
INVERTER DRIVER AND SHUT DOWN CIRCUITRY
VOLTAGE MULTIPLIER
Use in CAMAC/NIM Modules
TIME TO AMPLITUDE T.A.CHYBRIDS FS 500NS-10U FS 5V RESOLUTION 75PS @ 500NS FS
FAST PULSE AMPLIFIER Tr/Tf < 2NS@2V 50 OHMS GAIN 10 O/P DC STABILIZED (HIGH COUNT RATE)
Peak stretcher for 8K Nuclear ADC
Hybrids & ASIC ….
Indian neutrino Observatory Gas RPC Fast Preamp family tr 1.5 ns… 27,000 Qty requirement
Low power pulse channels for portables designs.
“Singleplex” ASIC in HybridFor Neutron Monitors
Trans-impendence Preamp current pulse applications
ASIC IN HYBRIDS !
Many Hybrids have High Production VolumesUsers NSC, TIFR, VECC, CAT BARC, etc~ 5 cr account
THANK YOU
Email : [email protected]
Ack: Menka Tewani, Anubha Tewari, Vangnayee Sharma Nidhi Gupta , Sudheer M , R S Sastrakar, Viashali S
& P K Mukhopadhayay
New facility :CMEMS
GROUND FLOOR• Device Characterization, modeling & ATE • Packaging laboratory
FRIST FLOOR• IC design Software for VLSI (VLSI EDA LAB)• TCAD Lab • Embedded development & testing System LAB• Auxiliary facilities