Meyer Burger welcomes the delegates to WRETC

Are your ready for the next solar wave ?

Passionate about PV

«We will shape the future energy mix by combining leading technology with the infinite power of the sun .»

«We will further develop the photovoltaic, semiconductor and otherhigh-end niche markets using both new and exisiting technologies.»

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From ingot to solar module to complete BIPV energy system

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PV will play a key role in a sustainable future mix

Potential : 2050 scenarii according to IEA

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Learning curve

Source: ISE, MBT4

Cumulative installed capacity [GWp]

d [µm] = 400 300 200 100 50

ηcell [%] = 10 15 18 20 22 25

[€/Wp]

100

10

1

1980

1990

20002004

110-210-310-4 102 10310-1 10

2007

4

20122020

80% experience curve:cost reduction appr. 10% pa.But 2012: 60% in one year-> 6 years in advance

60%

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0.3

0.6

0.9

1.2

1.5

2010 2011 2012 2013 2014 2015

Modul prices Modul cost

Solar modules cost/price development

Source: PVinsights & Management estimates.Note: Average price for end-user for installed on-roof systems up to 10 kWp.

Difficult market environment forcell and module manufacturers

– Price decline in solar modules puts enormous pressure on module manufacturers – however, it is necessary to reach and keep grid parity

– Cell and module manufacturers still cautious on undertaking any major investments– Cost-/price ratio disadvantage of solar modules expected to reverse

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profit

US$/Wp

E E E E

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PV Industry Drivers

Cell & module efficiency,yield, uptime, TCO

Performance ratio,longevity, BOS

LCOE =Total life cycle cost

Total life cycle energy production

TCO = Total cost of ownership LCC = Life cycle costOEE = Overall equipment effectivenessVDMA 34160 : 2006-06; SEMI E35, SEMI:E 79

BOS = Balance of systemPR = Performance ratio

Solar systemsMono- /Multi c-Si Ingot/Wafer slicing Solar cells Solar modules

$Wafer

$Wp

$kg

$Wp

$kWh

1 2

MES automation system

4

3

Cus

tom

er a

nd g

loba

l ser

vice

s (tr

aini

ng, r

amp

up, m

aint

enan

ce)

Cus

tom

er a

nd g

loba

l se

rvic

es (f

eedb

ack)

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Material UtilizationThin Wafer / Wire

Yield

>80%>95%

>90%Line UtilizationYield Improvement

WaferLine CellLine

High efficient cell technology

3 strategic initiatives

Disruptive wafering technology

Diamond coated, Ni plated

Combine best in class wafering

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Heterojunction – more power persurface and more yield at hightemperatures

Thin-filmLow efficiency

High harvesting factor in hot climates

High BOS+ =

HJT TechnologyHigh efficiency

High harvesting factor in hot climates

Proven process steps

Crystalline technologyhigh efficiency

Proven, reliable technology

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Standard process MB-HJT process

CZ :18,5% MC: 16,8-17%

CZ: 18,5%-19% MC: 17%-18%

CZ n-type: 20~23%, potencially to reach even 24% in soon future

Selective Emitter process

TextureDoping / Diffusion

PSG Etch

Firing

Test & Sort

Print Rear Side

AR Coating

Print Front Side

Texture

a-Si Front/ Rear Side

Test & Sort

TCO / Metal Rear Contact

Print Front Side

Curing

Edge Isolation

TextureDoping / Diffusion

PSG Etch

Firing

Test & Sort

Print Rear Side

AR Coating

Print Front Side

Edge Isolation

Additional ???

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Reduced complexity withMB-Cell-Technologies

Additional ???

Additional ???Additional ???

AlOx layer

SiNx layer

Laser openings

Al Screen print Local Al-BSF

p-type wafer

Texture

Emitter

SiN layerFS Metallization

Si material

TextureDoping / Diffusion

PSG Etch

Firing

Test & Sort

Print Rear Side

AR Coating

Print Front Side

Edge Isolation

MB-iPerc upgrade

AlOx passivation layerSiNx Capping layer

Laser contact opening

Low temperature(< 250°C) processesReduced complexity

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Smart Wire Connection 5% higher power output10% higher energy yield

Rays descending on a bus bar tabbing (left) and on a round wire (right). The wire can be divided into three regions: Black arrows indicate the descending rays, green rays will reach the surface of the cell and red rays will not reach the surface.

Source: Stefan Braun, University Konstanz

• Highly effective front side without shading by bus bars• Higher sensitivity in regard of partial cell shading • Higher light efficiency based on the better light trapping• 80% less silver consumption• Route to very thin wafers

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PECVD

PECVD

SCREEN PRINT

CHARACTERIZATION

Diamond wire wafering-> thinner wafer -> lower costs

High efficiency-> lower system cost (BOS)-> independent of wafer thicknessOnly 6 process steps-> low COOTemperature coefficient-> higher energy yieldBifacial -> higher energy yield

TCO layer and wafer thicknesssuitable for SmartWire-> 80% less silver, -> higher energy yield-> higher efficiency-> longevity-> microcrack resistent-> less sand dust sensitive

Adapted test metrology-> high cap cells-> BB0-> dragon back-> PED (Chipping)

Single wafer tracking

HJT cell

texture + surface

preparationi/n Si

i/p Si

Front contact

Back contact

contacting

test & sort

WET

PVD

PVD

2

1 31

2

3

4

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MB technology road map at a glance

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Achievements – TemperatureCoefficient

-0,20 %/K on Cell level!

-0,22 %/K on Module level!

Excellent Temperature Coefficient certified by Fraunhofer ISE CalLab and TÜV Rheinland! Mey

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DAMPHEAT

1000hIEC

2000h 5000h 8000h

MB HJT -0.7% -1% -1% -8%

Even after 5000 hours of Damp Heat testing Meyer Burger HJT modules still stable without power losses.Fully compatible with IEC conditions (< 5% power loss)Even after 8000 hours damp heat still working with only 8% power lossHigher longevity

HJT – SmartWire TechnologyDamp Heat Test

Damp Heat Testing up to 8000h (8 x IEC) !

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We think in material-Process flows& act on technologies

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1 GW-fab 160MW cluster

AlOx layerSiNx layerLaser openings

Al Screen printLocal Al-BSF

p-type wafer

Texture

EmitterSiN layer

FS Metallization

Si material

Latest single technologies

Fab-level Material-Process flow Technology

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