meeting from Mai 10th at ETHZ

ArgonTube electronics

• Charge amplifier or linear amplifer ?

• Front end module

10.5.2006 Max Hess

Signal pulse width & charge in one pad in function from the trace angle

p = 10 mm

trace

d

pad

s pulse width: tp = d / vdrift = p / (vdrift tan )

signal charge: QS = Qnom p s = Qnom p / sin

vdrift

signal current: IS = QS / tp

Pad dimensions: 10 mm x 10 mm

vdrift = 2 mm/s @ Edrift = 1 kV/cm

LEM Gain = 100

1 MIP produces 6000 e- in LAr

Qnom = 100 fC/mm

10.5.2006 Max Hess

Values for simulation

p = 10 mm

trace

d

pad

s

d[mm]

s [mm]

tp

[s]

QS

[pC]

IS

[nA]

0.09° 600.0 600.1 300.00 60.01 200

4° 143.0 143.4 71.68 14.34 200.6

10° 56.0 57.6 28.00 5.76 206

30° 17.3 20.0 8.65 2.00 23145° 10.0 14.1 5.00 1.41 282

60° 5.7 11.5 2.85 1.15 403 * 90° 0 10.0 50.10- 3 1.00 20. 103

vdrift

* therotical: tp 0 and IS ∞

10.5.2006 Max Hess

Scheme for simulation

Cf

Rf

Vout

Vout BW

10.5.2006 Max Hess

Ideal charge amplifier

Uout = 85 V

Qs (pC) | 1.00 | 1.41 | 5.76 | 14.34 | 60.01

1 pF / 100 G = 2 ms

Qs = Iin • tp = Vout • CF

= (300 V / 5) • 1 pF = 60 pC

Gain Opamp = 5

10.5.2006 Max Hess

Prototype ETHZ

1 pF / 470 M = 94 s

Vout = 85 V

(Vout without Rf = 300 V)

Vout = 6.55 V

10.5.2006 Max Hess

Qs (pC) | 1.00 | 1.41 | 5.76 | 14.34 | 60.01

Reduced output voltage

30 pF / 15 M = 90 s

Vout = 2.8 V

10.5.2006 Max Hess

Qs (pC) | 1.00 | 1.41 | 5.76 | 14.34 | 60.01

Shorter time constant

15 pF / 15 M = 45 s

Vout = 3.0 V

Vout = 0.42 V

10.5.2006 Max Hess

Qs (pC) | 1.00 | 1.41 | 5.76 | 14.34 | 60.01

Linear amplifier

1 pF / 15 M = 3 s

Vout = 3.0 V

tp = 300 s

Qs = Iin • tp = (Vout / RF) • tp

= (3V / 15 M) • 300 s = 60 pC

10.5.2006 Max Hess

Qs (pC) | 1.00 | 1.41 | 5.76 | 14.34 | 60.01

Linear amplifier with bandwith limitation

2 pF / 15 M = 6 s

10.5.2006 Max Hess

Vout = 3.0 V

Qs (pC) | 1.00 | 1.41 | 5.76 | 14.34 | 60.01

Linear amplifier with bandwith limitation (detail)

2 pF / 15 M = 6 s

without BW limitation

BW limitation = 500 kHz ( = 0.3 s)

BW limitation 350 kHz two RC ( = 0.3 s) serial

10.5.2006 Max Hess

Qs (pC) | 1.00 (short signal)

Wath‘s the best solution ?

10.5.2006 Max Hess

• physical parameters• LEM (pad dimensions, gain min / max)• needed signal range (signal / noise, ADC resolution)• off line calculation (signal fit)• •

Block Diagram for analog path

+-

+- +

-

-+

UPRE

Charge amplifier

-US

+US

Shaper

+-

-+

offset

UADC

DAQ analog input stage

ADCCF

RF

CD

CI

RD

RPZ

RI

RI

RI

RI

RI = 1k Twisted pair flat cableshielded

first idea presented in the last meeting

10.5.2006 Max Hess

Front end module

analog in

ADC

serial link: 2 wire LVDS or optical

REG

COUNTER

MUX16:1

1

ld

12

ADC REGld

1 12

5 clk

40 MHz

12

41:16

Clk = 20 MHz

sampling rate = 1 MS/s

SERIALIZERDS92LV16

DAQ module

DESERIALIZERDS92LV16

16

FPGA

AMPL

AMPL

32 channels

Front end module

2

system clk 40 MHz

POWER

consumption 20W

2 x 24VAC

10.5.2006 Max Hess

ADC121S101