3D Wireless Network‐on‐Chip Architecture with interlayer cooling

‐‐Md Shahriar Shamim & Fernando Cueva

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Overview

• Introduction• Multi‐core chip• Network‐on‐Chip• 3D NoC

• Thermal Challenges• Why 3D Wireless?• Proposed Architecture• Results• Conclusion

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Multi‐core Chips: A Necessity• Need for explosive computational power• Consumer/Entertainment 

Application• Scientific Application

• Increasing clock frequency is not possible as it increases power dissipation

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Solution: Core level Parallelism,distribute tasks to multiple cores 

Challenges: Interconnection of Cores

• Traditional Interconnectarchitectures are not scalable

• Delay limit number of cores

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Solution: Scalable interconnect infrastructure for communication

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Network‐on‐Chip (NoC)• Packet based on‐chip network

• Route packets, not wires –Bill Dally, 2000.• Dedicated infrastructure for data transport

• Decoupling of functionality from communication• A plug‐and‐play network independent of the cores

High-bandwidthmemory interface

High-performanceARM processor

High-bandwidthARM processor

DMA Busmaster

BRI

DGE

UART

PIOKeypad

TimerAHB APB

NoC infrastructureAMBA bus: ARM

Multiple publications in IEEE ISSCC, 2010 from Intel, IBM, AMD, and Sun Microsystems show that multi-core NoC is a reality5/6/2015 5

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•Limitation of Wireline Interconnect•Multi‐hop wireline communication

• High Latency and energy dissipation 

source destination

-core

-NoC interface

-NoC switch

80% of chip power will be from on-chip interconnects in the next 5 years – ITRS, 2007

Problem with Traditional wire Interconnect

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WirelessInterconnects

Optical Interconnects

Three DimensionalIntegration

Goal: High Bandwidth + Low Energy Dissipation

Emerging Interconnect Technologies

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3D Integration• Stacking multiple active layers• Heterogeneous integration• Higher connectivity & less hop count High

bandwidth• Shorter average path length Lower Power

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• Pavlidis et al., “3-D topologies for Networks-on-Chip”, IEEE Transactions on Very Large Scale Integration (TVLSI), 2007.

Challenges• High power densities• Thermal issues

• High temperatures• Hotspots• Limited ability to extract heat only from top or bottom

layer

Micro‐channel based Sophisticated Cooling Layer• Microchannels between active layers circulating with chilled fluids

• What about TSVs?

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• pumping liquid can cause extreme pressure drops across the cooling layer ‐‐> structural instability.

• Complex manufacturing process as the TSVs and micro‐channels will co‐exist between the cooling layer.

• Longer TSVs ‐‐> Higher delay and power dissipation 

SABRY et al. Energy-Efficient Multiobjective Thermal Control for Liquid-Cooled 3-D Stacked Architectures. Trans. Comp.-Aided Des. Integ. Cir. Sys. Vol:30, Issue:12, page(s): 1883-1896

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What should we do?

But Photonic interconnect also requires dedicated physical layout like TSVs..

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Can incorporating another emerging interconnect technology fix these problems?? Maybe Photonic???Wireless?

What about wireless?? It does not need any physical interconnect layout. Hmm, it can alleviate the height limitation of the cooling layer.. 

Wireless Interconnect• Use of on‐chip wireless links

• Single Hop Shortcut• Reduce latency and energy 

dissipation in communication• No physical interconnect layout is 

necessary• Wireless port/wireless interface (WI) 

consists of transceiver and antenna• Antenna Technology:

• Metal zigzag antennas (mm‐wave) are CMOS compatible

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J. Lin et al., “Communication Using Antennas Fabricated in Silicon Integrated Circuits,” IEEE Journal of Solid-State Circuits, vol. 42, no. 8, August 2007, pp. 1678-1687.

Proposed Architecture

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• Hierarchical in nature• Two level Hierarchy• Bottom layer

• Mesh Connectivity• Upper layer

• Switches grouped into subnets• One hub per subnet• All switches from one subnet connected to the hub from that subnet

• One wireless per subnet• Wireless interconnected with each other in all‐to‐all fashion

Performance Evaluation of 3D Wireless NoC• 4 layers

• 64 cores

• 8 wireless routers

• 2 in each layer

• 2 MAC protocols• Token based• CDMA

• Lower temperatures for several benchmarks

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Lower packet energy, lower temperature, comparable bandwidth

Fig. Peak temperature in presence of real application traffics

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3D‐Mesh‐TSV CDMA based 3D‐HiWiNoC

Peak te

mpe

rature (ºC)

CANNEAL FFT LU RADIX BODYTRACK

Performance Evaluation of 3D Wireless NoC

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Lower packet energy, lower temperature, But bandwidth is also reducing. Why??

Fig. Peak temperature in presence of real application traffics

• What about bandwidth and energy?

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CANNEAL FFT LU RADIX BODYTRACK

Normalize

d Packet Ene

rgy 

Normalize

d Pe

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idth 

BW(3D‐Mesh_TSV) BW(CDMA based 3D‐HiWiNoC)

Packet Energy(3D‐Mess‐TSV) Packet Energy(CDMA based 3D‐HiWiNoC)

Why 3D wireless NoCs with interlayer cooling suffers from bandwidth degradation?• Number of active links in wireless architecture is less than 3D wireline mesh in order to accommodate micro‐channel liquid cooling layer.

• In 64 core 4 layer system,16 TSV based links connecting the vertically adjacent switches across the cooling layer is eliminated. 

• Results in a loss of an aggregate bisection bandwidth of 1.2Tbps.

• Wireless bandwidth is only 16GBps. 

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Limitation???

Conclusion• Interlayer Wireless Interconnects

• Eliminate TSVs across the cooling layer

• Make cooling layers modular in design

• Improves pressure drops and thermal efficiencies

• Improvement in peak temperature reduction and energy efficient.

• However, suffers from Bandwidth degradation.

• Requires performance evaluation of interlayer communication

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Finally!!!

Questions???

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