MCP631/2/3/4/5/9 Data Sheet - Transfer Multisort Elektronik · The Microchip Technology, Inc. MCP631/2/3/4/5/9 fam-ily of operational amplifiers features high gain band-width product

MCP631/2/3/4/5/924 MHz, 2.5 mA Op Amps

Features:• Gain Bandwidth Product: 24 MHz (typical)• Short Circuit Current: 70 mA (typical)• Noise: 10 nV/Hz (typical, at 1 MHz)• Rail-to-Rail Output• Slew Rate: 10 V/µs (typical)• Supply Current: 2.5 mA (typical)• Power Supply: 2.5V to 5.5V• Extended Temperature Range: -40°C to +125°C

Typical Applications:• Driving A/D Converters• Power Amplifier Control Loops• Barcode Scanners• Optical Detector Amplifier

Design Aids:• SPICE Macro Models• FilterLab® Software• Microchip Advanced Part Selector (MAPS)• Analog Demonstration and Evaluation Boards• Application Notes

Description:The Microchip Technology, Inc. MCP631/2/3/4/5/9 fam-ily of operational amplifiers features high gain band-width product (24 MHz, typical) and high output shortcircuit current (70 mA, typical). Some also provide aChip Select pin (CS) that supports a low-power modeof operation. These amplifiers are optimized for highspeed, low noise and distortion, single-supplyoperation with rail-to-rail output and an input thatincludes the negative rail.

This family is offered in single (MCP631), single withCS pin (MCP633), dual (MCP632), dual with two CSpins (MCP635), quad (MCP634), and quad with twoChip Select pins (MCP639). All devices are fully speci-fied from -40°C to +125°C.

Typical Application Circuit

Power Driver with High Gain

R1 R2

VIN

VDD/2 VOUT

R3 RL

MCP63X

2009-2011 Microchip Technology Inc. DS22197B-page 1

MCP631/2/3/4/5/9
Package Types
MCP631SOIC

MCP632SOIC

VIN+

VIN–

VSS

VDD

VOUT

1

2

3

4

8

7

6

5 NC

NCNC

VINA+VINA–

VSS

1234

8765

VOUTA VDD

VOUTB

VINB-VINB+

MCP635MSOP

VINA+VINA–

VSS

1234

10987

VOUTA VDD

VOUTB

VINB-VINB+

CSA 5 6 CSB

MCP6323x3 DFN *

VINA+

VINA–

VSS

VOUTA VDD

VOUTB

VINB–

VINB+

MCP6353x3 DFN *

* Includes Exposed Thermal Pad (EP); see Table 3-1.

1

2

3

4

8

7

6

5

VINA+VINA–

CSA

VOUTA VDDVOUTBVINB-

CSB

123

5

1098

6VSS VINB+4 7

MCP633SOIC

VIN+

VIN–

VSS

VDD

VOUT

1

2

3

4

8

7

6

5 NC

CSNC

MCP634SOIC, TSSOP

VINA+VINA-

VDD

1234

14131211

VOUTA VOUTD

VIND-VIND+VSS

VINB+ 5 10 VINC+VINB- 6 9

VOUTB 7 8 VOUTC

VINC-

2VDD

VINB+

VINA- VIND+

VSSV

INB-

VINC+V

OU

TB

CS

BC

VO

UTC

VINC-

VO

UTA

CS

AD

VO

UTD

VIN

D-

VINA+ EP

161

15 14 13

3

4

12

1110

95 6 7 8

17

MCP6394x4 QFN*

EP9

EP11

MCP6312x3 TDFN *

VIN+

VIN–

VSS

VDD

VOUT

1

2

34

8

7

65 NC

NCNC

EP9

VIN+

VOUT

VSS

VIN-

MCP631SOT-23-5

VDD1

2

3 4

5

CS

VIN+

VOUT

VSS

VIN-

MCP633SOT-23-6

VDD1

2

3 4

5

6

DS22197B-page 2 2009-2011 Microchip Technology Inc.

MCP631/2/3/4/5/9

1.0 ELECTRICAL CHARACTERISTICS

1.1 Absolute Maximum Ratings †VDD – VSS .......................................................................6.5VCurrent at Input Pins ....................................................±2 mAAnalog Inputs (VIN+ and VIN–) †† . VSS – 1.0V to VDD + 1.0VAll other Inputs and Outputs .......... VSS – 0.3V to VDD + 0.3VOutput Short Circuit Current ................................ContinuousCurrent at Output and Supply Pins ..........................±150 mAStorage Temperature ...................................-65°C to +150°CMax. Junction Temperature ........................................ +150°CESD protection on all pins (HBM, MM) 1 kV, 200V

† Notice: Stresses above those listed under “AbsoluteMaximum Ratings” may cause permanent damage to thedevice. This is a stress rating only and functional operation ofthe device at those or any other conditions above thoseindicated in the operational listings of this specification is notimplied. Exposure to maximum rating conditions for extendedperiods may affect device reliability.†† See Section 4.1.2 “Input Voltage and Current Limits”.

1.2 Specifications

TABLE 1-1: DC ELECTRICAL SPECIFICATIONSElectrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/3, VOUT VDD/2, VL = VDD/2, RL = 2 k to VL and CS = VSS (refer to Figure 1-2).

Parameters Sym Min Typ Max Units ConditionsInput OffsetInput Offset Voltage VOS -8 ±1.8 +8 mVInput Offset Voltage Drift VOS/TA — ±2.0 — µV/°C TA= -40°C to +125°CPower Supply Rejection Ratio PSRR 61 76 — dBInput Current and ImpedanceInput Bias Current IB — 4 — pA

Across Temperature IB — 100 — pA TA= +85°CAcross Temperature IB — 1500 5,000 pA TA= +125°C

Input Offset Current IOS — ±2 — pACommon Mode Input Impedance ZCM — 1013||9 — ||pFDifferential Input Impedance ZDIFF — 1013||2 — ||pFCommon ModeCommon Mode Input Voltage Range VCMR VSS 0.3 — VDD 1.3 V (Note 1)Common Mode Rejection Ratio CMRR 63 78 — dB VDD = 2.5V, VCM = -0.3 to 1.2V

CMRR 66 81 — dB VDD = 5.5V, VCM = -0.3 to 4.2VOpen Loop GainDC Open Loop Gain (large signal) AOL 88 115 — dB VDD = 2.5V, VOUT = 0.3V to 2.2V

AOL 94 124 — dB VDD = 5.5V, VOUT = 0.3V to 5.2VOutputMaximum Output Voltage Swing VOL, VOH VSS + 20 — VDD 20 mV VDD = 2.5V, G = +2,

0.5V Input OverdriveVOL, VOH VSS + 40 — VDD 40 mV VDD = 5.5V, G = +2,

0.5V Input OverdriveOutput Short Circuit Current ISC ±40 ±85 ±130 mA VDD = 2.5V (Note 2)

ISC ±35 ±70 ±110 mA VDD = 5.5V (Note 2)Power SupplySupply Voltage VDD 2.5 — 5.5 VQuiescent Current per Amplifier IQ 1.2 2.5 3.6 mA No Load CurrentNote 1: See Figure 2-5 for temperature effects.

2: The ISC specifications are for design guidance only; they are not tested.


MCP631/2/3/4/5/9

TABLE 1-2: AC ELECTRICAL SPECIFICATIONSElectrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, VL = VDD/2, RL = 2 k to VL, CL = 50 pF and CS = VSS (refer to Figure 1-2).

Parameters Sym Min Typ Max Units ConditionsAC ResponseGain Bandwidth Product GBWP — 24 — MHzPhase Margin PM — 65 — ° G = +1Open Loop Output Impedance ROUT — 20 —

AC DistortionTotal Harmonic Distortion plus Noise THD+N — 0.0015 — % G = +1, VOUT = 2VP-P, f = 1 kHz,

VDD = 5.5V, BW = 80 kHzStep ResponseRise Time, 10% to 90% tr — 20 — ns G = +1, VOUT = 100 mVP-P

Slew Rate SR — 10 — V/µs G = +1NoiseInput Noise Voltage Eni — 16 — µVP-P f = 0.1 Hz to 10 HzInput Noise Voltage Density eni — 10 — nV/Hz f = 1 MHzInput Noise Current Density ini 4 — fA/Hz f = 1 kHz

TABLE 1-3: DIGITAL ELECTRICAL SPECIFICATIONSElectrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, VL = VDD/2, RL = 2 k to VL, CL = 50 pF and CS = VSS (refer to Figure 1-1 and Figure 1-2).

Parameters Sym Min Typ Max Units Conditions

CS Low Specifications

CS Logic Threshold, Low VIL VSS — 0.2VDD V

CS Input Current, Low ICSL — 0.1 — nA CS = 0V

CS High Specifications

CS Logic Threshold, High VIH 0.8VDD VDD V

CS Input Current, High ICSH — 0.7 — µA CS = VDD

GND Current ISS -2 -1 — µA

CS Internal Pull-Down Resistor RPD — 5 — M

Amplifier Output Leakage IO(LEAK) — 50 — nA CS = VDD, TA = +125°C

CS Dynamic Specifications

CS Input Hysteresis VHYST — 0.25 — V

CS High to Amplifier Off Time(output goes High-Z)

tOFF — 200 — ns G = +1 V/V, VL = VSSCS = 0.8VDD to VOUT = 0.1(VDD/2)

CS Low to Amplifier On Time tON — 2 10 µs G = +1 V/V, VL = VSS,CS = 0.2VDD to VOUT = 0.9(VDD/2)


MCP631/2/3/4/5/9

1.3 Timing Diagram

FIGURE 1-1: Timing Diagram.

1.4 Test CircuitsThe circuit used for most DC and AC tests is shown inFigure 1-2. It independently sets VCM and VOUT; seeEquation 1-1. The circuit’s common mode voltage is(VP + VM)/2, not VCM. VOST includes VOS plus theeffects of temperature, CMRR, PSRR and AOL.

EQUATION 1-1:

TABLE 1-4: TEMPERATURE SPECIFICATIONSElectrical Characteristics: Unless otherwise indicated, all limits are specified for: VDD = +2.5V to +5.5V, VSS = GND.

Parameters Sym Min Typ Max Units ConditionsTemperature RangesSpecified Temperature Range TA -40 — +125 °C

Operating Temperature Range TA -40 — +125 °C (Note 1)

Storage Temperature Range TA -65 — +150 °C

Thermal Package ResistancesThermal Resistance, 5L-SOT-23 θJA — 220.7 — °C/WThermal Resistance, 6L-SOT-23 θJA — 190.5 — °C/WThermal Resistance, 8L-2x3 TDFN θJA — 52.5 — °C/WThermal Resistance, 8L-3x3 DFN JA — 60 — °C/W (Note 2)Thermal Resistance, 8L-SOIC JA — 149.5 — °C/WThermal Resistance, 10L-3x3 DFN JA — 57 — °C/W (Note 2)Thermal Resistance, 10L-MSOP JA — 202 — °C/WThermal Resistance, 14L-SOIC θJA — 95.3 — °C/WThermal Resistance, 14L-TSSOP θJA — 100 — °C/WThermal Resistance, 16L-4x4-QFN θJA — 45.7 — °C/W (Note 2)Note 1: Operation must not cause TJ to exceed Maximum Junction Temperature specification (+150°C).

2: Measured on a standard JC51-7, four layer printed circuit board with ground plane and vias.

VOUT

ISS

ICS

-1 µA

High-Z

0.7 µA

On

-2.5 mA-1 µA

tON tOFF

High-Z

0.1 nA 0.7 µA

CS VIL VIH

(typical) (typical) (typical)

(typical)(typical) (typical)

GDM RF RG=

VCM VP 1 1 GN– VREF 1 GN +=

VOUT VREF VP VM– GDM VOSTGN+ +=

Where:

GDM = Differential Mode Gain (V/V)GN = Noise Gain (V/V)

VCM = Op Amp’s Common ModeInput Voltage

(V)

VOST = Op Amp’s Total Input OffsetVoltage

(mV)

VOST VIN– VIN+–=

GN 1 GDM+=


MCP631/2/3/4/5/9

FIGURE 1-2: AC and DC Test Circuit for Most Specifications.

VDD

RG RF

VOUTVM

CB2

CLRL

VL

CB1

10 k10 k

RG RFVREF = VDD/2

VP

10 k10 k

50 pF2 k

2.2 µF100 nF

VIN-

VIN+

CF

CF6.8 pF

MCP63X

6.8 pF


MCP631/2/3/4/5/9

2.0 TYPICAL PERFORMANCE CURVES

Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 2 kto VL, CL = 50 pF and CS = VSS.

2.1 DC Signal Inputs

FIGURE 2-1: Input Offset Voltage.

FIGURE 2-2: Input Offset Voltage Drift.

FIGURE 2-3: Input Offset Voltage vs. Power Supply Voltage with VCM = 0V.

FIGURE 2-4: Input Offset Voltage vs. Output Voltage.

FIGURE 2-5: Low Input Common Mode Voltage Headroom vs. Ambient Temperature.

FIGURE 2-6: High Input Common Mode Voltage Headroom vs. Ambient Temperature.

Note: The graphs and tables provided following this note are a statistical summary based on a limited number ofsamples and are provided for informational purposes only. The performance characteristics listed hereinare not tested or guaranteed. In some graphs or tables, the data presented may be outside the specifiedoperating range (e.g., outside specified power supply range) and therefore outside the warranted range.

0%

2%

4%

6%

8%

10%

12%

14%

-6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6Input Offset Voltage (mV)

Perc

enta

ge o

f Occ

urre

nces

396 SamplesTA = +25°CVDD = 2.5V and 5.5V

0%

2%

4%

6%

8%

10%

12%

14%

16%

-8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8Input Offset Voltage Drift (µV/°C)

Perc

enta

ge o

f Occ

urre

nces

398 SamplesVDD = 2.5V and 5.5VTA = -40°C to +125°C

-4.0-3.8-3.6-3.4-3.2-3.0-2.8-2.6-2.4-2.2-2.0

1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5Power Supply Voltage (V)

Inpu

t Offs

et V

olta

ge (m

V)

+125°C+85°C+25°C-40°C

Representative PartVCM = VSS

-3.0-2.8-2.6-2.4-2.2-2.0-1.8-1.6-1.4-1.2-1.0

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5Output Voltage (V)

Inpu

t Offs

et V

olta

ge (m

V)

VDD = 2.5V

VDD = 5.5V

Representative Part

-0.5

-0.4

-0.3

-0.2

-0.1

0.0

-50 -25 0 25 50 75 100 125Ambient Temperature (°C)

Low

Inpu

t Com

mon

Mod

e H

eadr

oom

(V)

1 LotLow (VCMR_L – VSS)

VDD = 2.5V and 5.5V

0.9

1.0

1.1

1.2

1.3


Hig

h In

put C

omm

onM

ode

Hea

droo

m (V

)

VDD = 2.5V

VDD = 5.5V

1 LotHigh (VDD – VCMR_H)


MCP631/2/3/4/5/9
FIGURE 2-7: Input Offset Voltage vs. Common Mode Voltage with VDD = 2.5V.

FIGURE 2-8: Input Offset Voltage vs. Common Mode Voltage with VDD = 5.5V.

FIGURE 2-9: CMRR and PSRR vs. Ambient Temperature.

FIGURE 2-10: DC Open-Loop Gain vs. Ambient Temperature.

FIGURE 2-11: DC Open-Loop Gain vs. Load Resistance.

FIGURE 2-12: Input Bias and Offset Currents vs. Ambient Temperature with VDD = +5.5V.

-2.0

-1.5

-1.0

-0.5

0.0

0.5

1.0

1.5

2.0

-0.5 0.0

0.5

1.0

1.5

2.0

2.5

3.0

Input Common Mode Voltage (V)

Inpu

t Offs

et V

olta

ge (m

V)

VDD = 2.5VRepresentative Part

+125°C+85°C+25°C-40°C

-2.0

-1.5

-1.0

-0.5

0.0

0.5

1.0

1.5

2.0

-0.5 0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

Input Common Mode Voltage (V)

Inpu

t Offs

et V

olta

ge (m

V)

VDD = 5.5VRepresentative Part

+125°C+85°C+25°C-40°C

6065707580859095

100105110


CM

RR

, PSR

R (d

B)

PSRR

CMRR, VDD = 2.5VCMRR, VDD = 5.5V

100

105

110

115

120

125

130


DC

Ope

n-Lo

op G

ain

(dB

)

VDD = 5.5V

VDD = 2.5V

95

100

105

110

115

120

125

130

1.E+02 1.E+03 1.E+04 1.E+05Load Resistance (Ω)

DC

Ope

n-Lo

op G

ain

(dB

) VDD = 5.5V

VDD = 2.5V

100 1k 10k 100k

1.E-12

1.E-11

1.E-10

1.E-09

1.E-08

25 45 65 85 105 125Ambient Temperature (°C)

Inpu

t Bia

s, O

ffset

Cur

rent

s(p

A)

VDD = 5.5VVCM = VCMR_H

| IOS |

IB

1p

10p

100p

1n

10n


MCP631/2/3/4/5/9
FIGURE 2-13: Input Bias Current vs. Input Voltage (below VSS).

FIGURE 2-14: Input Bias and Offset Currents vs. Common Mode Input Voltage with TA = +85°C.

FIGURE 2-15: Input Bias and Offset Currents vs. Common Mode Input Voltage with TA = +125°C.

1.E-121.E-111.E-101.E-091.E-081.E-071.E-061.E-051.E-041.E-03

-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0Input Voltage (V)

Inpu

t Cur

rent

Mag

nitu

de (A

)

+125°C+85°C+25°C-40°C

1m100µ

10µ1µ

100n10n

1n100p10p

1p

-200

-150

-100

-50

0

50

100

150

200

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

Common Mode Input Voltage (V)

Inpu

t Bia

s, O

ffset

Cur

rent

s(p

A)

IB

Representative PartTA = +85°CVDD = 5.5V

IOS

-1500

-1000

-500

0

500

1000

1500

2000

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0


Inpu

t Bia

s, O

ffset

Cur

rent

s(p

A)

IB

Representative PartTA = +125°CVDD = 5.5V

IOS


MCP631/2/3/4/5/9
2.2 Other DC Voltages and Currents

FIGURE 2-16: Output Voltage Headroom vs. Output Current.

FIGURE 2-17: Output Voltage Headroom vs. Ambient Temperature.

FIGURE 2-18: Output Short Circuit Current vs. Power Supply Voltage.

FIGURE 2-19: Supply Current vs. Power Supply Voltage.

FIGURE 2-20: Supply Current vs. Common Mode Input Voltage.

1

10

100

1000

0.1 1 10 100Output Current Magnitude (mA)

Out

put V

olta

ge H

eadr

oom

(mV)

VDD = 2.5V

VDD = 5.5V

VDD – VOH

VOL – VSS

02468

101214161820


Out

put H

eadr

oom

(mV)

VDD = 5.5VVOL – VSS

VDD = 2.5V VDD – VOH

RL = 2 kΩ

-100-80-60-40-20

020406080

100

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

6.5

Power Supply Voltage (V)

Out

put S

hort

Circ

uit C

urre

nt(m

A)

+125°C+85°C+25°C-40°C

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

6.5


Supp

ly C

urre

nt(m

A/a

mpl

ifier

)

+125°C+85°C+25°C-40°C

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

-0.5 0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0


Supp

ly C

urre

nt(m

A/a

mpl

ifier

)

VDD = 2.5V

VDD = 5.5V


MCP631/2/3/4/5/9
2.3 Frequency Response

FIGURE 2-21: CMRR and PSRR vs. Frequency.

FIGURE 2-22: Open-Loop Gain vs. Frequency.

FIGURE 2-23: Gain Bandwidth Product and Phase Margin vs. Ambient Temperature.

FIGURE 2-24: Gain Bandwidth Product and Phase Margin vs. Common Mode Input Voltage.

FIGURE 2-25: Gain Bandwidth Product and Phase Margin vs. Output Voltage.

FIGURE 2-26: Closed-Loop Output Impedance vs. Frequency.

102030405060708090

100

1.E+2 1.E+3 1.E+4 1.E+5 1.E+6 1.E+7Frequency (Hz)

CM

RR

, PSR

R (d

B)

100 1M10k 10M100k1k

CMRRPSRR+PSRR-

-20

0

20

40

60

80

100

120

140

1.E+0 1.E+1 1.E+2 1.E+3 1.E+4 1.E+5 1.E+6 1.E+7 1.E+8Frequency (Hz)

Ope

n-Lo

op G

ain

(dB

)

-240

-210

-180

-150

-120

-90

-60

-30

0

Ope

n-Lo

op P

hase

(°)

| AOL |

AOL

100 10k 1M 100M1 1k 100k 10M10

20

22

24

26

28

30

32

34

36


Gai

n B

andw

idth

Pro

duct

(M

Hz)

40

45

50

55

60

65

70

75

80

Phas

e M

argi

n (°

)

PM

GBWP

VDD = 5.5VVDD = 2.5V

20

22

24

26

28

30

32

34

36

-0.5 0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0


Gai

n B

andw

idth

Pro

duct

(MH

z)

40

45

50

55

60

65

70

75

80

Phas

e M

argi

n (°

)PM

GBWP


20

22

24

26

28

30

32

34

36

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5Output Voltage (V)

Gai

n B

andw

idth

Pro

duct

(MH

z)

40

45

50

55

60

65

70

75

80

Phas

e M

argi

n (°

)

PM

GBWP


0.1

1

10

100

1.0E+04 1.0E+05 1.0E+06 1.0E+07 1.0E+08Frequency (Hz)

10k 1M 10M 100MClo

sed-

Loop

Out

put I

mpe

danc

e (Ω

)

100k

G = 101 V/VG = 11 V/V

G = 1 V/V


MCP631/2/3/4/5/9
FIGURE 2-27: Gain Peaking vs. Normalized Capacitive Load.

FIGURE 2-28: Channel-to-Channel Separation vs. Frequency.

0123456789

10

1.0E-11 1.0E-10 1.0E-09Normalized Capacitive Load; CL/GN (F)

Gai

n Pe

akin

g (d

B)

10p 100p 1n

GN = 1 V/VGN = 2 V/VGN 4 V/V

5060708090

100110120130140150

1.E+03 1.E+04 1.E+05 1.E+06 1.E+07Frequency (Hz)

Cha

nnel

-to-C

hann

elSe

para

tion;

RTI

(dB

)

1k 10k 100k

VCM = VDD/2G = +1 V/V

RS = 10 kΩRS = 100 kΩ

1M 10M

RS = 0ΩRS = 100ΩRS = 1 kΩ


MCP631/2/3/4/5/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,VL = VDD/2, RL = 2 kto VL, CL = 50 pF and CS = VSS.
2.4 Noise and Distortion

FIGURE 2-29: Input Noise Voltage Density vs. Frequency.

FIGURE 2-30: Input Noise Voltage Density vs. Input Common Mode Voltage with f = 100 Hz.

FIGURE 2-31: Input Noise Voltage Density vs. Input Common Mode Voltage with f = 1 MHz.

FIGURE 2-32: Input Noise vs. Time with 0.1 Hz Filter.

FIGURE 2-33: THD+N vs. Frequency.

1.E+0

1.E+1

1.E+2

1.E+3

1.E+4

1.E-1 1.E+0 1.E+1 1.E+2 1.E+3 1.E+4 1.E+5 1.E+6 1.E+7Frequency (Hz)

0.1 100 10k 1MInpu

t Noi

se V

olta

ge D

ensi

ty (V

/ H

z)

1 1k 100k 10M101n

100n

1µ

10µ

10n

020406080

100120140160180200

-0.5 0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0


VDD = 5.5V

VDD = 2.5V

Inpu

t Noi

se V

olta

ge D

ensi

ty(n

V/H

z)

f = 100 Hz

02468

101214161820

-0.5 0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5


VDD = 5.5V

VDD = 2.5V

Inpu

t Noi

se V

olta

ge D

ensi

ty(n

V/H

z)

f = 1 MHz

-20

-15

-10

-5

0

5

10

15

20

0 5 10 15 20 25 30 35 40 45 50 55 60 65Time (min)

Inpu

t Noi

se; e

ni(t)

(µV)

Representative Part

Analog NPBW = 0.1 HzSample Rate = 2 SPSVOS = -3150 µV

0.0001

0.001

0.01

0.1

1

1.E+2 1.E+3 1.E+4 1.E+5Frequency (Hz)

THD

+ N

oise

(%)

VDD = 5.0VVOUT = 2 VP-P

100 1k 10k 100k

BW = 22 Hz to 80 kHz

BW = 22 Hz to > 500 kHz G = 1 V/VG = 11 V/V


MCP631/2/3/4/5/9
2.5 Time Response

FIGURE 2-34: Non-inverting Small Signal Step Response.

FIGURE 2-35: Non-inverting Large Signal Step Response.

FIGURE 2-36: Inverting Small Signal Step Response.

FIGURE 2-37: Inverting Large Signal Step Response.

FIGURE 2-38: The MCP631/2/3/4/5/9 family shows no input phase reversal with overdrive.

FIGURE 2-39: Slew Rate vs. Ambient Temperature.

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8Time (µs)

Out

put V

olta

ge (1

0 m

V/di

v)

VDD = 5.5VG = 1

VIN VOUT

0.00.51.01.52.02.53.03.54.04.55.05.5

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0Time (µs)

Out

put V

olta

ge (V

)

VDD = 5.5VG = 1

VIN VOUT

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8Time (µs)

Out

put V

olta

ge (1

0 m

V/di

v)

VDD = 5.5VG = -1RF = 1 kΩ

VIN

VOUT

0.00.51.01.52.02.53.03.54.04.55.05.5

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0Time (µs)

Out

put V

olta

ge (V

)

VDD = 5.5VG = -1RF = 1 kΩ

VIN

VOUT

-1

0

1

2

3

4

5

6

7

0 1 2 3 4 5 6 7 8 9 10Time (ms)

Inpu

t, O

utpu

t Vol

tage

s (V

) VDD = 5.5VG = 2

VOUT

VIN

02468

1012141618202224


Slew

Rat

e (V

/µs)

Falling Edge

Rising Edge

VDD = 2.5V

VDD = 5.5V


MCP631/2/3/4/5/9
FIGURE 2-40: Maximum Output Voltage Swing vs. Frequency.

0.1

1

10

1.E+05 1.E+06 1.E+07 1.E+08Frequency (Hz)

Max

imum

Out

put V

olta

geSw

ing

(VP-

P)

VDD = 5.5V

VDD = 2.5V

100k 1M 10M 100M


MCP631/2/3/4/5/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,VL = VDD/2, RL = 2 kto VL, CL = 50 pF and CS = VSS.
2.6 Chip Select Response

FIGURE 2-41: CS Current vs. Power Supply Voltage.

FIGURE 2-42: CS and Output Voltages vs. Time with VDD = 2.5V.

FIGURE 2-43: CS and Output Voltages vs. Time with VDD = 5.5V.

FIGURE 2-44: CS Hysteresis vs. Ambient Temperature.

FIGURE 2-45: CS Turn On Time vs. Ambient Temperature.

FIGURE 2-46: CS’s Pull-down Resistor (RPD) vs. Ambient Temperature.

0.00.10.20.30.40.50.60.70.80.91.01.1

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5Power Supply Voltage (V)

CS

Cur

rent

(µA

)

CS = VDD

-0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

0 2 4 6 8 10 12 14 16 18 20Time (µs)

CS,

VO

UT

(V)

VDD = 2.5VG = 1VL = 0V

On

CS

VOUT

OffOff

-1

0

1

2

3

4

5

6

0 2 4 6 8 10 12 14 16 18 20Time (µs)

CS,

VO

UT

(V)

VDD = 5.5VG = 1VL = 0V

On

CS

VOUT

OffOff

0.00

0.05

0.10

0.15

0.20

0.25

0.30

0.35

0.40


CS

Hys

tere

sis

(V)

VDD = 2.5V

VDD = 5.5V

0

1

2

3

4

5


CS

Turn

On

Tim

e (µ

s)

VDD = 2.5V

VDD = 5.5V

0

1

2

3

4

5

6

7

8


CS

Pull-

dow

n R

esis

tor

(MΩ

)

Representative Part


MCP631/2/3/4/5/9
FIGURE 2-47: Quiescent Current in Shutdown vs. Power Supply Voltage.

FIGURE 2-48: Output Leakage Current vs. Output Voltage.

-2.2-2.0-1.8-1.6-1.4-1.2-1.0-0.8-0.6-0.4-0.20.0

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

6.5


Neg

ativ

e Po

wer

Sup

ply

Cur

rent

; ISS

(µA

)

CS = VDD

-40°C+25°C+85°C

+125°C

1.E-11

1.E-10

1.E-09

1.E-08

1.E-07

1.E-06

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0Output Voltage (V)

Out

put L

eaka

ge C

urre

nt (A

)

+25°C

+125°C

+85°C

CS = VDD = 5.5V1µ

100n

10n

1n

100p

10p


MCP631/2/3/4/5/9
NOTES:

MCP631/2/3/4/5/9

3.0 PIN DESCRIPTIONSDescriptions of the pins are listed in Table 3-1.

TABLE 3-1: PIN FUNCTION TABLE

3.1 Analog OutputsThe analog output pins (VOUT) are low-impedancevoltage sources.

3.2 Analog InputsThe non-inverting and inverting inputs (VIN+, VIN-, …)are high-impedance CMOS inputs with low biascurrents.

3.3 Power Supply PinsThe positive power supply (VDD) is 2.5V to 5.5V higherthan the negative power supply (VSS). For normaloperation, the other pins are between VSS and VDD.

Typically, these parts are used in a single (positive)supply configuration. In that case, VSS is connected toground and VDD is connected to the supply. VDD willneed bypass capacitors.

MC

P631

MC

P632

MC

P633

MC

P634

MC

P635

MC

P639

Sym

bol

Description

SOIC SOT TDFN SOIC DFN SOIC SOT SOIC TSSOP MSOP DFN QFN

6 1 6 1 1 6 1 1 1 1 1 16 VOUT, VOUTA

Output (op amp A)

2 4 2 2 2 2 4 2 2 2 2 1 VIN-, VINA-

Inverting Input (op amp A)

3 3 3 3 3 3 3 3 3 3 3 2 VIN+, VINA+

Non-inverting Input (op amp A)

4 2 4 4 4 4 2 11 11 4 4 11 VSS Negative Power Supply

— — — — — 8 5 — — 5 5 — CS, CSA Chip Select Digital Input (op amp A)

— — — — — — — — — 6 6 — CSB Chip Select Digital Input (op amp B)

— — — 5 5 — — 5 5 7 7 4 VINB+ Non-inverting Input (op amp B)

— — — 6 6 — — 6 6 8 8 5 VINB- Inverting Input (op amp B)— — — 7 7 — — 7 7 9 9 6 VOUTB Output (op amp B)7 5 7 8 8 7 6 4 4 10 10 3 VDD Positive Power Supply— — — — — — — — — — — 7 CSBC Chip Select Digital Input

(op amp B and C)— — — — — — — 8 8 — — 8 VOUTC Output (op amp C)— — — — — — — 9 9 — — 9 VINC- Inverting Input (op amp C)— — — — — — — 10 10 — — 10 VINC+ Non-Inverting Input (op

amp C)— — — — — — — 12 12 — — 12 VIND+ Non-inverting Input (op

amp D)— — — — — — — 13 13 — — 13 VIND- Inverting Input (op amp D)— — — — — — — 14 14 — — 14 VOUTD Output (op amp D)— — — — — — — — — — — 15 CSAD Chip Select Digital Input

(op amp A and D)1,5,8

— 1, 5, 8

— — 1,5 — — — — — — NC No Internal Connection

— — — — 9 — — — — — 11 17 EP Exposed Thermal Pad (EP); must be connected to VSS


MCP631/2/3/4/5/9
3.4 Chip Select Digital Input (CS)This input (CS) is a CMOS, Schmitt-triggered input thatplaces the part into a low-power mode of operation.
3.5 Exposed Thermal Pad (EP)There is an internal connection between the exposedthermal pad (EP) and the VSS pin; they must beconnected to the same potential on the printed circuitboard (PCB).This pad can be connected to a PCB ground plane toprovide a larger heat sink. This improves the packagethermal resistance (JA).


MCP631/2/3/4/5/9

4.0 APPLICATIONSThe MCP631/2/3/4/5/9 family op amps is manufacturedusing the Microchip state-of-the-art CMOS process. Itis designed for low cost, low power and high speedapplications. Its low supply voltage, low quiescentcurrent and wide bandwidth make the MCP631/2/3/4/5/9 ideal for battery-powered applications.

4.1 Input

4.1.1 PHASE REVERSALThe input devices are designed to not exhibit phaseinversion when the input pins exceed the supplyvoltages. Figure 2-38 shows an input voltageexceeding both supplies with no phase inversion.

4.1.2 INPUT VOLTAGE AND CURRENT LIMITS

The electrostatic discharge (ESD) protection on theinputs can be depicted as shown in Figure 4-1. Thisstructure was chosen to protect the input transistors,and to minimize input bias current (IB). The input ESDdiodes clamp the inputs when they try to go more thanone diode drop below VSS. They also clamp any volt-ages that go too far above VDD; their breakdown volt-age is high enough to allow normal operation, and lowenough to bypass quick ESD events within the speci-fied limits.

FIGURE 4-1: Simplified Analog Input ESD Structures.In order to prevent damage and/or improper operationof these amplifiers, the circuit must limit the currents(and voltages) at the input pins (see Section 1.1“Absolute Maximum Ratings †”). Figure 4-2 showsthe recommended approach to protecting these inputs.The internal ESD diodes prevent the input pins(VIN+ and VIN-) from going too far below ground, andthe resistors R1 and R2 limit the possible current drawnout of the input pins. Diodes D1 and D2 prevent theinput pins (VIN+ and VIN-) from going too far aboveVDD, and dump any currents onto VDD. Whenimplemented as shown, resistors R1 and R2 also limitthe current through D1 and D2.

FIGURE 4-2: Protecting the Analog Inputs.It is also possible to connect the diodes to the left of theresistor R1 and R2. In this case, the currents throughthe diodes D1 and D2 need to be limited by some othermechanism. The resistors then serve as in-rushcurrent limiters; the DC current into the input pins(VIN+ and VIN-) should be very small.

A significant amount of current can flow out of theinputs (through the ESD diodes) when the commonmode voltage (VCM) is below ground (VSS); seeFigure 2-13. Applications that are high-impedance mayneed to limit the usable voltage range.

4.1.3 NORMAL OPERATIONThe input stage of the MCP631/2/3/4/5/9 op amps usesa differential PMOS input stage. It operates atlow common mode input voltages (VCM), with VCMbetween VSS – 0.3V and VDD – 1.3V. To ensure properoperation, the input offset voltage (VOS) is measuredat both VCM = VSS – 0.3V and VDD – 1.3V.See Figure 2-5 and Figure 2-6 for temperature effects.

When operating at very low non-inverting gains, theoutput voltage is limited at the top by the VCM range(< VDD – 1.3V); see Figure 4-3.

FIGURE 4-3: Unity Gain Voltage Limitations for Linear Operation.

BondPad

BondPad

BondPad

VDD

VIN+

VSS

InputStage

BondPad

VIN-

V1

R1

VDD

D1

R1 >VSS – (minimum expected V1)

2 mA

VOUT

R2 >VSS – (minimum expected V2)

2 mA

V2R2

D2

MCP63X

VIN

VDD

VOUT

VSS V IN V OUT VDD 1.3V–

MCP63X


MCP631/2/3/4/5/9
4.2 Rail-to-Rail Output
4.2.1 MAXIMUM OUTPUT VOLTAGEThe Maximum Output Voltage (see Figure 2-16 andFigure 2-17) describes the output range for a givenload. For instance, the output voltage swings to within50 mV of the negative rail with a 1 k load tied to VDD/2.

4.2.2 OUTPUT CURRENTFigure 4-4 shows the possible combinations of outputvoltage (VOUT) and output current (IOUT), whenVDD = 5.5V. IOUT is positive when it flows out of the opamp into the external circuit.

FIGURE 4-4: Output Current.

4.2.3 POWER DISSIPATIONSince the output short circuit current (ISC) is specifiedat ±70 mA (typical), these op amps are capable of bothdelivering and dissipating significant power.

Figure 4-5 shows the quantities used in the followingpower calculations for a single op amp. RSER is 0 inmost applications; it can be used to limit IOUT. VOUT isthe op amp’s output voltage, VL is the voltage at theload, and VLG is the load’s ground point. VSS is usuallyground (0V). The input currents are assumed to benegligible. The currents shown are approximately:

EQUATION 4-1:

FIGURE 4-5: Diagram for Power Calculations.The instantaneous op amp power (POA(t)), RSER power(PRSER(t)) and load power (PL(t)) are:

EQUATION 4-2:

The maximum op amp power, for resistive loads,occurs when VOUT is halfway between VDD and VLG orhalfway between VSS and VLG:

EQUATION 4-3:

The maximum ambient to junction temperature rise(TJA) and junction temperature (TJ) can be calculatedusing POAmax, ambient temperature (TA), the packagethermal resistance (JA) found in Table 1-4, and thenumber of op amps in the package (assuming equalpower dissipations):

EQUATION 4-4:

-0.50.00.51.01.52.02.53.03.54.04.55.05.56.0

-120

-100 -8

0

-60

-40

-20 0 20 40 60 80 100

120

IOUT (mA)

V OU

T (V

)

RL = 10Ω

RL = 100ΩRL = 1 kΩ

VOH Limited

VOL Limited

-I SC L

imite

d

+ISC

Lim

ited

(VDD = 5.5V)

VOUT – VLGIOUT = IL =RSER + RL

IDD IQ + max(0, IOUT)

ISS –IQ + min(0, IOUT)

Where:

IQ = quiescent supply current

VDD

VL

RL

VLG

IDD

ISS

IL

IOUT RSER

VOUT

VSS

MCP63X

POA(t) = IDD (VDD – VOUT) + ISS (VSS – VOUT)

PRSER(t) = IOUT2RSER

PL(t) = IL2RL

POAmax max2(VDD – VLG , VLG – VSS)

4(RSER + RL)

TJA = POA(t) JA n POAmaxJATJ = TA + TJA

Where:

n = number of op amps in package (1, 2)


MCP631/2/3/4/5/9
The power de-rating across temperature for an op ampin a particular package can be easily calculated(assuming equal power dissipations):
EQUATION 4-5:

Several techniques are available to reduce TJA for agiven POAmax:

• Lower JA- Use another package- PCB layout (ground plane, etc.)- Heat sinks and air flow

• Reduce POAmax- Increase RL- Limit IOUT (using RSER)- Decrease VDD

4.3 Improving Stability

4.3.1 CAPACITIVE LOADSDriving large capacitive loads can cause stabilityproblems for voltage feedback op amps. As the loadcapacitance increases, the feedback loop’s phasemargin decreases and the closed-loop bandwidth isreduced. This produces gain peaking in the frequencyresponse, with overshoot and ringing in the stepresponse. A unity gain buffer (G = +1) is the mostsensitive to capacitive loads, though all gains show thesame general behavior.

When driving large capacitive loads with these opamps (e.g., > 20 pF when G = +1), a small seriesresistor at the output (RISO in Figure 4-6) improves thefeedback loop’s phase margin (stability) by making theoutput load resistive at higher frequencies. Thebandwidth will be generally lower than the bandwidthwith no capacitive load.

FIGURE 4-6: Output Resistor, RISO stabilizes large capacitive loads.

Figure 4-7 gives recommended RISO values fordifferent capacitive loads and gains. The x-axis is thenormalized load capacitance (CL/GN), where GN is thecircuit’s noise gain. For non-inverting gains, GN and theSignal Gain are equal. For inverting gains, GN is1+|Signal Gain| (e.g., -1 V/V gives GN = +2 V/V).

FIGURE 4-7: Recommended RISO Values for Capacitive Loads.After selecting RISO for your circuit, double check theresulting frequency response peaking and stepresponse overshoot. Modify RISO’s value until theresponse is reasonable. Bench evaluation andsimulations with the MCP631/2/3/4/5/9 SPICE macromodel are helpful.

4.3.2 GAIN PEAKINGFigure 4-8 shows an op amp circuit that representsnon-inverting amplifiers (VM is a DC voltage and VP isthe input) or inverting amplifiers (VP is a DC voltageand VM is the input). The capacitances CN and CGrepresent the total capacitance at the input pins; theyinclude the op amp’s common mode input capacitance(CCM), board parasitic capacitance and any capacitorplaced in parallel.

FIGURE 4-8: Amplifier with Parasitic Capacitance.CG acts in parallel with RG (except for a gain of +1 V/V), which causes an increase in gain at high frequen-cies. CG also reduces the phase margin of the feed-back loop, which becomes less stable. This effect canbe reduced by either reducing CG or RF.

n JA

TJmax – TAPOAmax

Where:

TJmax = absolute maximum junction temperature

RISOVOUT

CL

RG RF

RNMCP63X

10

100

1,000

1.E-12 1.E-11 1.E-10 1.E-09 1.E-08Normalized Capacitance; CL/GN (F)

Rec

omm

ende

d R

ISO (Ω

)

GN = +1GN +2

10p 100p 1n 10n

VP

RF

VOUT

RNCN

VMRG CG

MCP63X


MCP631/2/3/4/5/9
CN and RN form a low-pass filter that affects the signalat VP. This filter has a single real pole at 1/(2RNCN).
The largest value of RF that should be used dependson noise gain (see GN in Section 4.3.1 “CapacitiveLoads”), CG and the open-loop gain’s phase shift.Figure 4-9 shows the maximum recommended RF forseveral CG values. Some applications may modifythese values to reduce either output loading or gainpeaking (step response overshoot).

FIGURE 4-9: Maximum Recommended RF vs. Gain.Figure 2-34 and Figure 2-35 show the small signal andlarge signal step responses at G = +1 V/V. The unitygain buffer usually has RF = 0 and RG open.

Figure 2-36 and Figure 2-37 show the small signal andlarge signal step responses at G = -1 V/V. Since thenoise gain is 2 V/V and CG 10 pF, the resistors werechosen to be RF = RG = 1 k and RN = 500.

It is also possible to add a capacitor (CF) in parallel withRF to compensate for the de-stabilizing effect of CG.This makes it possible to use larger values of RF. Theconditions for stability are summarized in Equation 4-6.

EQUATION 4-6:

4.4 MCP631, MCP633, MCP635, and MCP639 Chip Select

The MCP633 is a single amplifier with Chip Select(CS). When CS is pulled high, the supply current dropsto 1 µA (typical) and flows through the CS pin to VSS.When this happens, the amplifier output is put into ahigh-impedance state. By pulling CS low, the amplifieris enabled. The CS pin has an internal 5 M (typical)pull-down resistor connected to VSS, so it will go low ifthe CS pin is left floating. Figure 1-1, Figure 2-42 andFigure 2-43 show the output voltage and supply currentresponse to a CS pulse.

The MCP635 is a dual amplifier with two CS pins; CSAcontrols op amp A and CSB controls op amp B. Theseop amps are controlled independently, with an enabledquiescent current (IQ) of 2.5 mA/amplifier (typical) anda disabled IQ of 1 µA/amplifier (typical). The IQ seen atthe supply pins is the sum of the two op amps’ IQ; thetypical value for the MCP635’s IQ will be 2 µA, 2.5 mAor 5 mA when there are 0, 1 or 2 amplifiers enabled,respectively.

The MCP639 is a quad amplifier with two CS pins; CSBcontrols op amp B and CSD control s op amp D.

4.5 Power SupplyWith this family of operational amplifiers, the powersupply pin (VDD for single supply) should have a localbypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mmfor good high frequency performance. Surface mount,multilayer ceramic capacitors, or their equivalent,should be used.

These op amps require a bulk capacitor (i.e., 2.2 µF orlarger) within 50 mm to provide large, slow currents.Tantalum capacitors, or their equivalent, may be a goodchoice. This bulk capacitor can be shared with othernearby analog parts as long as crosstalk through thesupplies does not prove to be a problem.

4.6 High Speed PCB LayoutThese op amps are fast enough that a little extra carein the PCB (Printed Circuit Board) layout can make asignificant difference in performance. Good PC boardlayout techniques will help you achieve theperformance shown in the specifications and TypicalPerformance Curves; it will also help you minimizeEMC (Electro-Magnetic Compatibility) issues.

Use a solid ground plane. Connect the bypass localcapacitor(s) to this plane with minimal length traces.This cuts down inductive and capacitive crosstalk.

Separate digital from analog, low speed from highspeed, and low power from high power. This will reduceinterference.

1.E+02

1.E+03

1.E+04

1.E+05

1 10 100Noise Gain; GN (V/V)

Max

imum

Rec

omm

ende

d R

F(Ω

)

GN > +1 V/V100

10k

100k

1k

CG = 10 pFCG = 32 pF

CG = 100 pFCG = 320 pF

CG = 1 nF

fF fGBWP 2GN2 , GN1 GN2We need:

GN1 1 RF RG+=GN2 1 CG CF+=

fF 1 2RFCF =fZ fF GN1 GN2 =

Given:

fF fGBWP 4GN1 , GN1 GN2


MCP631/2/3/4/5/9
Keep sensitive traces short and straight. Separatethem from interfering components and traces. This isespecially important for high frequency (low rise time)signals.
Sometimes, it helps to place guard traces next to victimtraces. They should be on both sides of the victimtrace, and as close as possible. Connect guard tracesto ground plane at both ends, and in the middle for longtraces.

Use coax cables, or low inductance wiring, to routesignal and power to and from the PCB. Mutual and selfinductance of power wires is often a cause of crosstalkand unusual behavior.

4.7 Typical Applications

4.7.1 POWER DRIVER WITH HIGH GAINFigure 4-10 shows a power driver with high gain(1 + R2/R1). The MCP631/2/3/4/5/9 op amp’s short cir-cuit current makes it possible to drive significant loads.The calibrated input offset voltage supports accurateresponse at high gains. R3 should be small, and equalto R1||R2, in order to minimize the bias current inducedoffset.

FIGURE 4-10: Power Driver.

4.7.2 OPTICAL DETECTOR AMPLIFIERFigure 4-11 shows a trans-impedance amplifier, usingthe MCP63X op amp, in a photo detector circuit. Thephoto detector is a capacitive current source.RF provides enough gain to produce 10 mV at VOUT.CF stabilizes the gain and limits the trans-impedancebandwidth to about 1.1 MHz. RF’s parasiticcapacitance (e.g., 0.2 pF for a 0805 SMD) acts inparallel with CF.

FIGURE 4-11: Trans-impedance Amplifier for an Optical Detector.

4.7.3 H-BRIDGE DRIVERFigure 4-12 shows the MCP632 dual op amp used asa H-bridge driver. The load could be a speaker or a DCmotor.

FIGURE 4-12: H-Bridge Driver.This circuit automatically makes the noise gains (GN)equal, when the gains are set properly, so that thefrequency responses match well (in magnitude and inphase). Equation 4-7 shows how to calculate RGT andRGB so that both op amps have the same DC gains;GDM needs to be selected first.

EQUATION 4-7:

Equation 4-8 gives the resulting common mode anddifferential mode output voltages.

EQUATION 4-8:

R1 R2

VIN

VDD/2 VOUT

R3 RLMCP63X

PhotoDetector

CD

CF

RF

VDD/2

30pF

100 k

1.5 pF

ID100 nA

VOUT

MCP63X

RFRF

VIN

VOT

RFRGBVOB

VDD/2

RGTRL

½ MCP632

½ MCP632

GDMVOT VOB–

VIN VDD 2–-------------------------------- 1 V/V

RGTRF

GDM 2 1–---------------------------------=

RGBRF

GDM 2-------------------=

VOT V+ OB2---------------------------

VDD2-----------=

VOT V– OB GDM VINVDD

2-----------–

=


MCP631/2/3/4/5/9

5.0 DESIGN AIDSMicrochip provides the basic design aids needed forthe MCP631/2/3/4/5/9 family of op amps.

5.1 SPICE Macro ModelThe latest SPICE macro model for the MCP631/2/3/4/5/9 op amps is available on the Microchip web site atwww.microchip.com. This model is intended to be aninitial design tool that works well in the op amp’s linearregion of operation over the temperature range.See the model file for information on its capabilities.

Bench testing is a very important part of any design andcannot be replaced with simulations. Also, simulationresults using this macro model need to be validated bycomparing them to the data sheet specifications andcharacteristic curves.

5.2 FilterLab® SoftwareMicrochip’s FilterLab® software is an innovativesoftware tool that simplifies analog active filter(using op amps) design. Available at no cost from theMicrochip web site at www.microchip.com/filterlab, theFilterLab design tool provides full schematic diagramsof the filter circuit with component values. It alsooutputs the filter circuit in SPICE format, which can beused with the macro model to simulate actual filterperformance.

5.3 Microchip Advanced Part Selector (MAPS)

MAPS is a software tool that helps efficiently identifyMicrochip devices that fit a particular designrequirement. Available at no cost from the Microchipweb site at www.microchip.com/maps, the MAPS is anoverall selection tool for Microchip’s product portfoliothat includes Analog, Memory, MCUs and DSCs. Usingthis tool, a customer can define a filter to sort featuresfor a parametric search of devices and exportside-by-side technical comparison reports. Helpful linksare also provided for data sheets, purchase andsampling of Microchip parts.

5.4 Analog Demonstration and Evaluation Boards

Microchip offers a broad spectrum of AnalogDemonstration and Evaluation Boards that aredesigned to help customers achieve faster timeto market. For a complete listing of these boardsand their corresponding user’s guides and technicalinformation, visit the Microchip web site atwww.microchip.com/analog tools.

Some boards that are especially useful are:

• MCP6XXX Amplifier Evaluation Board 1• MCP6XXX Amplifier Evaluation Board 2• MCP6XXX Amplifier Evaluation Board 3• MCP6XXX Amplifier Evaluation Board 4• Active Filter Demo Board Kit• 8-Pin SOIC/MSOP/TSSOP/DIP Evaluation Board,

P/N SOIC8EV

5.5 Application NotesThe following Microchip Application Notes areavailable on the Microchip web site at www.microchip.com/appnotes and are recommended as supplementalreference resources.

• ADN003: “Select the Right Operational Amplifier for your Filtering Circuits”, DS21821

• AN722: “Operational Amplifier Topologies and DC Specifications”, DS00722

• AN723: “Operational Amplifier AC Specifications and Applications”, DS00723

• AN884: “Driving Capacitive Loads With Op Amps”, DS00884

• AN990: “Analog Sensor Conditioning Circuits – An Overview”, DS00990

• AN1228: “Op Amp Precision Design: Random Noise”, DS01228

Some of these application notes, and others, are listedin the design guide:

• “Signal Chain Design Guide”, DS21825


www.microchip.com

www.microchip.com/filterlab

www.microchip.com/filterlab

www.microchip.com/maps

www.micro chip.com/analog tools

www.microchip. com/appnotes

MCP631/2/3/4/5/9

6.0 PACKAGING INFORMATION

6.1 Package Marking Information

Legend: XX...X Customer-specific informationY Year code (last digit of calendar year)YY Year code (last 2 digits of calendar year)WW Week code (week of January 1 is week ‘01’)NNN Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn)* This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it willbe carried over to the next line, thus limiting the number of availablecharacters for customer-specific information.

3e 3e

Device Code

MCP632 DABMNote: Applies to 8-Lead 3x3 DFN

8-Lead DFN (3x3)(MCP632) Example

DABM1131256

8-Lead SOIC (150 mil) (MCP631, MCP632, MCP633) Example:

NNN

MCP631ESN ^^1131

2563e

Example:5-Lead SOT-23 (MCP631)

6-Lead SOT-23 ( MCP633) Example:

XXNN YV25

XXNN JC25


MCP631/2/3/4/5/9
Package Marking Information (Continued)
14-Lead SOIC (.150”) (MCP634) Example

MCP634E/SL ^^1131256

3e

10-Lead MSOP (MCP635)Example:

635EUN131256

10-Lead DFN (3x3) (MCP635)

Device Code

MCP635 BAFBNote: Applies to 10-Lead 3x3 DFN

Example

BAFB1131256

8-Lead TDFN (2 x 3) (MCP631) Example:

ABK13125




3e 3e


MCP631/2/3/4/5/9
Package Marking Information (Continued)
14-Lead TSSOP (MCP634) Example

YYWWNNN

XXXXXXXX 634E/ST1131256

16-Lead QFN (4x4) (MCP639) Example

PIN 1 PIN 1 639E/ML ^^131256

3e




3e 3e


MCP631/2/3/4/5/9

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)*+ ) # &#,$ --#$##

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Nb

E

E1

D

1 2 3

e

e1

A

A1

A2 c

L

L1

- *)


MCP631/2/3/4/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging


MCP631/2/3/4/5/9

6-Lead Plastic Small Outline Transistor (CHY) [SOT-23]

Notes:1. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.127 mm per side.2. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.


Units MILLIMETERSDimension Limits MIN NOM MAX

Number of Pins N 6Pitch e 0.95 BSCOutside Lead Pitch e1 1.90 BSCOverall Height A 0.90 1.45Molded Package Thickness A2 0.89 1.30Standoff A1 0.00 0.15Overall Width E 2.20 3.20Molded Package Width E1 1.30 1.80Overall Length D 2.70 3.10Foot Length L 0.10 0.60Footprint L1 0.35 0.80Foot Angle 0° 30°Lead Thickness c 0.08 0.26Lead Width b 0.20 0.51

b

E

4N

E1

PIN 1 ID BYLASER MARK

D

1 2 3

e

e1

A

A1

A2 c

LL1

φ

Microchip Technology Drawing C04-028B


MCP631/2/3/4/5/9

6-Lead Plastic Small Outline Transistor (CHY) [SOT-23]



MCP631/2/3/4/5/9



MCP631/2/3/4/5/9



MCP631/2/3/4/5/9

!"#$%&'**+,./0!"

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MCP631/2/3/4/5/9



MCP631/2/3/4/5/9



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MCP631/2/3/4/5/9



MCP631/2/3/4/5/9



MCP631/2/3/4/5/9

'1#,4+/057

.# #$ #/ !- 0 # 1/ %## !###+22---2/


MCP631/2/3/4/5/9



MCP631/2/3/4/5/9



MCP631/2/3/4/5/9



MCP631/2/3/4/5/9

8+ & $%9&

1, $! &% #$ ,08$#$ #8 # !-## # ! !"!#$! !% #$ !% #$ # & !( ! !# "'(

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D

E

E1

N

NOTE 1

1 2b

e

A

A1

A2 c

L

L1

φ

- *)


MCP631/2/3/4/5/9

10-Lead Plastic Micro Small Outline Package (UN) [MSOP]



MCP631/2/3/4/5/9



MCP631/2/3/4/5/9



MCP631/2/3/4/5/9

.# #$ #/ !- 0 # 1/ %## !###+22---2/


MCP631/2/3/4/5/9



MCP631/2/3/4/5/9



MCP631/2/3/4/5/9



MCP631/2/3/4/5/9

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1, $! &% #$ ,08$#$ #8 # !-## # ! 1/ - $# ! !# "'(

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5$8 %1 5 =1# =()*6, 9 # ; #!%% (*##/ ".6, <!# " )*"& !1!<!# " ( =( ;6, 4 # )*"& !1!4 # ( =( ;*##<!# 8 ( (*##4 # 4 (*###"& !1! | : :

D

E

N

2

1

EXPOSEDPAD

D2

E22

1

e

b

KN

NOTE 1

A3

A1

A

LTOP VIEW BOTTOM VIEW

- *)


MCP631/2/3/4/5/9



MCP631/2/3/4/5/9
NOTES:

MCP631/2/3/4/5/9

APPENDIX A: REVISION HISTORY

Revision B (November 2011)The following is the list of modifications:

1. Added the MCP634 and MCP639 amplifiers tothe product family and the related informationthroughout the document.

2. Added the 2x3 TDFN (8L), SOT23 (5L) packageoption for MCP631, SOT23 (6L) package optionfor MCP633, 4x4 QFN (16L) package option forMCP639, SOIC and TSSOP (14L) packageoptions for MCP634 and the related informationthroughout the document. Updated packagetypes drawing with pin designation for each newpackage.

3. Updated Table 1-4 to show the temperaturespecifications for new packages.

4. Updated Table 3-1 to show all the pin functions.5. Updated Section 6.0 “Packaging Informa-

tion” with markings for the new additions.Added the corresponding SOT23 (5L), SOT23(6L), TDFN (8L), SOIC, TSSOP (14L), and 4x4QFN (16L) package options and related infor-mation.

6. Updated table description and examples in theProduct Identification System section.

Revision A (August 2009)• Original Release of this Document.


MCP631/2/3/4/5/9
NOTES:

MCP631/2/3/4/5/9

PRODUCT IDENTIFICATION SYSTEMTo order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO. -X /XX

PackageTemperatureRange

Device

Device: MCP631 Single Op Amp

MCP631T Single Op Amp (Tape and Reel)(SOIC, SOT-23, TDFN)

MCP632 Dual Op AmpMCP632T Dual Op Amp (Tape and Reel)

(DFN and SOIC)MCP633 Single Op Amp with CSMCP633T Single Op Amp with CS (Tape and Reel)

(SOIC, SOT-23)MCP634 Quad Op AmpMCP634T Quad Op Amp (Tape and Reel)

(TSSOP and SOIC)MCP635 Dual Op Amp with CSMCP635T Dual Op Amp with CS (Tape and Reel)

(DFN and MSOP)MCP639 Quad Op AmpMCP639T Quad Op Amp (Tape and Reel)

(QFN)

Temperature Range:

E = -40°C to +125°C

Package: OT = Plastic Small Outline (SOT-23), 5-leadCHY = Plastic Small Outline (SOT-23), 6-leadMNY= Plastic Dual Flat, No Lead (2x3 TDFN), 8-leadMF = Plastic Dual Flat, No Lead (3×3 DFN),

8-lead, 10-leadSN = Plastic Small Outline (3.90 mm), 8-leadUN = Plastic Micro Small Outline (MSOP), 10-leadSL = Plastic Small Outline, Narrow, (3.90 mm SOIC),

14-leadST = Plastic Thin Shrink Small Outline, (4.4 mm TSSOP),

14-leadML = Plastic Quad Flat, No Lead Package (4x4 QFN),

(4x4x0.9 mm), 16-lead

Examples:a) MCP631T-E/OT: Tape and Reel

Extended temperature, 5LD SOT-23 package

b) MCP631T-E/MNY:Tape and ReelExtended temperature,8LD TDFN package

c) MCP631T-E/SN: Tape and ReelExtended temperature,8LD SOIC package

d) MCP632T-E/MF: Tape and ReelExtended temperature,8LD DFN package

e) MCP632T-E/SN: Tape and ReelExtended temperature,8LD SOIC package

f) MCP633T-E/SN: Tape and ReelExtended temperature, 8LD SOIC package

g) MCP633T-E/CHY: Tape and ReelExtended temperature,6LD SOT package

h) MCP634T-E/SL: Tape and ReelExtended temperature,14LD SOIC package

i) MCP634T-E/ST: Tape and ReelExtended temperature,14LD TSSOP package

j) MCP635T-E/MF: Tape and ReelExtended temperature,10LD DFN package

k) MCP635T-E/UN: Tape and ReelExtended temperature,10LD MSOP package

l) MCP639T-E/ML: Tape and ReelExtended temperature, 16LD QFN package.


MCP631/2/3/4/5/9
NOTES:

Note the following details of the code protection feature on Microchip devices:• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of ourproducts. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such actsallow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding deviceapplications and the like is provided only for your convenienceand may be superseded by updates. It is your responsibility toensure that your application meets with your specifications.MICROCHIP MAKES NO REPRESENTATIONS ORWARRANTIES OF ANY KIND WHETHER EXPRESS ORIMPLIED, WRITTEN OR ORAL, STATUTORY OROTHERWISE, RELATED TO THE INFORMATION,INCLUDING BUT NOT LIMITED TO ITS CONDITION,QUALITY, PERFORMANCE, MERCHANTABILITY ORFITNESS FOR PURPOSE. Microchip disclaims all liabilityarising from this information and its use. Use of Microchipdevices in life support and/or safety applications is entirely atthe buyer’s risk, and the buyer agrees to defend, indemnify andhold harmless Microchip from any and all damages, claims,suits, or expenses resulting from such use. No licenses areconveyed, implicitly or otherwise, under any Microchipintellectual property rights.

2009-2011 Microchip Technology Inc.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their respective companies.

© 2009-2011, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.

Printed on recycled paper.

ISBN: 978-1-61341-848-2

DS22197B-page 61

Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.


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Documents

MCP631/2/3/4/5/9 Data Sheet - Transfer Multisort Elektronik · The Microchip Technology, Inc. MCP631/2/3/4/5/9 fam-ily of operational amplifiers features high gain band-width product