MC68HC11 Instruction Set. Overview 68HC11 instruction set oA quick look at the programming procedure oThe programmer's model oInstruction types and formats

MC68HC11 Instruction Set

Overview

• 68HC11 instruction seto A quick look at the programming procedureo The programmer's modelo Instruction types and formatso Addressing modeso A tour of the instruction set

• Readings for instruction set:o Spasov, Chap. 2 and Appendix Ao HC11 Reference Manual, Appendix Ao HC11 Programming Reference Guide

SEGMENT code

Looking ahead at the programming procedure:

• Soon you'll write programs in assembly language for the HC11

• Here's a super simple example program:; Super simple test program ORG $B600

TLOOP:INCAINCB JMP TLOOP

• Before the HC11 can run this program,o The assembly-language code needs to be converted to machine

language, and the machine-language code needs to be transferred to the HC11's memory

Cont..


• Here is the machine code that results from the assembly-lang. program given above

Address Contents

$B600 01001100

$B601 01011100

$B602 01111110

$B603 10110110

$B604 00000000

Cont.


Putting it all togetherPutting it all together

Cont.

• try1.asm is a source file

o It is created by you, the programmer, using a text editor on your PC

o Format: HC11 assembly language (ASCII text)

• try1.lst is a listing file

o It is created by AS11.exe, the assembler/linker that runs on your PC

o (You'll probably run AS11.exe from DevHC11.exe)

o Its purpose of the file is to help you debug the program – Format: ASCII text


• try1.s19 is an object file

o It is created by AS11.exe, the assembler/linker

o Its purpose is to specify what bytes should be downloaded to the HC11, and to what locations in HC11 memory

o Format: Motorola S-record (ASCII text)

o Sometimes this is called a hex file

• The object file is converted to executable machine code

o The machine code is created by DevHC11.exe, the development environment that runs on your PC

Cont..


o Its purpose is to provide instructions and data to the HC11 Format: HC11 machine language (binary)

o Sometimes this is called the binary code

o The machine code is transferred to the HC11 through the coordinated efforts of DevHC11.exe (running on your PC) and the Buffalo monitor program (running on the HC11)

Programmer’s ModelProgrammer’s Model

• What features of the processor are most important to the assembly-language programmer?o Register set

o Memory organization

o Instruction set

o Addressing modes

• Here is the register set (again):

Cont.


Cont.

• Accumulatorso A: 8-bit general purpose accumulator

o B: 8-bit general purpose accumulator

o D: Double accumulator (concatenation of A and B for 16-bit operations)Most operations can be done using either accumulator A or B

• Index registerso X: 16-bit index register

o Y: 16-bit index register X and Y are used for indexed addressingX is preferred, usually, because addressing with Y is slower

and takes 1 extra byte of object code than with X


Operations on index registers:

o Simple operations (INC, DEC, and ADD from B) can be performed

o More complex operations are done by exchanging the index register and the D register, doing some computation, and then exchanging the values again

o X or Y is often loaded with the base address of the I/O register address space ($1000)

Cont.


• SP: 16-bit stack pointer Stack may be anywhere in

the 64 Kbyte address space The stack grows downward

in memory (i.e., a push decrements SP)

Cont.


Cont…

• PC: 16-bit Program Counter

• CCR: -bit Condition Code Registero H, N, Z, V, C: rithmetic status bits

N: Negative result Z: Zero result V: Overflow result C: Carry out from operation H: Carry from low nibble (4 bits) of accumulator

o S: Stop bit disabled =1 disables STOP instruction =1 after processor reset


o I: Interrupt mask =1 masks all maskable interrupts (not XIRQ) =1 after processor reset

o X: XIRQ interrupt mask =1 masks XIRQ =1 after processor reset (must be cleared just after reset)

Overview of the 68HC11 Overview of the 68HC11 instruction setinstruction set

• The instruction set specifies the kinds of data transfers and transformations that can occur in the machine

• Instructions can be grouped into 5 broad categorieso Data transfers: instructions that move data to and between

registers

o Logical: instructions that perform logic operations on data --AND, OR, etc.

o Arithmetic: addition, subtraction, increment, etc.

o Flow control: instructions that change the sequence of execution of a program --conditional and unconditional branches, stack operations, etc.

o Input / Output operations

Cont.


• An instruction generally consists of an opcode and some operand(s)

• HC11 instructions are of different lengths (1 to 5 bytes)

• The instruction set is summarized in Table A.1 of the text, Appendix A of the HC11 Reference Manual, and M68HC11 E Series Programming Reference Guide

o Lists instruction mnemonic, brief description of the operation, addressing modes available, machine code format of the instruction, timing information, and effect on condition code registers

Cont.


Cont.


• Opcode construction

o In general, an n-bit opcode is capable of specifying any one of 2n instructions

o With 8-bit opcodes, 256 distinct instructions are possible

o 68HC11 has more than 300 actual instructions

145 "basic" instructions plus “addressing variations”

1 or 2 bytes of storage specify the opcode!

• 1-byte opcodes

o Most opcodes use just 1 byte

o Downward compatible with 6801

Cont.


• 2-byte opcodes

o Most 2-byte instructions deal with register Y, which was not present in the 6801 processor

o It takes longer to fetch and execute 2-byte opcodes

o New instructions use a "pre-byte", which signals that another opcode byte follows:

$18, $1A, or $CD

Ex. INX $08

INY $18 $08

Cont.


• Instruction formato An instruction is made up of an opcode and a set of operands

Opcode may be one or two bytes Instructions may use 0, 1, 2, or 3 operands• Operands may be 1 or 2 bytes

o Instruction lengths range from 1 to 5 bytes o Example (assume this is stored at address $E000):

LDAA #$FF ; load ACCA with the ; Value $FF

Machine code: $E000 $86$E001 $FF

Cont.


• Fetch/Execute operation:

LDAA #$FF

First clock cycle

Cont.


• Fetch/Execute operation:

LDAA #$FF

Second clock cycle

Addressing modesAddressing modes

• How does the instruction specify the location of data?• The HC11 supports 5 different addressing modes

o Inherent Addressing Operands are specified implicitly in the opcode itself Operands are contained in the registers instead of memory Instruction length: or 2 bytes Examples:

• Register increment, clearsCLRA

• Register shift operationsASLA

• Register additionsABA

Cont.


• How does the instruction specify the location of data?• The HC11 supports 5 different addressing modes

o Inherent Addressing Operands are specified implicitly in the opcode itself Operands are contained in the registers instead of memory Instruction length: or 2 bytes Examples:

• Register increment, clearsCLRA

• Register shift operationsASLA

• Register additionsABA

Cont.


• Immediate addressing

One operand is included as part of the instruction word

Other operand (if needed) comes from an implied register

Instruction length: 2 -4 bytes

Specified operand is a constant and cannot be altered at run time

Mode is denoted by a # before the operand value

Example:

LDAA #$05

$86 $05

Cont.

Addressing modeAddressing mode• Direct addressing

The operand included in the instruction word is a memory address, specifying where the data is located

Second operand is an implied register Instruction length: 2 -4 bytes Since an address is specified, the data value itself can be

changed during program execution• Address is a constant Address included in the instruction word is only 1 byte• Direct addressing can only be used to reference locations

$0000 --$00FF --256 locationsExample: LDAA 05 $96 $05

Cont.

Addressing modeAddressing mode

• Extended addressing

Same as direct addressing, but with 2 bytes of address --the full range of addresses can be specified ($0000 to $FFFF)

Instruction length: 3 or 4 bytes

Example:

LDAA $0005

$B6 $00 $05

Why have both modes?

Cont.


• Indexed addressingThe effective address of the data in memory is

computed as the sum of the value contained in an index register (X or Y) and an offset (contained in the instruction word)

The offset is a 1-byte unsigned quantity » Useful for table and array access

Eg.DAA $56,X

$A6 56

Cont.


• Relative addressingSimilar to indexed addressing uses PC value

instead of the value in X or Y Instruction's offset value is added to the value in

the program counter to give the address of the next instruction

Used to specify branch addresses resulting from jump commands

Offset is an 8-bit 2's complement number --ranges from -128 to +127 decimal

Basic tour of the Basic tour of the instruction setinstruction set

• Load Instructionso Transfer data from memory to registero LDAA, LDAB, LDD, LDX, LDY, LDSo Different addressing modes supportedo Assume the following memory contents:

0050 40 41 42 43 44 45 46 47 -48 49 4a 4b 4c 4d 4e 4f2000 50 51 52 53 54 55 56 57 -58 59 5a 5b 5c 5d 5e 5f

LDAA #$56 ; ACCA$56 (immediate) LDAB $56 ; ACCB = $46 (direct) LDAA $2000 ; ACCA = $50 (extended) LDD $2002 ; ACCD = $5253 (extended)

Cont.


; CCA = $52, ACCB = $53 LDX #$2000 ; IX = $2000 (immediate) LDAA $C, X ; ACCA = $5C (indexed) LDY #$56 ; IY = $56 (immediate) LDAB 0, Y ; ACCB = $46 (indexed) LDX $5, X ; IX = ? (indexed)

• Store Instructionso Transfer data from register to memory o STAA, STAB, STD, STX, STY, STSo Direct, extended, or indexed addressing No immediate

addressing

Cont.


• Transfer Instructionso Transfer data from register to register

TAB ; ACCA ACCB�TBA ; ACCB ACCA�TAP ; ACCA CCR�TPA ; CCR ACCA�TXS ; IX SP�TSX ; SP IX�TYS ; IY SP�TSY ; SP IY�XGDX ; IX ACCD�XDGY ; IY ACCD�

Cont.


• Increment Instructions INC oprINCA INCB INX INY INS

• Decrement InstructionsDEC oprDECA DECB

Cont.


DEX DEY DES

• Clear InstructionsCLR oprCLRARotate Instructionso Shifts all 8 bits plus the Carry bit

circularly one position.ROL oprROLAROLB

Cont.


ROR oprRORARORB

o Note: 9 rotates puts data back in original position (not 8 as stated in text)

• Rotate InstructionsExampleAssume C = 1, ACCA =

$3B

Cont.


• Shift Instructionso Logical Shifts

LSL oprLSLALSLBLSLDLSR oprLSRALSRBLSRD

Cont.


• Shift Instructionso Arithmatic Shifts

ASL oprASLAASLBASLDASR oprASRAASRBASRD

Cont.

ASR preserves sign bit ASL/ASR can be used to

multiply/divide by 2 What is the difference

between ASL and LSL?


• Logical Instructionso Bit-wise AND

ANDA opr

ANDB opro Bit-wise OR

ORA opr

ORB opro Bit-wise Exclusive-OR

EORA opr

EORB opr

Cont.


o 1’s ComplementCOM oprCOMACOMB

• Arithmetic Instructionso Add instructions ABA ; ACCA + ACCB ACCA�ADDA opr ; ACCA + M ACCA�ADDB opr ; ACCB + M ACCB�ADDD opr ; ACCD + M ACCD�ADCA opr ; ACCA+ M+ C ACCA�

Cont.


ABX ; IX + ACCB IX �ABY ; IY + ACCB IY�o Subtract Instructions

SBA ; ACCA -ACCB ACCA�SUBA opr ; ACCA -M ACCA�SUBB opr ; ACCB -M ACCB�SUBD opr ; ACCD -M ACCD�SBCA opr ; ACCA -M -C ACCA�SBCB opr ; ACCB -M -C ACCB�

Cont.


• Arithmetic Instructionso Unsigned arithmetic

Numbers range from $00 to $FF (0 to 255)The carry bit (C) is set if result is outside range

o Signed arithmeticNumbers range from $80 to $7f (-128 to +127)The overflow bit (V) is set if result is outside rangeThe negative bit (N) is set if result is negative (same as

MSB of result)

Cont.


• Arithmetic instructionso The same instructions are used for both signed and unsigned

arithmetic The CPU does not care whether the values are signed or

unsigned

• The arithmetic result is the same for both cases

• C, V, and N bits are set based on Boolean combinations of the operands Programmer must keep track of whether values are signed

or unsigned

• Whether to use the C or V bit to check for overflow

Cont.


• Arithmetic Instructionso Example:

Add $56 + $B0• Unsigned: $56 + $B0 = $106 (86 + 176 = 262)• Signed: $56 + $B0 = $06 (86 + (-80) = 6) LDAA #$56 LDAB #$B0ABA ;ACCA = $06, C = 1, V = 0o Example:

Add $56 to $60 • Unsigned: $56 + $60 = $B6 (86 + 96 = 182)• Signed: $56 + $60 = $B6 (86 + 96 = -74!!!)

Cont.


LDAA #$56LDAB #$60ABA ;ACCA = $B6, C = 0, V = 1

• Multiplicationo MUL instruction

Multiplies 8-bit unsigned values in ACCA and ACCB, then puts the 16-bit result in ACCD

• Note that this overwrites ACCA and ACCB! o If you’re multiplying by a power of 2, you may want to use

ASL instructions instead Why?

Cont.


• Binary Fractionso Multiplying two 8-bit numbers gives 16-bit result. What if

you only want 8 bits?o Different ways to interpret 8-bit numbers

Unsigned integers 0 –255Signed integers -128 -+127Binary fractions 0 -1

• $00 = 0/256 = 0 • $80 = 128/256 = 0.5 • $FF = 255/256 = 0.9961

o You can use the ADCA instruction after a MUL to convert 16-bit result to 8-bit binary fractionMUL sets C to 1 if bit 7 of ACCB is 1

Cont.


• Binary Fractions o Example:

Multiply $20 x $35 (32 x 53 in decimal) Unsigned integers: • $20 x $35 = 32 x 53 = 1696 = $6A0

LDAA #$20 LDAB #$35 MUL ; ACCD = $06A0, C = 1

; ACCA=$06, ACCB=$A0Binary fractions:• (32 / 256) x (53 / 256) = 1696 / 65,536

Cont.


= 6.625 / 256 = 7 / 256 LDAA #$20LDAB #$35 MUL ; ACCD = $06A0, C = 1 ADCA #$00 ; now ACCA = $07

• Integer Divisiono IDIV

Divides 16-bit unsigned integer in ACCD by 16-bit unsigned integer in IX

Puts quotient in IX, remainder in ACCDo Example: 6 / 4

Cont.


LDD #$6 ; ACCD = $6 LDX #$4 ; IX = $4 IDIV ; IX = $1, ACCD = $2o Note: IDIV takes 41 cycles to execute

You can use ASR instructions to divide by powers of 2o Only gives you the quotient, not the remainder

o Divide by zero IX set to $FFFF, C set to 1

• Fractional Divisiono FDIV

Divides 16-bit binary fraction in ACCD by 16-bit fraction in IX

• 16-bit values between 0 and 1

Cont.


• 16-bit values between 0 and 1Puts quotient in IX, remainder in ACCDOften used to convert remainder from IDIV into a fraction Example: 6/4

LDD #$6 LDX #$4 IDIV ; IX = $1, ACCD = $2 STX Somewhere ; store quotient LDX #$4 ; reload denominator FDIV ; IX = $8000, ACCD = $0

; (Note $8000 = 0.5)

Cont.


• Floating point numberso Used to increase the range of number representation past that

of integer formatso Due to 8-bit CPU, IEEE floating point standard is not

supported on the HC11o Motorola has a non-standard formato Floating point routines can be downloaded from the Motorola

web site if you need these for projects (you will not need them for the labs)

• CCR OperationsCLC ; clear the C bitCLV ; clear the V bitSEC ; set the C bitSEV ; set the V bit

Cont.


o Can use SEC and CLC to set up the C bit prior to rotate instructions, for example

• “No Operation” Instruction NOPo Does nothing but increment the PCo Why would you need this?

• Compare Instructionso Compares two registers, or a register and a memory

location/immediate value Subtracts the two values

o Sets N, Z, V, C condition codes o Does not change operands

Cont.


CBA ; ACCA -ACCB CMPA opr ; ACCA -M CMPB opr ; ACCB –MCPD opr ; ACCD -M CPX opr ; IX -M CPY opr ; IY -M• Can be used to check if two values are equal, greater than/less

than, etc. Often used before conditional branch instruction

• Compare Instructions • Example: Assume the 16-bit value $5100 is stored at memory

location $2000: LDAA #$50

Cont.


• Bit Set/Clear Instructionso Used to set or clear multiple bits in a memory location

BSET opr mask

BCLR opr mask o 1’s in mask specify which bits are set or cleared. Other bits

are unaffected.

o Example: Assume IX = $20, memory location $34 contains the value $1A

BSET $14,X $31 ; now location $34 = $3B

BCLR $34 $1C ; now location $34 = $23

• Bit Test Instructions

Cont.


• Bit Test Instructionso Performs logical AND and modifies condition codes N and Z

(V is always cleared, C is unaffected)

o Does not modify the operands

BITA opr

BITB opro Example: Assume location $2000 contains the value $1A

LDAA #$3F

LDAB #$05

BITA #$03 ; N=0, Z=0 BITB $2000

; N=0, Z=1

Cont.


• Flow control with looping and branchingo Flow control is the

process ofMaking decisionsPerforming

operations in sequence

Repeating identical operations

• Fig 2.21 Flow control mechanisms

Cont.


• Relative addressing o Offset is added to the PC to cause the branch o 8-bit offset

Range is -128 to +127

o Destination address is actually relative to the address following the branch instructionWhy?

o Calculating destination addresses:PCnew = PCold + T + rel

PCold is address of branch instructionPCnew is destination address rel is the relative addressT is 2 for most instructions

Cont.


o T = 4 for BRCLR, BRSET with indexed addressing using IXo T = 5 for BRCLR, BRSET with indexed addressing using IY

• Relative addressing o The assembler usually handles the calculation of relative

addresses In your program, put a label on the destination instruction, and then the branch instruction can reference the label

o Example: ORG $B600

Label: LDAA $100 ; get current val INCA ; increment it

STAA $100 ; store updated val BRA Label ; repeat

Cont.


Object code: B600 B6 01 00 B603 4C B604 B7 01 00 B607 20 F7

• Conditional branchingo Here, the branch instruction checks if a (specified) condition

is true or falseUses condition codes in CCRo Use branch instruction after setting the condition codes If it is true, branch to target address If false --no branch, continue execution at the next

instructiono Uses only relative addressing to specify the target address

Cont.


Limited to 8-bit relative offsetTextbook shows a way to combine a conditional branch

with a JMP to overcome this limit• Conditional Branching

o Simple conditional branchesBCS rel ; branch if C=1 BCC rel ; branch if C=0 BMI rel ; branch if N=1 BPL rel ; branch if N=0 BVS rel ; branch if V=1 BVC rel ; branch if V=0 BEQ rel ; branch if Z=1 BNE rel ; branch if Z=0

Cont.


• Conditional Branching o Signed branches

Use when working with signed valuesBranches are based on N, Z, and V bits only

BGT rel ; greater than BLT rel ; less than BGE rel ; greater than or equal BLE rel ; less than or equal BEQ rel ; equal BNE rel ; not equal

• Conditional Branchingo Unsigned branches

Use when working with unsigned valuesBranches based on C and Z condition codes

Cont.


Note that Motorola uses the terms “greater than” and “less than” to refer to signed values, and “higher” and “lower” to refer to unsigned values

BHI rel ; higher BHS rel ; higher or same (same as BCC) BLO rel ; lower (same as BCS) BLS rel ; lower or same BEQ rel ; equal BNE rel ; not equal

Conditional branching can also be based on bit values in a particular memory value

o Format: BRCLR opr mask relBRSET opr mask rel

Cont.


o opr is the memory address (direct or indexed addressing is used)

o mask identifies the bits to check (set to 1, others are 0) in an AND format

o rel is the relative branch address

o Example: BRSET $10 $05 new Branch to address "new" if bits 0 and 2 of the value stored at

location $10 are both 1

• Fetch/Execute Operation o BNE LOOPo First clock cycle

Cont.


Cont.


• Fetch/Execute Operation o BNE OOP

o Second clock cycle

Cont.


• Fetch/Execute Operation o BNE OOP

o Third clock cycle

o New PC = $E012 + $FFF6 = $E008

Cont.


o How do we stop a program once its execution is finished?o What happens at the "end" of our program?

• STOPo This instruction stops the execution by disabling all system

clocks and putting the system in a minimum-power standby mode

o Only ways to recover from a STOP are:Perform a system RESET*Generate a valid system interrupt

o Avoid using this –catastrophic

• BRA $ or BRA *o Used in our text's examples

Cont.


o Infinite loop branching back on itselfo $ (or *) denotes "current" address (location of BRA

instruction)o Program never really terminates, so use with caution

• SWIo This instruction causes a software generated interrupt to occuro Upon occurrence, can jump to a location in memory and

execute what's found thereo Some systems use this approach to return to a monitor routine

after program execution is finished

Documents

MC68HC11 Instruction Set. Overview 68HC11 instruction set oA quick look at the programming procedure oThe programmer's model oInstruction types and formats