mblaze

Microblaze ”soft” IP from Xilinx

Soft IP Core “MicroBlaze”

• Soft Processor Core– 32-bit - Harvard Bus RISC Architecture– Size: 1000 Logic Cells– Speed: 150MHz, 125 MIPS in Virtex-II Pro– 32 General Purpose Registers; 3 Operand

Instruction Format

• IBM CoreConnnect Bus• Standard Peripheral

set

• GNU Development tools


Microblaze 32 RISC softcore

• 32-bit instruction word with three operands and two addressingmodes

• Separate 32-bit instruction and data buses that conform to IBM’sOPB (On-chip Peripheral Bus) specification

• Separate 32-bit instruction and data buses with direct connection to on-chip block RAM through a LMB (Local Memory Bus)

• 32-bit address bus


Microblaze 32 RISC softcore

• Single issue pipeline

• Instruction and data cache

• FSL (Fast Simplex Link) support

• Hardware multiplier (in Virtex-II and subsequent devices)


The MicroBlaze Soft Processor

~ 6% of XC3S1000

An Implementation Example


Microblaze Core Blockdiagram


General Purpose Registers



Machine Status Register (cont’d)


3-stage pipeline


Load/Store Architecture

• Microblaze use Big-endian addressing and can access memory in three data sizes:

1. Byte (8 bits)2. Halfword (16 bits)3. Word (32 bits)


Big-Endian Data Type


Instruction word format


Instruction Cache overview

Optional I-cache can be used when executing code residing outside the LMB address range.

• User selectable cacheable memory area• Configurable cache size and tag size• Individual cache line lock capability• Cache on/off controlled by bit in the MSR register• Instructions to write to the I-cache• Doesn’t require any specific memory controller• Little area (< 20 LUTs) and frequency impact• Can be used in conjunction with Instruction side LMB


Data Cache overviewOptional D-cache can be used when accessing data residing outside the

LMB address range.

• Write through policy• User selectable cacheable memory area• Configurable cache size and tag size• Individual cache line lock capability• Cache on/off controlled by bit in the MSR register• Instructions to write to the D-cache• Doesn’t require any specific memory controller• Little area (< 20 LUTs) and frequency impact• Can be used in conjunction with Data side LMB


Microblaze 32 RISC softcore – Bus interfaces

• OPB (On-chip Peripheral Bus) bus interface with byte-enable support

• LMB (Local Memory Bus) provides simple synchronous protocol for efficient block RAM transfers.

• LMB provides guaranteed performance of 125 MHz for local memorysubsystem.

• FSL (Fast Simplex Links) provides a fast non-arbitrated streamingcommunication mechanism.


Six different bus configurations


Use this configuration when the application requires more instruction and data memorythan is available in the on-chip block RAM (BRAM). Critical sections of instruction memory can be allocated to the faster ILMB BRAM to improve the application’s performance.


In this configuration, all of the instruction memoryis resident in off-chip memory


Use this configuration when your application code fits into the on-chip BRAM, but morememory may be required for data memory.


Use this configuration when the application requires more instruction and data memorythan is available in the on-chip BRAM. Critical sections of instruction memory can beallocated to the faster ILMB BRAM to improve the application’s performance.


Use this configuration when the application requires external instruction and datamemory. In this configuration, all of the instruction and data memory is resident in off-chipmemory.


Use this configuration when your application code fits into the on-chip ILMB BRAM, butmore memory may be required for data memory.


Microblaze 32 RISC softcore- FSL : Fast Simplex Links


The Designer’s Challenge

• How to partition between HW and SW to get the best cost and performance ?

– Hardware is fast and cost grows with complexity– Software is inexpensive and performance degrades with

complexity– Some functions are naturally meant to be implemented in

processors


Accelerating Software Example:Inverse Discrete Cosine Transform

• A typical software development starts as 100% “C”

• Performance profiling determines the critical paths

– IDCT function is in the critical path

– The system requirements are off by an order of magnitude


If All Code is Run in Software...

• Entire IDCT function takes 1144 clock cycles to execute

• 896 clock cycles (14*64) reside in the inner loop

IDCT Software Library

Main Software Calling IDCT Function

#include "mb_interface.h"

int main() {int indata[8], outdata[8];...xil_idct (indata, outdata);...

}

xil_idct (int *indata, int *outdata) {int i, j, k;int sum;

for (j = 0; j < 8; j++) {sum = 0;for (i = 0; i < 8; i++)

sum += (indata[i] * idct_constants[j][i]);

outdata[j] = (sum >> 2);outdata[j] = (int) DESCALE (outdata[j], 10);

}


“Xtreme Processing Acceleration”( Xilinx )

Option 1:Use small (200 LUTs)implementation of IDCT in

HW– only 107 clock cycles–– 10x faster10x faster

Option 2:Use fast (1,600 LUTs) implementation of IDCT in

HW– only 52 clock cycles–– 22x faster22x faster

FSLPorts

OPB PCI

IDCT Function in HWthrough FSL

Main Software Calling IDCT Function

#include "mb_interface.h"

int main() {int indata[8], outdata[8];…xil_idct_hw(indata, outdata);…

}

void xil_idct_hw(int indata[8], int outdata[8] {microblaze_bwrite_datafsl (indata[0], 0);microblaze_bwrite_datafsl (indata[1], 0);microblaze_bwrite_datafsl (indata[2], 0);microblaze_bwrite_datafsl (indata[3], 0);microblaze_bwrite_datafsl (indata[4], 0);

microblaze_bread_datafsl (outdata[0], 0);microblaze_bread_datafsl (outdata[1], 0);microblaze_bread_datafsl (outdata[2], 0);microblaze_bread_datafsl (outdata[3], 0);microblaze_bread_datafsl (outdata[4], 0);

}

IDCT Logic

IDCT Logic

FSLPorts


MicroBlaze FSL Accelerates System Performance

Control Tasks

Control Tasks

IDCT Function

C++ Code Stack

Control Tasks

IDCT Function

IDCT Function IDCT Function

Processing time

Traditional

XtremeProcessing

Parallel HW Acceleration

FSL

3

+

2

+

0 1

+

n

+

Processor(s) and HW on a single programmable platform


Microblaze 32 RISC softcore- FSL : Fast Simplex Links

FSL Read Instructions

Blocking Data Get Instruction:get regM, fslN

Non-blocking Data Get Instruction:nget regM, fslN

Blocking Control Get Instruction:cget regM, fslN

Non-blocking Control Get Instruction:ncget regM, fslN


FSL Write Instructions

Blocking Data Put Instruction:put regM, fslN

Non-blocking Data Put Instruction:nput regM, fslN

Blocking Control Put Instructioncput regM, fslN

Non-blocking Data Put Instruction:ncput regM, fslN


Microblaze 32 RISC softcore - Full documentation

Full Microblaze documentation can be found at :

www.xilinx.com/ise/embedded/mb_ref_guide.pdf

Also in the lab: Start -> Programs -> Embedded Development Kit 8.2i -> Documentation

And: Use the ”Help” button in EDK !

Documents

mblaze