M. Bharath Reddy (M.Tech. VLSI)

M. BHARATH REDDY 28-783B1, NGOSColony, Nandyal - 518501, Kurnool District, Andhra Pradesh Contact: +91-9912-342-2021, 09686480448, 09041012888 Email: bharathreddym91@rediffmail.com

Seeking assignments in

ELECTRONICS ENGINEERING / EMBEDDED SYSTEMS/ANALOG MIXED SIGNAL IC DESIGN with industrial experience of 2 years

WORK EXPERIENCE

Year Designation Job Description 2015 Scientist/Engineer-C at Indian Space Research

Organization (ISRO), Semiconductor Laboratory (SCL). Working as Analog IP design engineer at SCL ISRO. Designed a 3-bit 50Msps Flash ADC converter. Designed 8-bit segmented current-DAC. Has Experience in front end design and circuit simulations, physical design and physical verification (DRC, LVS) and post layout simulations.

2014 Worked as Design Engineer-1 at LSI Research and Development Pvt Ltd (An Avago Technologies Company)

Carried out verification of SOCs in test mode. Writing test-cases for standalone verification of IP’s in SOC.

2014 Graduate Technical Intern at Intel India Pvt Ltd Worked as Design Automation Engineer.

EDUCATIONAL CREDENTIALS

2014

2012

M. Tech (VLSI Design)

B.E.(Electronics & Communications Engineering)

VIT University

AVR&SVR College of Engineering, Nandyal

8.92

83.2 %

2008 Class XII (Intermediate) - AP Board Sri Chaitanya College 93.9 %

2006 Class X (SSC) - AP Board Chaitanya High School 83.0 %

TECHNICAL SKILLS

Chip design skills: Amplifiers, current mirrors, phase locked loop, CMOS logic styles, Latches , Knowledge on STA. Device physics: Strong foundation in diode, BJT, MOSFET physics Verification: System Verilog basics and UVM Methodology basics. Knowledge on AMBA AXI protocol. Programming Languages and HDL’S:Verilog, Assembly Language programming for 8085,PERL & TCL basics Software: Xilinx ISE Simulator, Altera (Quartus & Modelsim), Electronics: Analog and Digital Electronic Circuit Analysis and Design, Signals & Systems Tools: Cadence tools (virtuoso environment) Applications: MS Office 2003, 2007, 2010 (Word, Excel, Presentation, Power Point), Internet Applications

INTERNSHIP

Done Internship atIntel India Post Silicon Debugging through Debug Enhance Tool (DET): M. Tech Final Year Project Work

Design Automation Synopsis We have observed the chip in some buggy state and have no idea how that could have happened. This is one of the problems in post silicon validation. DET helps to explain about the inexplicably buggy state by enabling the back tracing capability in the design cycle.DET is a tool which links design database form RTL to schematics to Layout to actual sil icon . It saves debugging time by reducing the time to map signals from one domain to another domain (ex: logical domain to physical domain). Mapping is done by collecting design database at each level of abstraction of the design. I worked on the automation of the different flows of the tool by writing Perl scripts and provided tool support to the Debug team.

Learning

Learning about Perl scripting and automation. Leant about TCL basics.

Verification of AMBA AXI4 Protocol Project done for a certification course

System Verilog and UVM Synopsis The AMBA AXI protocol is targeted at high-performance, high frequency system designs and includes a number of features that make it suitable for a high-speed submicron interconnects. The AMBA AXI protocol is a standard bus protocol and most of the submicron interconnects supports AXI bus interface. AXI protocol is a complex protocol because of its ultra-high performance. Therefore a complete verification of such a protocol is necessary and challenging. To verify AXI protocol an efficient verification

M. Bharath Reddy (M.Tech. VLSI)

environment is needed and this environment has to be reusable for a wide range of functional IPs. Primary Features 1. Configurable Verification Environment. 2. Test Cases write to verify basic AXI protocol. Which include

Single write transaction (aligned and unaligned for INC burst type, aligned for wrap burst type) Single Read transaction. Multiple write transaction (Addresses with different ID tags). Out of Order read transaction.

3. Built in functional coverage. Learning Leant about AXI protocol

Leant about developing verification environment using UVM methodology.

ACADEMIC PROJECTS

Design of All Digital Phase Locked Loop (D-PLL) with Fast Acquisition Time M. Tech second semester Project

Verilog Synopsis Phase locked loops are widely used in frequency synthesis applications. For many portable applications the acquisition of the pll is very important so the design of pll’s with minimum acquisition time is the primary goal this work. Traditional Pll’s are ana log pll’s. However analog pll’s occupy large chip area due to the use of capacitors in the loop filter and also sensitive to noise. So a Digital Pll is designed with improved acquisition time and power efficiency.

Design Specifications Lock Range: 6.54MHz to 105MHz Power Dissipation: 7.763μW (at 210MHz)

Maximum Acquisition time: less than 18 cycles Supply Voltage: 1.2V

Programming Language: Verilog Software: The D-PLL is simulated using NC launch and synthesized using cadence RTL compiler in 45nm CMOS process technology

Learning

Practical learning of Digital Phase Locked Loops and their concepts. Leant about practical coding in Verilog

Modified FIR Filter Architecture to trade off filter performance

For Dynamic Power Consumption

M.Tech second semester project

Verilog Synopsis The growth in mobile computing and portable multimedia applications has increased the demand for low power digital signal processing (DSP) systems. One of the most widely used operations performed in DSP is finite impulse response (FIR) fi ltering. An architectural approach to the design of finite impulse response (FIR) fi lter for reduced dynamic power consumption with less area overhead is presented. The reduction of dynamic power is based on the concept of dynamic fi lter order Design Specifications Order: N=16 Input sequence and coefficients: 16-bit data Input and coefficient threshold: 5 & 20 MCSD window length: 4 Filter type: Sixteenth order Gaussian, low pass FIR fi lter Software: Cadence IUS Power Savings: 20 to 30% Learning

Designing of Low power FIR fi lter Architecture Leant RTL style coding

Design of CMOS Differential Ring Voltage Controlled Oscillator. M.Tech third semester project

Analog Synopsis The objective of this project is to design a four stage CMOS Differential Ring Voltage Controlled Oscillator suitable and to learn the key concepts in the design of VCO. The designed VCO has three blocks: the VCO unit circuit, the bias circuit for constant output voltage swing and the startup circuit. The VCO unit circuit is responsible for providing the voltage dependent oscil lations at the output. The bias circuit reduces output voltage swing variation and finally the startup circuit reduces the time r equired for the oscil lator to move from non-oscil lating state to oscil lating stage when it is powered up.

M. Bharath Reddy (M.Tech. VLSI)

Design Specifications Operating frequency range: 1.075 GHz to 2.56GHz Control Voltage Range: 960-1055mV Supply Voltage: 1.8V

Technology: 180nm Software: The designed VCO is simulated by using Cadence Virtuoso in 180nm technology.

Learning Leant about practical analog design challenges and biasing concepts .

Design of Operational Amplifier M.Tech third semester project

Analog Synopsis First stage is differential pair and second stage is common source stage. Miller compensation is used to make the op-amp stable.

Design Specifications Unity gain frequency: 10MHz Gain: 10000 Supply Voltage: 1.8V

Technology: 180nm Software: The designed OPAMP is simulated by using Cadence Virtuoso in 180nm technology.

Learning

Leant about basics of analog circuit design and biasing concepts.

Design and Implementation of FIR Filters with VHDL B. Tech Final Year Main Project VHDL Synopsis Digital filters are found everywhere in audio system applications. Therefore, the design of good digital fi lters is important in audio system applications. If one wishes to take advantage of the computational speed of FFT, then todesign fi lters, the finite duration impulse response is essential. IIR fi lters have excellent amplitude response at the expense of non-linear phase whereas FIR fi lters have exactly l inear phase. Thus , the design techniques of FIR fi lters are of significant interest. Design Specifications Order: N=16 Filter type: Symmetric/Anti Symmetric impulse response with even N(order) Programming Language: Very High Speed Integrated Circuit Hardware Descriptive Language(VHDL) Software: Xil inx ISE Simulator, Version:8.2

Learning Immense practical learning of FIR Filters and their functioning in audio systems Leant about practical coding in VHDL

ACTIVITIES AND INTERESTS

Activities

Presented a Technical Paper on Sub-mill imeter-Wave and Terahertz Region IC Devices

Presented a Technical Paper on FRAM (Ferro electric RAMs)

Participated in many Technical Quizzes conducted by various colleges

Achievements

Received outstanding performer’s o f the month, monthly award in Intel for generating and enabling DET database across different sites on time. While considering me for this award my performance is evaluated as against with regular employees and other interns in our team.

GATE Score: 558, Rank: 2785, Percentile: 96

Hobbies Numismatics (Coin Collection), Reading Newspapers, yoga

M. Bharath Reddy (M.Tech. VLSI)

PERSONAL INFORMATION

Date of Birth: 25Jul 1991 Gender: Male Nationality: Indian Languages Known: English, Telugu Permanent Address: 28-783B1, NGOS Colony, Nandyal - 518501, Kurnool District, Andhra Pradesh

References to be provided upon request