Mass production testing of the front-end ASICs for the ALICE SDD system L. Toscano a, R. Arteche Diaz b,d, S. Di Liberto b, M.I. Martínez a,c, S.Martoiu

Mass production testing of the front-end ASICs for the ALICE

SDD system

L. Toscanoa, R. Arteche Diazb,d, S. Di Libertob, M.I. Martíneza,c, S.Martoiua, G. Mazzaa, M.A. Mazzonib, F. Meddib, A. Rivettia,

F. Toselloa, G.M. Urciuolib and R. Wheadona

a INFN Sezione di Torino, Torino, Italyb INFN Sezione di Roma, Roma, Italy

c UNAM, Mexico City, Mexicod CEADEN, Havana, Cuba.

11th Workshop, Heidelberg, Sept 12-16,2005L. Toscano - INFN Torino

Outline

•SDD overview

•Front-end ASICs

•Test criteria and test set-up

•Test results

•Conclusions


The Inner Tracking System

The ITS: six layers of silicon detectors

Two layers of hybrid pixels Two layers of silicon drift

detectors Two layers of double sided

microstrips

The SDD layers Will have 260 SDDs Total area: 1.3 m2

About 130.000 electronic channels


SDD mechanical support

The SDD mechanical support is composed by carbon-fibre cones and cylinders:

Carbon-fibre structures called ladders form two layers: • 3rd with 14 units• 4th with 22 units

Ladders supported by rings SDD modules on ladder:

• detector• front-end electronics

End ladder cards• HV boards• LV boards• data compression • interface with the DAQ

Microcables• aluminium on Upilex• TAB-style bonding

rings

Ladders

cones


The front-end module

The silicon drift detector • 256 anodes each side

Two front-end hybrids: • based on two ASICs• 8 PASCAL and AMBRA

Two LV boards: • power supply • LVDS to CMOS • parameter monitoring

One HV board:• filter capacitors• voltage divider

The basic building block of SDD system is the module, composed by:

detector

front-end hybrids


PASCAL

•64 preamplifiers •64 channel SCA with 256 cells/channel

•32 10-bit ADCs•internal test-pulse generator•JTAG protocol•custom low power digital interface

PASCAL is a mixed-mode ASIC with 64 input channels:

Preamp Analog memorySAR ADC

PreampPreamp Analog memoryAnalog memorySAR ADCSAR ADC

Preamp Analog memorySAR ADC

PreampPreamp Analog memoryAnalog memorySAR ADCSAR ADC


AMBRA

• baseline subtraction (6-bit registers)• channel masking• compression (10 to 8 bits)• parity check (RAM & registers)• multiplexing• fully differential digital I/Os• addressable JTAG interfaceAMBRA compression curve

0

64

128

192

256

0 256 512 768 1024

Din(10 bits)

Do

ut(

8 b

its

)

AMBRA is a control, pre-processing and buffering ASIC:


The 8-inch wafer

• For cost reasons both ASICs fabricated using the same set of masks

• IBM Commercial technology

• Both ICs implemented in 0.25 m CMOS

• Each 8-inch wafer hosts about 146 testable couples PASCAL and AMBRA AMBRA

PASCAL

Preselection and characterization of AMBRA and PASCAL:

•On-wafer tests

•2 test procedures


PASCAL test procedure (1)

1. Power consumption test: measures Iadc, Ianlg and Idig without clock measures repeated with clock at 40MHz values in a reference range

2. ADC frequency test: at 40MHz or at 20MHz programmable via

JTAG ADC current value reduced at 20MHz

3. AM frequency test: at 40MHz or at 20MHz programmable via

JTAG internal test pulse generator measures test pulse signal position

The PASCAL chips test procedure consists of 6 tests:


PASCAL test procedure (2)

4. Noise test: measures the mean and rms for all channels performed at the low gain value parameters must be in range for all 64 channels

5. Baseline test: sets a sweep of baseline values via JTAG tests the baseline DAC linearity gain values must be in range for all 64 channels

6. Signal test: sets a sweep of test pulse values via JTAG checks the calibration DAC linearity gain values must be in range for all 64 channels


AMBRA test procedure

The AMBRA test procedure consists of one power consumptions test + 4 functional tests:

1. Power consumptions test: checks the I dd at 40MHz

checks Idde

2. Logic test A: handshake signals from/to

PASCAL data bus and flow control

signals multi event buffer mode

3. Logic test B: 10-to-8-bit compression baseline subtraction registers

4. Memory test: 4 memory buffers parity bit

5. JTAG test: W\R all JTAG

registers JTAG lines from/to

PASCAL


Test system set-up

Agilent E3631A Power

supplies

Agilent 16702B Logic

Analysis System

Test board

PC

Probe station

Chuck stage

Probe card

Vanl&Vdig CMOS signals

LVDS signals + Val

GPI B bus TCP/ I P

Wafer

y x

z

Minimal changes in the hardware:

2 full custom probe cards2 different test boards

Agilent 16702B Logic Analysis System for data acquisition (TCP/IP).

Test system controlled by a PC running dedicated software in LabView for data analysis

2 Agilent E3631A power supplies (GPIB)

The test system set-up is based on a semiautomatic Cascade Microtech probe station with motorized chuck stage for 8-inch wafers (GPIB):


AMBRA and PASCAL probe cards

Custom low power digital interface between AMBRA and PASCAL

On board digital buffers pseudo LVDS to LVDS standard conversion

Are required:


PASCAL selection criteria

The PASCAL chips are considered:

• Good, all six tests are passed with no errors

• Grey, the first three tests are passed, at least one of the last three is not passed

• Bad, all other ones

LabView front panel for PASCAL tests


AMBRA selection criteria

The AMBRA chips are preselected by this classification:

• Good, power consumption test and all four functional tests are passed with no errors

• Grey, power consumption test and functional tests are passed with no errors and no more than 128 memory bits are stuck

• Bad, all other ones

LabView front panel for AMBRA tests


PASCAL power test results (1)

ADC and analogue current values of 143 good PASCAL chips in wafer ALEQARX

Mean = 11.95 mA

= 0.24 mA (2.0%)

Mean = 68.22 mA

= 3.09 mA (4.5%)


PASCAL power test results (2)

Digital current values for 143 good PASCAL chips in wafer ALEQARX with clock at 40MHz:

• Mean value = 52.7mA

• = 0.41 mA (0.8%)


0

500

1000

1500

2000

2500

0,89 0,9 0,91 0,92 0,93 0,94 0,95 0,96 0,97

gain

Gain

gain 0.90000

Minimum 0.95000

Maximum 5069 Channels 0.92543

Mean 0.0073

Std Dev 0.00010

Std Error

chan

nels

5069 good PASCAL channels

On one wafer

Mean value = 0.925

= 0.007 (0.76%)

Typical voltage gain values for baseline DAC

PASCAL baseline test results


On 4 wafers

Mean value = 0.92

= 0.01 (1.13%)


PASCAL Signal test results

0

100

200

300

400

500

39,6 42 44,4 46,8 49,2 51,6

gain-good

Gain (mV/fC)

gain-good

40.450Minimum

51.290Maximum

5012channels

46.317Mean

1.6Std Deviation

0.023Std Error

C

H

A

N

N

E

L

S


On one wafer

Mean value = 46.3 mV/fC

= 1.6 mV/fC (3.5%)

Typical gain values for test pulse DAC


On 4 wafers

Mean value = 46.87 mV/fC

= 1.94 mV/fC (4.1%)


AMBRA power test results (1)

Values of I dd of 63 good AMBRA chips on wafer SK8MQHX:

• Mean value = 47.46 mA

• = 0.41 mA (0.86%)

0

5

10

15

20

46,2 46,6 47 47,4 47,8 48,2 48,6

Idd (mA)

# A

MB

RA


AMBRA power test results (2)

0

5

10

15

20

25

30

33 33,5 34 34,5 35 35,5 36 36,5 37

Idde (mA)

#AM

BRA

Values of Idde of 63 good AMBRA chips on wafer SK8MQHX:

• Mean value = 34.9 mA

• = 0.5 mA (1.43%)


PASCAL test map

105 151 152 153 154 155 156 157 158 159 160

135 136 137 138 139 140 141 142 143 144 145 146 147 148 149

117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134

98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116

77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97

56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76

37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55

20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

7 8 9 10 11 12 13 14 15 16 17 18 19

1 2 3 4 5 6

Wafer AXEQFNX

Good = 119 -> 81%

Grey = 15 -> 10.2%

Bad = 13 -> 8.8%

Tot = 147

First 12 wafers:

Good = 89%

Grey = 6%

Bad = 5% Good

Grey

Bad

Damaged


AMBRA test map

155 156 157 158 159 160 161

142 143 144 145 146 147 148 149 150 151 152 153 154

125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141

106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124

85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105

64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84

45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63

27 28 28 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

1 2 3 4 5 6 7 8 9 10 11

Wafer AXEQFNX

Good = 114 -> 75.5%

Grey = 13 -> 8.6%

Bad = 24 -> 15.9%

Tot = 151

Good

Grey

Bad

Damaged

First 12 wafers:

Good = 73%

Grey = 10%

Bad = 17%


A mass production testing system was required to test 2400 AMBRA + 2400 PASCAL for 260 SDD modules

The system is working efficiently at INFN in Rome Typical testing times are 510 seconds for PASCAL and

220 seconds for AMBRA 89% good PASCAL chips and 73% good AMBRA chips on

12 wafers

Conclusions

1.8 wafers/month

2800 PASCAL and 2400 AMBRA in February 2006

22 wafers to be tested to meet the requirements

Documents

Mass production testing of the front-end ASICs for the ALICE SDD system L. Toscano a, R. Arteche Diaz b,d, S. Di Liberto b, M.I. Martínez a,c, S.Martoiu