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7/30/2019 Masks and layouts vlsi
http://slidepdf.com/reader/full/masks-and-layouts-vlsi 1/29
Masks and Layouts
7/30/2019 Masks and layouts vlsi
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Introduction We’ve learned all of the “standard” DRs
EE271, taping out 0.8 to 0.25mm chips
There are also a number of newer DRs
For more advanced processes, fab steps
They may affect you in future tapeouts
A brief intro to some of these rules
Not sure what processes use these...
7/30/2019 Masks and layouts vlsi
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Outline New metal density rules
Antenna rules and proper application
Phase-shift region coloring
Optical proximity correction Odds and ends
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resist
Metal Density
Old rule: minimum metal density
For Al, metals were etched away
ILD
metal
High density Low density
This etching steptakes a lot longer
(“microloading”)
Solution: Add dummymetal structures hereto maintain minimummetal density
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Metal Density
New rule: max/min metal density
For Cu, metals are “poured” (damascene)
Review of dual-damascene
An amateur’s view of dual
damascene(“via-first” variation)
Ta barrier layerto prevent Cu fromdiffusing into Si
SiN layerfor etch stop
M2
M1
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Metal Density
Min rule: Ta barrier is hard to remove
Max rule: Cu metal is much softer than Ta “Selectivity” of Cu is 20x higher than for Ta
Low density:Mandate min. metal density
Barrier tough to remove
High density:Mandate max. density and width
Softness of Curesults in “dishing”
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Metal Density
Min density: Around 30%/layer, in stepped windows
Windows are around 1mmx1mm square, steps of ~100mm
“Dummification” metal structures required to add metal
Max density Around 70%/layer, again in stepped windows
Usually, max width + min spacing -> 90% density
Insert slots in lines or turn wide wires into parallel lines
Rules checked in Dracula (not Magic)
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• Reactive ion etch charges up metal lines – Charge can accumulate and zap a gate oxide
– If a gate sees a long metal before a diffusion does
Antenna Rules
m4
m3
m2
m1gate
100l
Safe: m3 is too short toaccumulate very muchcharge; won’t kill gate
gate
2000l
Dangerous: lots of m3; willprobably accumulate lots ofcharge and then blow oxide
diff diff
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diff
Antenna Rules
Two solutions: bridging and node diodes
Bridging attaches a higher layer intermediary
Diode is a piece of diffusion to leak away charge
m4
m3
m2m1
psub
gate
2000l
Bridging keeps gate awayfrom long metals until they
drain through the diffusion
gate ndiff
Node diodes are inactive duringchip operation (reverse-biased p/n);
let charge leak away harmlessly
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Antenna Rules Bridge or add node diodes if area ratio > limit
Most rulesets today use Sum(metal_area_not_tied_to_diff)/gate_area
Examples from previous slides
Be careful to account for etch rate!
Etching rates vary depending on geometries
May expose antennas of smaller or larger size Note: this applies to Al, not Cu damascene
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Antenna Rules
In areas of lower metal density (microloading)
Slower etch can imply longer-lasting “islands”
Large island of metal lasts for a shorttime, but can be enough to gather a fatalcharge, especially if node X were alreadyclose to the ratio limit
Node “x”
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Antenna Rules
In regions of lots of narrowly space wires
Can get a slower etch effect from “e- shading”
Especially if resist aspect ratio is high Etching particles don’t enter trench as easily
Differential in etch rates, creating islands of metal
a b c d
Node “c,” e.g., has an etch-antenna that includes “a,” “b,” and “d”
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Phase-Shifting Masks
Lithography uses (partially) coherent light
Wavelength today is 248nm; changes slowly
Kahng et. al., 1999 DAC
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Phase-Shifting Masks
PSM enables higher resolution patterning
Exploiting constructive/destructive light
Kahng et. al., 1999 DAC
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Phase-Shifting Masks
PSM done typically on poly and contact
Most critical layers for narrow lines; PSM $$$
Around any line, we need to flip phases This is a 2-coloring problem
0o
0o
0o 180o
180o
180o 0o
0o
0o 180o
180o
180o
Phase conflicthere will create anunwanted line; need“trim mask” to kill it
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Phase-Shifting Masks
Two principal design rule effects Orthogonal gates cannot be too close
Avoid interdigitating poly
These should be checkable directly in Magic
0o
180o
180o
Orthogonal gates need to haveincreased spacing to allow roomfor the 0o section to the right ofthe vertical gate
Trying to duck the poly-poly ruleby interdigitating the fingers is bad
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Optical Proximity Correction
Also known as serifs and dog-ears
Layout is not WYSIWYG anymore
Patterning through a reticle is tough
Holes in reticle act as low-pass filter Blurred edges
Squares in mask are blobby ovals in production We can predistort the image to compensate
Analogous to channel equalization
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Optical Proximity Correction
Standard fixes include:
Outside corner dog-ears
Inside corner cut-outs Long line embellishments
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Optical Proximity Correction
Example
Schellenberg et. al., 1999 SPIE
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Optical Proximity Correction This is a back-end flow, done after tape-out
Designers are unaware of OPC for the most part
Only real restriction: limit use of 45o routing 45o routes, with OPC, need more spacing to other wires
Only important to those of us who use Cadence tools...
OPC does explode the database size Imagine the size of a microprocessor database...
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Odds and Ends
Via spacing rules will change
Center-to-center instead of edge-to-edge Reflect the fact that vias are really more circular
Most efficient packing is not a rectangular array More like a checkerboard pattern
Checkable in Magic (shrink, then edge-edge)
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Odds and Ends EM rules are relaxed with Cu metal
Vias in Cu processes are also Cu (poured) Expect that via EM rules are also relaxed
However, vias have some EM problems Void formation at vias
Defects in the hole formed during the dielectric etch
Void formation along the Cu wire
Adhesion of the Cu to the barrier metal above isn’t great
Voids will travel down the wire and get “stuck” in the vias
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CMOS transistors are fabricated on silicon wafer
Wafers diameters (200-300 mm)
Lithography process similar to printing press
On each step, different materials are deposited,or patterned or etched
Easiest to understand by viewing both top andcross-section of wafer in a simplified
manufacturing process
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Inverter Cross-section
Typically use p-type substrate for nMOS transistors
Requires to make an n-well for body of pMOStransistors
n+
p substrate
p+
n well
A
YGND
VDD
n+ p+
SiO2
n+ diffusion
p+ diffusion
polysilicon
metal1
nMOS transistor pMOS transistor
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Well and Substrate Taps
Substrate must be tied to GND and n-well to VDD
Metal to lightly-doped semiconductor forms poor connection called Schottky Diode
Use heavily doped well and substrate contacts/taps(or ties)
n+
p substrate
p+n well
A
YGND VDD
n+p+
substrate tap well tap
n+ p+
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Inverter Mask Set
Top view Transistors and wires are defined by masks
Cross-section taken along dashed line
GND VDD
Y
A
substrate tap well tap
nMOS transistor pMOS transistor
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Detailed Mask Views
Six masks
n-well
Polysilicon
n+ diffusion
p+ diffusion
Contact
Metal
Metal
Polysilicon
Contact
n+ Diffusion
p+ Diffusion
n well
InIn reality >40 masks
may be needed
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End of session5/24/201329