Major Report New11

7/30/2019 Major Report New11

1/28

DESIGNING OF CMOS BASED LINEAR

FEEDBACK SHIFT REGISTER (LFSR) IN 0.35u

TECHNOLOGY

S ub m i tt e d B y - Priya Vinayak (9102310)

Aastha Gupta (9102312)

Sup ervi sed B y- Mr. Shamim Akhter

December 2012

Submitted in partial fulfilment of the Degree ofBachelor of Technology

DEPARTMENT OF ELECTRONICS AND COMMUNICATION

JAYPEE INSTITUTE OF INFORMATION TECHNOLOGY,

NOIDA


2/28

1


3/28

T AB LE OF CONTENT S

C h a p t e r N o . T op ics

Certificate from the Supervisor

P age N o .

3

Acknowledgement 4

Summary 5

Introduction 6

Chapter-1

Chapter-2

D Flip Flop

Contributional work

Conclusion

7

8-24

25

References (IEEE Format) 26

2


4/28

CE RT IFICATE

This is to certify that the major project, titled DESIGNING OF CMOS BASED LINEAR

FEEDBACK SHIFT REGISTER (LFSR) IN 0.35u TECHNOLOGY, submitted by Priya

Vinayak (9102310) & Aastha Gupta (9102312) of Jaypee Institute of Information

Technology, Noida has been carried out under my supervision.

Signature of Supervisor

Name of Supervisor .

Designation .Date .

3


5/28

ACKNOWLE DGEME NT

We are highly obliged and express great gratitude towards our project supervisor, Mr.

Shamim Akhtar for giving us suggestions, support and help. We are grateful to him for all his

assistance and guidance which motivated us to work on this topic and pursue it as our major

project. We are thankful to our lab assistant Mr Om Prakash, who was always there to help us

with the lab in the best possible way he could. We are also thankful to the authors of books and

papers we referred. We would also like to thank all those who gave me support for this project

in any way.

Date: ..

Name of Students:

PRIYA VINAYAK (9102310)

AASTHA GUPTA (9102312)

4


6/28

SUMMARY

Our aim in the major project was to create the layout of a LFSR i.e. linear feedback shift

register. Moreover the designing had to be done in 0.35u technology. Making a LFSR

essentially required us to make a basic block of a D flip flop first which had to be cascaded

to form a linear shift register according to the specified bit length and characteristic

polynomial. We adopted the bottom up approach and started by designing all the smaller

components needed in order to create the best topology for D flip flop. By best topology of D

flip flop, we mean a design which minimized the delay as well as power dissipation. Thus

we created schematics in Design architect for gates like NOT and NAND which were to be

used in designing DFF .Once we made a NAND gate, a symbol was created and those symbols

were instantiated to create a D flip flop. Similarly we also constructed D flip flop by

creating symbols for pass transistors and transmission gates and contrasted all these three

schematics for delay and power considerations. We also tried our hand at layout using IC

Station. We adopted the manual as well as SDL technique to create a net list for the inventor

and simulated it using ELDO. Literature review for LFSR was also done this semester and the

final specifications were finalized on which work will

commence from Jan 2013.

Signature of Student Signature of Supervisor Name NameDate Date

Signature of StudentName

Date

5


7/28

1 . INT RODUCTION

BR IE F IN SIG HT IN TO LFSR [ 1]

In c o m p u t in g, a linear feedback shift register (LFSR) is as hi f t r e g is t e r whose input bit is a

li n ea r function of its previous state.

The most commonly used li n e a r function of single bits is XOR. Thus, an LFSR is most often a

shift register whose input bit is driven by the e x c lu s ive - o r (XOR) of some bits of the overall

shift register value.

The initial value of the LFSR is called the seed, and because the operation of the register is

deterministic, the stream of values produced by the register is completely determined by itscurrent (or previous) state. Likewise, because the register has a finite number of possible states,

it must eventually enter a repeating cycle. However, an LFSR with a well-chosen feedback

function can produce a sequence of bits which appears random and which has a very long cycle.

Applications of LFSRs include generatingp s e ud o - r a n d o m n u m b e r s, p s e ud o - n o is e s e qu e n ce s,

fast digital counters, and wh it e n ing s e qu e n c e s. Both hardware and software implementations

of LFSRs are common.

The mathematics of a c y c li c r e d u n d a n c y c h ec k , used to provide a quick check

against transmission errors are closely related to those of an LFSR.

Fig 1.0,External feedback LFSR[7]

6
http://en.wikipedia.org/wiki/Computinghttp://en.wikipedia.org/wiki/Computinghttp://en.wikipedia.org/wiki/Shift_registerhttp://en.wikipedia.org/wiki/Shift_registerhttp://en.wikipedia.org/wiki/Linear#Boolean_functionshttp://en.wikipedia.org/wiki/Linear#Boolean_functionshttp://en.wikipedia.org/wiki/Exclusive-orhttp://en.wikipedia.org/wiki/Pseudorandomnesshttp://en.wikipedia.org/wiki/Pseudorandomnesshttp://en.wikipedia.org/wiki/Pseudorandomnesshttp://en.wikipedia.org/wiki/Scramblerhttp://en.wikipedia.org/wiki/Scramblerhttp://en.wikipedia.org/wiki/Cyclic_redundancy_checkhttp://en.wikipedia.org/wiki/Shift_registerhttp://en.wikipedia.org/wiki/Linear#Boolean_functionshttp://en.wikipedia.org/wiki/Linear#Boolean_functionshttp://en.wikipedia.org/wiki/Exclusive-orhttp://en.wikipedia.org/wiki/Pseudorandomnesshttp://en.wikipedia.org/wiki/Scramblerhttp://en.wikipedia.org/wiki/Cyclic_redundancy_checkhttp://en.wikipedia.org/wiki/Computing


8/28

D F LI P F L OP

The D flip-flop is widely used. It is also known as a data or delay flip-flop.

The D flip-flop captures the value of the D-input at a definite portion of the clock cycle (such

as the rising edge of the clock). That captured value becomes the Q output. At other times,

the output Q does not change. The D flip-flop can be viewed as a memory cell, a ze r o - o r d e r

h o ld , or a d e la y line.

Fig 1.1,DFF circuit

C I RC U I T O F T H E C L O C K I M P U L S E

Fig 1.2

7
http://en.wikipedia.org/wiki/Zero-order_holdhttp://en.wikipedia.org/wiki/Zero-order_holdhttp://en.wikipedia.org/wiki/Delay_linehttp://en.wikipedia.org/wiki/Delay_linehttp://en.wikipedia.org/wiki/Zero-order_holdhttp://en.wikipedia.org/wiki/Zero-order_holdhttp://en.wikipedia.org/wiki/Delay_line


9/28

3. CONTRIB UT IONAL WORK

3.1 Explore ELDO simulator by simulating a design entered from

Linux command prompt and verify the result through EZ waveform.

Steps:

1. Open the terminal window.

2. Write down the commands shown in picture.

3. Now to launch the simulator and EZ wave type the following commands in

shell csh

source /home/software/cshrc/ams.cshrc

4. Now write the netlist[5].

8


10/28

5. Save and exit.

6. In the terminal window change the permissions as

Chmod 777 filename.sp

7. Now simulate the file using ELDO simulator.

8. In shell prompt type

eldofilename.sp

9. Now the file is simulated using the ELDO simulator and the error and warnings (if any)

are displayed in the shell itself.

10. The simulation generates 5 files in the present working directory.

Filename.chi

Filename.id

Filename.sp

Filename.swd

Filename.wdb

11. Using the .wdb file well invoke waveforms through EZ waveform.

12. Type ezwave filename.wdb in shell prompt.

Output waveform of inverter simulated by ELDO

Fig 1.3

9


11/28

3.2Creating Schematic and simulating it using Mentor Graphics Design

Architect through a CMOS inverter [6].

1. Open the terminal window.

2. To launch design architect, at the prompt type:

csh

source /

home/software/cshrc/ams.cshrc

da_ic&

3. The Schematic sheet will get opened.

4. The components you will be using in this course are in the ADK IC Library. You can

add these components by clicking on the ADK IC Library button (right side of the

design window) and clicking on the desired component.

5. Using the Library place the required components (NMOS, PMOS, VDD, GND, IN and

OUT) for the inverter as shown below.

6. At this point, our schematic is almost complete. All the components have been placed

and wired together and you have assigned unique names to your inputs and outputs.

10


12/28

Schematic design of inverter in Design Architect[6]

Fig 1.47. We now need to verify the functional correctness of our inverter by simulating its

behaviour. To enter Simulation Mode.

8. Now run the simulation using RUN ELDO.

9. Using ezwave open the output screen.

Output waveform of inverter(schematic design) simulated by ELDO

Fig 1.5

NOTE: to observe perfect square wave shaped pulse the rise and fall times=0.001ns

11


13/28

1.4Creating a Symbol of the inverter made in schematic:

First we need to make schematic design of inverter, only after that wecan make symbol of it.

Fig 1.6, Inverter (schematic design)

Hierarchical design allows you to instantiate lower level cells (circuits) into upperlevel cells to create a tree structure. Since, at higher levels, we really don't need to seethe detailed transistor-level description of the base cells, we create symbols for them.Also we will use this symbol to perform various simulations on the circuit in thesimulation tutorial.

Make sure that the schematic is checked & saved before making the symbol.

To generate a Symbol Automatically:

To generate a Symbol Automatically select Tools -> Generate Symbol

In the Generate symbol dialog box,

ClickChoose shape.Notice that variety of shapes are available for the symbol and one can chooseanyof these shape that best describes the circuit.

Select Buffer and clickOK.

12


14/28

Do not change any other options in the dialog box and click the OKbutton

to generate a symbol for the cell.

The symbol is created automatically and displayed in a new window as shown below.

Do not forget to save this symbol by selecting Check & Save from the symbol_drawpalette on the right hand side. You can now use this symbol in other schemat ics. Youcan

edit symbol by selecting different shapes from right hand palette.

13


15/28

Using the above steps, the symbol of inverter is generated shown in the figure

below.

Similary Schematic design of NAND gate is made .

The symbol generated forNAND gate.


16/28

14


17/28

Using the symbols of inverter and NAND a DFF is made.

Similarly Symbol of DFF wasgenerated

15


18/28

Output waveform of DFF(using NAND and Inverter symbols)

Layout and Layout Verification of an Invertor Circuit

We can make layout using SDL as well as manually. First we made manually, later on

net list is generated using DRC/LVS which is simulated using ELDO

1.4.1 Steps to create manual layout

Drawing theLayoutIn the working space, one unit is equal to one Lambda ().(refer to the cursor

coordination on the window frame). If you follow the Lambda rules for TSMC0.35u

technology, the smallest feature size will be 2= 0.35u (for poly width and contact

size). Therefore we have 1= 0.175micron.

16


19/28

After making the active area and wells, the layout looks like the following

Procedure to add PORTS

When we add ports, the following layer palette comes up.

17


20/28

The final completed layout of inverter looks like this.

DRC/LVS

To Run DRC: File ->Cell ->Set Logic Source

Mentor Graphics window Pops up

Select ->Schematic ->OK

From Menu bar:

Click Calibre->Run DRC

Calibre Interactive_nmDRC window pops up

Select Run DRC on left panel

The following Calibre window opens.

18


21/28

LVS:From Menu Bar:

Click on Calibre Run LVS

Calibre Interactive _nmLVS window pops up

Select Run LVS (on left panel of window)

The final net list of an inventor looks like this

19


22/28

The net list when simulated by ELDO, generates the following output.

3.5.2 Creating Layout using SDL

Steps to create SDL

Schematic driven layout is the concept in I C L a y o ut orP C B layout where the

E DA s o f t w a r e links the schematic and layout databases.Schematic driven layout allows for

several features that make the layout designer's job easier and faster. One of the most

important features of SDL is that changes to the circuit schematic are easily translated to

the layout. Another is that the connections between components in the schematic are

graphically displayed in the layout ensuring work is correct by construction.

Click on Create SDL in session palatte.

Logic Source: EDMM Viewpoint.

Path to Viewpoint: $MGC_WD//sdl

Cell Leaf Name: Root Component

Layout Directory: $MGC_WD

Process Name: $ADK/technology/ic/process/

Rule File: $ADK/technology/ic/process/ Open Setup -> SDL

Click on MOS Folding -> Setup, then define MOS Folding

Click on SDL Port Style -> Setup and do as shown in figure and press OK.

20
http://en.wikipedia.org/wiki/Integrated_Circuit_Layouthttp://en.wikipedia.org/wiki/Printed_circuit_boardhttp://en.wikipedia.org/wiki/Electronic_design_automationhttp://en.wikipedia.org/wiki/Integrated_Circuit_Layouthttp://en.wikipedia.org/wiki/Printed_circuit_boardhttp://en.wikipedia.org/wiki/Electronic_design_automationhttp://en.wikipedia.org/wiki/Electronic_design_automation


23/28

Click on AutoInst on DLA Logic Palette. It will place the both NMOS and PMOSlayout on the cell window as shown in figure.

Follow instructions prompted by DRC to complete the layout.

21


24/28

3.5 Topologies of D FLIP FLOP

In order to make a D Flip flop we have used the following two topologies

1. Pass transistor

2. Transmission Gate

3.5.1 Construction of a basic transmission gate

Output of a transmission gate

22


25/28

Now constructing the DFF using transmission gate (symbol) made from

schematic design.

3.5.2 Construction of DFF using pass gate.

For the construction of DFF using pass gate, we need to make NAND gate using PassGate and then implement it.

3.5.2.1 Construction of NAND gate using pass gate

Output of NAND gate using pass gate

23


26/28

Constructing DFF using Pass gate

Outputs of DFF using Transmission gate, pass gates and NAND gates

24


27/28

CONCL USION

Our aim this semester was to come up with the optimal design of D flip flop so that the

layout of LFSR made will have the minimum delay and power considerations. Following

were the observations we made:

T y pe o f DFF P o w e r

D iss ip a t io n

Using MOS

NAND logic

5.3016 Nano

watts

Using Pass

transistor logic

1.2812 m watts

Using

transmission

gates

9.0746 Nano

watts

Thus from the above table we can conclude that making a flip flop using NAND gates

would be the optimized approach. A close second option is Transmission gates and we

could try some other schematics of DFF by TG to find out the most suitable combination.

We will analyse the delay constraints in the next semester.

25


28/28

RE FE RENCE S

[1]. LFSR Counter Implementation in CMOS VLSI, By Doshi N. A., Dhobale S. B.,and

Kakade S. R.

[2]. Design Architect Users Manual, Software Version 8.5_1.

[3]. Schematic design with design architect using Mentor, By George A. Mark

[4]. IC Station Users Manual, Software Version 8.9_9.

[5]. HSPICE Command Reference Version X-2005.09, September 2005, By SYNOPSYS.

[6]. Design and simulation an inverter, Tutorial for IC design using mentor graphics,

by Wei Wang and Dongsoo S. Kim

[7]. www .markharvy. c om. info/ fpga/ lfsr
http://c/Users/Aastha/Downloads/%C3%A2%E2%82%AC%C5%93www.markharvy.com.info/fpga/lfsr%C3%A2%E2%82%AC%C2%9Dhttp://c/Users/Aastha/Downloads/%C3%A2%E2%82%AC%C5%93www.markharvy.com.info/fpga/lfsr%C3%A2%E2%82%AC%C2%9D

Documents

Major Report New11