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MAIN MEMORY SYSTEM
CS/ECE 6810: Computer Architecture
Mahdi Nazm Bojnordi
Assistant Professor
School of Computing
University of Utah
Overview
¨ Announcement¤ Homework 4 submission deadline: Nov. 6th
¨ This and the following lectures¤ Dynamic random access memory (DRAM)¤ DRAM operations¤ Memory scheduling basics¤ Emerging memory technologies
Recall: Address Translation
¨ Exploit locality to reduce address translation time¤ Offset bits are copied from virtual address
Physical MemoryPage
Frame 0Page
Frame 1Page
Frame 2
Page Frame N-1
…
Virtual Address
Physical Address
offset
offset
Virtual Page No
Page frame No
Recall: Address Translation
¨ Exploit locality to reduce address translation time¤ OS maintains the page table for address translation
Physical MemoryPage
Frame 0Page
Frame 1Page
Frame 2
Page Frame N-1
…
Virtual Address
Physical Address
offset
offset
Virtual Page No
Page frame No
Page Table
Recall: Translation Lookaside Buffer
¨ Exploit locality to reduce address translation time¤ Keep recent translation in a buffer for future references
Physical MemoryPage
Frame 0Page
Frame 1Page
Frame 2
Page Frame N-1
…
Virtual Address
Physical Address
offset
offset
Virtual Page No
Page frame No
Page Table
0101
TLB
TLB in Memory Hierarchy
¨ On a TLB miss, is the page loaded in memory?¤ Yes: takes 10’s cycles to update the TLB¤ No: page fault
n Takes 1,000,000’s cycles to load the page and update TLB
Processor Core
TLB Lookup
CacheMain
MemoryVA
hitPA miss
Data
hit
TLB in Memory Hierarchy
¨ On a TLB miss, is the page loaded in memory?¤ Yes: takes 10’s cycles to update the TLB¤ No: page fault
n Takes 1,000,000’s cycles to load the page and update TLB
Processor Core
TLB Lookup
CacheMain
MemoryVA
hitPA miss
Translaltion
miss
Data
hit
TLB in Memory Hierarchy
¨ On a TLB miss, is the page loaded in memory?¤ Yes: takes 10’s cycles to update the TLB¤ No: page fault
n Takes 1,000,000’s cycles to load the page and update TLB
Processor Core
TLB Lookup
CacheMain
MemoryVA
hitPA miss
Translaltion
miss
Data
hit
Physically indexed, physically tagged: TLB on critical path!
Physically Indexed Caches
¨ Problem: increased critical path due to sequential access to TLB and cache
Virtual Page No Page Offset
TLB
Physical Frame Page Offset
Physically Indexed Caches
¨ Problem: increased critical path due to sequential access to TLB and cache
Virtual Page No Page Offset
TLB
Physical Frame Page Offset
Tag Array Data Array
= Data Block
hit/miss*
Tag Index Byte
Physically Indexed Caches
¨ Problem: increased critical path due to sequential access to TLB and cache
Virtual Page No Page Offset
TLB
Physical Frame Page Offset
Tag Array Data Array
= Data Block
hit/miss*
Tag Index Byte
Observation: lower address bits (page offset) are not
translated
Virtually Indexed Caches
¨ Idea: Index into cache in parallel with page number translation in TLB
Virtual Page No Page Offset
TLB
Tag Array Data Array
= Data Block
hit/miss*
Tag
Index Byte
Virtually Indexed Caches
¨ Idea: Index into cache in parallel with page number translation in TLB
Virtual Page No Page Offset
TLB
Tag Array Data Array
= Data Block
hit/miss*
Tag
Index Byte
what if the page offset is not equal to index+byte?
Main Memory
Computer System Overview
¨ DRAM technology is commonly used for main memory
Computer System Overview
¨ DRAM technology is commonly used for main memory
CPU
Computer System Overview
¨ DRAM technology is commonly used for main memory
CPU
Memory
Computer System Overview
¨ DRAM technology is commonly used for main memory
CPU
Memory
¨ SRAM is used for caches
¨ DRAM is used for main memory
¨ DRAM is accessed on a TLB or last level cache miss
Static vs. Dynamic RAM
Static RAM (SRAM) Dynamic RAM (DRAM)
wordline
bitline bitline
wordline
bitline
Static vs. Dynamic RAM
¨ Fast and leaky¤ 6 transistors per bit¤ Normal CMOS Tech.
¨ Static volatile¤ Retain data as long as
powered on
¨ Dense and slow¤ 1 transistor per bit¤ Special DRAM process
¨ Dynamic volatile¤ Periodic refreshing is
required to retain data
Static RAM (SRAM) Dynamic RAM (DRAM)
DRAM Organization
¨ DRAM array is organized as rows�columns
DRAM Organization
¨ DRAM array is organized as rows�columns
wordline
bitline
DRAM Organization
¨ DRAM array is organized as rows�columnsde
code
r
wordline
bitline
DRAM Organization
¨ DRAM array is organized as rows�columnsde
code
r
Sense Amplifier
row buffer
wordline
bitline
DRAM Organization
¨ DRAM array is organized as rows�columnsde
code
r
Sense Amplifier
row buffer
wordline
bitline
Data Block
multiplexer
DRAM Organization
¨ DRAM array is organized as rows�columnsde
code
rRow Address
ColumnAddress
Sense Amplifier
row buffer
wordline
bitline
Data Block
multiplexer
DRAM Organization
¨ DRAM array is organized as rows�columnsde
code
rRow Address
ColumnAddress
Sense Amplifier
row buffer
wordline
bitline
Data Block
multiplexer All reads and writes are performed through the
row buffer
DRAM Row Buffer
¨ All reads and writes are performed through RB
Data Array
Row Buffer (RB)
DRAM Cell
DRAMSense Amp.
Row Access Strobe (RAS)
Column Access Strobe (CAS)
Reading DRAM Cell
¨ DRAM read is destructive¤ After a read, contents of cells are destroyed
Precharge Activate Sense
Reading a zero
Reading a one
Reading DRAM Cell
¨ DRAM read is destructive¤ After a read, contents of cells are destroyed
Precharge Activate Sense
Reading a zero
Reading a one
0V/2
?
Reading DRAM Cell
¨ DRAM read is destructive¤ After a read, contents of cells are destroyed
Precharge Activate Sense
Reading a zero
Reading a one
0V/2
?
1V/2
?
Reading DRAM Cell
¨ DRAM read is destructive¤ After a read, contents of cells are destroyed
Precharge Activate Sense
Reading a zero
Reading a one
0V/2
?
1V/2
?
1V/2 + �
0
Reading DRAM Cell
¨ DRAM read is destructive¤ After a read, contents of cells are destroyed
Precharge Activate Sense
Reading a zero
Reading a one
0V/2
?
1V/2
?
1V/2 + �
0
0V/2
?
Reading DRAM Cell
¨ DRAM read is destructive¤ After a read, contents of cells are destroyed
Precharge Activate Sense
Reading a zero
Reading a one
0V/2
?
1V/2
?
1V/2 + �
0
0V/2
?
1V/2
?
Reading DRAM Cell
¨ DRAM read is destructive¤ After a read, contents of cells are destroyed
Precharge Activate Sense
Reading a zero
Reading a one
0V/2
?
1V/2
?
1V/2 + �
0
0V/2
?
1V/2
?
1V/2 - �
V