MACH TTL CMOS.pdf

8/19/2019 MACH TTL CMOS.pdf

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Lecture:

DIGITAL SYSTEMS

Nguyen Thanh Hai, PhD

Chapter 8:

Integrated Circuit s

University of Technical Education

Faculty of Electrical & Electronic Engineering


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Integrated Circuits

2Nguyen Thanh Hai, PhD

8.1 TTL and CMOS Families

8.2 Data sheet

8.3 The loading and the Fan-out

8.4 Open-Collector/Open-Drain Outputs

8.5 Tristate (Three-State) Logic Outputs

8.6 TTL Driving CMOS

8.7 CMOS Driving TTL


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Integrated Circuits


8.1 TTL and CMOS Families

CMOS FamilyTTL Family

Large

impendence

Ohm law:

R=U/I

Complementary metal –oxide –semiconductor (CMOS)Transistor

–Transistor Logic (TTL)

B

C

E


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8.2 Data sheet


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8.2 Data sheet


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-VIH (min) – High - Level Input Voltage

-VIL(max) – Low - Level Input Voltage

-VOH (min) – High - Level Output Voltage-VOL(max) – Low - Level Output Voltage

-IIH High - Level Input Current

-IIL Low - Level Input Current

-IOH High-Level Output Current

-IOL Low - Level Output Current

8.3 TTL Loading and the Fan-out


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Performance ratings 74 74S 74LS 74AS 74ALS 74F

Propagation delay (ns) 9 3 9.5 1.7 4 3

Power dissipation (mW) 10 20 2 8 1.2 6

Speed-power product (pJ) 90 60 19 13.6 4.8 18

Max. clock rate (MHz) 35 125 45 200 70 100

Fan-out (same series) 10 20 20 40 20 33

Voltage parameters

VOH(min)_V 2.4 2.7 2.7 2.5 2.5 2.5

VOL(max)_V 0.4 0.5 0.5 0.5 0.5 0.5

VIH(min)_mV 2.0 2.0 2.0 2.0 2.0 2.0

VIL(max)_mV 0.8 0.8 0.8 0.8 0.8 0.8

Table-1



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Source


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Sink


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- To calculate for driving many inputsOLI ILI

ILI

ILI


-Output of a logic gate can drive inputs

-Fan-out is also called loading factor:

the fan-out value of the output can drive

the maximum number of the logicinputs.


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U i it f T h i l Ed ti


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Example 8.1: How many 74ALS00 NAND gate inputs can be

driven by a 74ALS00 NAND gate output?

Solution: According to 74ALS00 data sheet, one finds

IOL(max) = 8 mA (Low output); IIL (max) = 0.1 mA (Low input)

IOH(max) = 400 uA (High output); IIH(max) = 20 uA (High input)

Fan-out

•Fan-out (LOW) = IOL(max)/IIL(max)=8 mA/0.1 mA = 80. Then, the

number of inputs possibly driven in the LOW state is 80.

•Fan-out (HIGH) = IOH(max)/IIH(max)=400 uA/20 uA = 20. Then, the

number of inputs possibly driven in the HIGH state is 20.

•High and Low states are not the same, so we can choose so that the

74ALS00 can drive up to 20 other 74ALS00 NAND gates.



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Example 8.2: A 74LS00 NAND gate output is driving three 74SXX gate

inputs and one 7406 input. Determine if there is a loading problem.

Solution:

1. Add all of the IIH values:

3.(IIH for 74S) + 1.(IIH for 74)

Total = 3.(50 uA) + 1.(40 uA) = 190 uA

IOH for the 74LS output is 400 uA (max) > 190 uA. This satisfies the

HIGH output.

2. Add all of the IIL values:

3.(IIL for 74S) + 1.(IIL for 74)

Total = 3.(2 mA) + 1.(1.6 mA) = 7.6 mA

IOL for the 74LS output is 8 mA (max) > 7.6 mA. This satisfies the LOW

output.



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Q3 ON V0 = VOL ≤ 0.4 V

Q3 OFF V0 = VOL = +5 V

0V

)(

R p

external

Rp = 10k is small enough for the

minimum below VOH and IOL(max)

Rp is connected

outside

V0 at the

output



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Symbolizes the

wired-AND

connection

A

B

C

k 10

V5

C.B.AOutput

A

B

C

drain)-(open74HC05or collector)-(open74LS05

-Only pulling outputs LOW

-Sharing the same wire for transmitting in a logic level



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Transistor shown for illustrative purposes

Q

CLK

J

K

0V

mA25V,24740674LS112

Q

V24

-7406 buffer between FF and Lamp

-Lamp acting as the pull-up resistor for the open-collector output

-Q = 1, the lamp is on and otherwise Q = 0, it is off.



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-In this case, 7406 open-collector output is to drive an indicator LED.

-The resistor Rs is for limiting the current

Q

CLK

D

s R

740674HCT74

Q

V5



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V

LOW HIGHON

OFF

enabled

1OE (a)

V

HIGH LOW

ON

OFF

enabled

1OE (b)V

LOW

or

HIGH

Z-HIOFF

disabled

0OE

OFF

(c)



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Integrated Circuits



A74LS125

X

E

0

1

A

Hi-Z

E X

0

1

Hi-Z

A

A74LS126

X

E

E X



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A

74LS126

AE

B

bus

Common

BE

C

circuits

other To

CE

A

74LS126

X

AE

B

Disabled

BE

C

circuits

other To

CE

X

V5

Disabled

Enabled



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8.6 TTL Driving CMOS

k 10

CMOS TTL

V5

External pull-up

resistor is used

when TTL drive

COMS

K 10

74LS07

V5

Q

CLK

J

K

74LS112

Q

V10

CMOS

A 7407 open-

collector buffer canbe used to interface

TTL to high-voltage

COMS

TTL

TTL



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Integrated Circuits


8.7 CMOS Driving TTL

A 4050B buffer simply passes the 4001B output signal to the 74LS loads

with the assurance that a logic “0” will pull LS inputs to their LOW state.

A

4050B

B

V5 DDV

C

0

V51

DDV

V51 V50

4001B74LS00

CMOS

VDD=+15V

CMOS

VDD

=+5VCMOS

VCC=+5V

V5CC V


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Integrated Circuits


Example 8.4:



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Integrated Circuits


Example 8.5:



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Example 8.6:



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-Take a look Examples from pages

- Answer Review questions

- Homework



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30N Th h H i PhD

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MACH TTL CMOS.pdf