M28W640FCB

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PRELIMINARY DATA

April 2005

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

M28W640FCT

M28W640FCB

64 Mbit (4Mb x16, Boot Block)3V Supply Flash Memory

FEATURES SUMMARY SUPPLY VOLTAGE

VDD = 2.7V to 3.6V Core Power Supply

VDDQ= 1.65V to 3.6V for Input/Output

VPP = 12V for fast Program (optional)

ACCESS TIME: 70, 85, 90,100ns

PROGRAMMING TIME:

10s typical

Double Word Programming Option

Quadruple Word Programming Option

COMMON FLASH INTERFACE

MEMORY BLOCKS

Parameter Blocks (Top or Bottomlocation)

Main Blocks

BLOCK LOCKING

All blocks locked at Power Up

Any combination of blocks can be locked

WP for Block Lock-Down SECURITY

128 bit user Programmable OTP cells

64 bit unique device identifier

AUTOMATIC STAND-BY MODE

PROGRAM and ERASE SUSPEND

100,000 PROGRAM/ERASE CYCLES perBLOCK

ELECTRONIC SIGNATURE

Manufacturer Code: 20h

Top Device Code, M28W640FCT: 8848h

Bottom Device Code, M28W640FCB:8849h

PACKAGES

Compliant with Lead-Free SolderingProcesses

Lead-Free Versions

Figure 1. Packages

TSOP48 (N)

12 x 20mm

FBGA

TFBGA48 (ZB)

6.39 x 10.5mm

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M28W640FCT, M28W640FCB

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TABLE OF CONTENTS

FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 1. Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 3. TSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 4. TFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 5. Block Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 6. Protection Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Address Inputs (A0-A21). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Data Input/Output (DQ0-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Write Protect (WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Reset (RP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

VDD Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

VDDQ Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

VPP Program Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

VSS Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Read.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Automatic Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 2. Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Read Memory Array Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Read Status Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Read Electronic Signature Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 3. Command Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Read CFI Query Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Double Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Quadruple Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

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Clear Status Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Program/Erase Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Program/Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Protection Register Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Block Lock Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Block Unlock Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Block Lock-Down Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 4. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 5. Read Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 6. Read Block Lock Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 7. Read Protection Register and Lock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 8. Program, Erase Times and Program/Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . 16

BLOCK LOCKING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Reading a Blocks Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Locked State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Unlocked State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Lock-Down State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Locking Operations During Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 9. Block Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 10. Protection Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Program/Erase Controller Status (Bit 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Erase Suspend Status (Bit 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Erase Status (Bit 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Program Status (Bit 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

VPP Status (Bit 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Program Suspend Status (Bit 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Block Protection Status (Bit 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Reserved (Bit 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 11. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 12. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 13. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 7. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 8. AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 14. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 15. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 9. Read AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 16. Read AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 10.Write AC Waveforms, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 17. Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

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Figure 11.Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 18. Write AC Characteristics, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 12.Power-Up and Reset AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 19. Power-Up and Reset AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 13.TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline . . . . . . . . . 30

Table 20. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data . 30

Figure 14.TFBGA48 6.39x10.5mm - 8x6 ball array, 0.75mm pitch, Bottom View Package Outline 31

Table 21. TFBGA48 6.39x10.5mm - 8x6 ball array, 0.75mm pitch, Package Mechanical Data . . . 31

Figure 15.TFBGA48 Daisy Chain - Package Connections (Top view through package) . . . . . . . . 32

Figure 16.TFBGA48 Daisy Chain - PCB Connections proposal (Top view through package) . . . . 32

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 22. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33Table 23. Daisy Chain Ordering Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

APPENDIX A.BLOCK ADDRESS TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 24. Top Boot Block Addresses, M28W640FCT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 25. Bottom Boot Block Addresses, M28W640FCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

APPENDIX B.COMMON FLASH INTERFACE (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 26. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 27. CFI Query Identification String. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 28. CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 29. Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 30. Primary Algorithm-Specific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 31. Security Code Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

APPENDIX C.FLOWCHARTS AND PSEUDO CODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 17.Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 18.Double Word Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 19.Quadruple Word Program Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 20.Program Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . 47

Figure 21.Erase Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 22.Erase Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . 49Figure 23.Locking Operations Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 24.Protection Register Program Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . 51

APPENDIX D.COMMAND INTERFACE AND PROGRAM/ERASE CONTROLLER STATE. . . . . . . . 52

Table 32. Write State Machine Current/Next, sheet 1 of 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 33. Write State Machine Current/Next, sheet 2 of 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 34. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

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SUMMARY DESCRIPTIONThe M28W640FCT and M28W640FCB are 64Mbit (4 Mbit x 16) non-volatile Flash memories thatcan be erased electrically at block level and pro-

grammed in-system on a Word-by-Word basis us-ing a 2.7V to 3.6V VDD supply for the circuitry anda 1.65V to 3.6V VDDQ supply for the Input/Outputpins. An optional 12V VPP power supply is provid-ed to speed up customer programming.

The devices feature an asymmetrical blocked ar-chitecture. They have an array of 135 blocks: 8Parameter Blocks of 4 KWord and 127 MainBlocks of 32 KWord. The M28W640FCT has theParameter Blocks at the top of the memory ad-dress space while the M28W640FCB locates theParameter Blocks starting from the bottom. Thememory maps are shown in Figure 5., Block Ad-dresses.

The M28W640FCT and M28W640FCB feature aninstant, individual block locking scheme that al-lows any block to be locked or unlocked with no la-tency, enabling instant code and data protection.All blocks have three levels of protection. They canbe locked and locked-down individually preventingany accidental programming or erasure. There isan additional hardware protection against programand erase. When VPP VPPLK all blocks are pro-tected against program or erase. All blocks arelocked at Power Up.

Each block can be erased separately. Erase canbe suspended in order to perform either read or

program in any other block and then resumed.Program can be suspended to read data in anyother block and then resumed. Each block can beprogrammed and erased over 100,000 cycles.

The device includes a 192 bit Protection Registerto increase the protection of a system design. TheProtection Register is divided into a 64 bit segmentand a 128 bit segment. The 64 bit segment con-tains a unique device number written by ST, whilethe second one is one-time-programmable by theuser. The user programmable segment can bepermanently protected. Figure 6., shows the Pro-tection Register Memory Map.

Program and Erase commands are written to theCommand Interface of the memory. An on-chipProgram/Erase Controller takes care of the tim-ings necessary for program and erase operations.The end of a program or erase operation can bedetected and any error conditions identified. Thecommand set required to control the memory isconsistent with JEDEC standards.

The memory is offered in TSOP48 (12 X 20mm)and TFBGA48 (6.39 x 10.5mm, 0.75mm pitch)packages and is supplied with all the bits erased(set to 1).

In addition to the standard version, the packagesare also available in Lead-free version, in compli-ance with JEDEC Std J-STD-020B, the ST ECO-

PACK 7191395 Specification, and the RoHS(Restriction of Hazardous Substances) directive.

All packages are compliant with Lead-free solder-ing processes.

Figure 2. Logic Diagram

Table 1. Signal Names

A0-A21 Address Inputs

DQ0-DQ15 Data Input/Output

E Chip Enable

G Output Enable

W Write Enable

RP Reset

WP Write Protect

VDD Core Power Supply

VDDQPower Supply forInput/Output

VPPOptional Supply Voltage forFast Program & Erase

VSS Ground

NC Not Connected Internally

AI09903

22

A0-A21

W

DQ0-DQ15

VDD

M28W640FCTM28W640FCB

E

VSS

16

G

RP

WP

VDDQ VPP

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Figure 3. TSOP Connections

DQ3

DQ9

DQ2

A6

DQ0

W

A3

DQ6

A8

A9

DQ13

A17

A10 DQ14

A2

DQ12

DQ10

DQ15

VDD

DQ4

DQ5

A7

DQ7

VPPWP

AI09904b

M28W640FCT

M28W640FCB

12

1

13

24 25

36

37

48

DQ8

A20

A19

A1

A18

A4

A5

DQ1

DQ11

G

A12

A13

A16

A11

VDDQA15A14

VSS

E

A0

RP

VSSQ

A21

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Figure 4. TFBGA Connections (Top view through package)

AI04380b

C

B

A

87654321

E

D

F

A4A7VPPA8A11A13

A0EDQ8DQ5DQ14A16

VSSQDQ0DQ9DQ3DQ6DQ15VDDQ

DQ1DQ10VDDDQ7VSS

DQ2

A2A5A17WA10A14

A1A3A6A9A12A15

RP A18

DQ4DQ13 G

DQ12

DQ11

WP A19

A20A21

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Figure 5. Block Addresses

Note: Also see APPENDIX A., Tables 24 and 25 for a full listing of the Block Addresses.

Figure 6. Protection Register Memory Map

AI09905

4 KWords

3FFFFF

3FF000

32 KWords

00FFFF

008000

32 KWords007FFF

000000

M28W640FCTTop Boot Block Addresses

4 KWords

3F8FFF

3F8000

32 KWords

3F0000

3F7FFF

Total of 84 KWord Blocks


4 KWords

3FFFFF

3F8000

32 KWords

32 KWords

000FFF

000000

M28W640FCBBottom Boot Block Addresses

4 KWords

3F7FFF

00FFFF

32 KWords

3F0000

008000



007FFF

007000

AI05520b

User Programmable OTP

Unique device number

Protection Register Lock 1 0

8Ch

85h

84h

81h

80h

PROTECTION REGISTER

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SIGNAL DESCRIPTIONSSee Figure 2., Logic Diagram and Table 1., SignalNames, for a brief overview of the signals connect-ed to this device.

Address Inputs (A0-A21). The Address Inputsselect the cells in the memory array to access dur-ing Bus Read operations. During Bus Write opera-tions they control the commands sent to theCommand Interface of the internal state machine.

Data Input/Output (DQ0-DQ15). The Data I/Ooutputs the data stored at the selected addressduring a Bus Read operation or inputs a commandor the data to be programmed during a Write Busoperation.

Chip Enable (E). The Chip Enable input acti-vates the memory control logic, input buffers, de-coders and sense amplifiers. When Chip Enable is

at VILandReset is at VIH the device is in activemode. When Chip Enable is at VIH the memory isdeselected, the outputs are high impedance andthe power consumption is reduced to the stand-bylevel.

Output Enable (G). The Output Enable controlsdata outputs during the Bus Read operation of thememory.

Write Enable (W). The Write Enable controls theBus Write operation of the memorys CommandInterface. The data and address inputs are latchedon the rising edge of Chip Enable, E, or Write En-able, W, whichever occurs first.

Write Protect (WP). Write Protect is an inputthat gives an additional hardware protection foreach block. When Write Protect is at VIL, the Lock-Down is enabled and the protection status of theblock cannot be changed. When Write Protect is atVIH, the Lock-Down is disabled and the block canbe locked or unlocked. (refer to Table 7., ReadProtection Register and Lock Register).

Reset (RP). The Reset input provides a hard-ware reset of the memory. When Reset is at VIL,the memory is in reset mode: the outputs are highimpedance and the current consumption is mini-mized. After Reset all blocks are in the Locked

state. When Reset is at VIH, the device is in normaloperation. Exiting reset mode the device entersread array mode, but a negative transition of Chip

Enable or a change of the address is required toensure valid data outputs.

VDD Supply Voltage. VDD provides the powersupply to the internal core of the memory device.It is the main power supply for all operations(Read, Program and Erase).

VDDQ Supply Voltage. VDDQ provides the powersupply to the I/O pins and enables all Outputs tobe powered independently from VDD. VDDQ can betied to VDD or can use a separate supply.

VPP Program Supply Voltage. VPP is both acontrol input and a power supply pin. The twofunctions are selected by the voltage range ap-

plied to the pin. The Supply Voltage VDD and theProgram Supply Voltage VPP can be applied inany order.

If VPP is kept in a low voltage range (0V to 3.6V)VPP is seen as a control input. In this case a volt-age lower than VPPLK gives an absolute protectionagainst program or erase, while VPP > VPP1 en-ables these functions (see Table 15., DC Charac-teristics, for the relevant values). VPP is onlysampled at the beginning of a program or erase; achange in its value after the operation has starteddoes not have any effect on Program or Erase,however for Double or Quadruple Word Programthe results are uncertain.

If VPP is in the range 11.4V to 12.6V it acts as apower supply pin. In this condition VPP must bestable until the Program/Erase algorithm is com-pleted (see Table 17. and Table 18.).

VSS Ground. VSS is the reference for all voltagemeasurements.

Note: Each device in a system should haveVDD,VDDQ and VPP decoupled with a 0.1F ca-pacitor close to the pin. See Figure 8., AC Mea-surement Load Circuit. The PCB track widthsshould be sufficient to carry the required VPPprogram and erase currents.

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BUS OPERATIONSThere are six standard bus operations that controlthe device. These are Bus Read, Bus Write, Out-put Disable, Standby, Automatic Standby and Re-

set. See Table 2., Bus Operations, for a summary.Typically glitches of less than 5ns on Chip Enableor Write Enable are ignored by the memory and donot affect bus operations.

Read. Read Bus operations are used to outputthe contents of the Memory Array, the ElectronicSignature, the Status Register and the CommonFlash Interface. Both Chip Enable and Output En-able must be at VIL in order to perform a read op-eration. The Chip Enable input should be used toenable the device. Output Enable should be usedto gate data onto the output. The data read de-pends on the previous command written to the

memory (see Command Interface section). SeeFigure 9., Read AC Waveforms, and Table16., Read AC Characteristics, for details of whenthe output becomes valid.

Read mode is the default state of the device whenexiting Reset or after power-up.

Write. Bus Write operations write Commands tothe memory or latch Input Data to be programmed.A write operation is initiated when Chip Enableand Write Enable are at VIL with Output Enable atVIH. Commands, Input Data and Addresses arelatched on the rising edge of Write Enable or ChipEnable, whichever occurs first.

See Figure 10. and Figure 11., Write AC Wave-forms, and Table 17. and Table 18., Write AC

Characteristics, for details of the timing require-ments.

Output Disable. The data outputs are high im-pedance when the Output Enable is at VIH.

Standby. Standby disables most of the internalcircuitry allowing a substantial reduction of the cur-rent consumption. The memory is in stand-bywhen Chip Enable is at VIH and the device is inread mode. The power consumption is reduced tothe stand-by level and the outputs are set to highimpedance, independently from the Output Enableor Write Enable inputs. If Chip Enable switches toVIH during a program or erase operation, the de-vice enters Standby mode when finished.

Automatic Standby. Automatic Standby pro-vides a low power consumption state during Read

mode. Following a read operation, the device en-ters Automatic Standby after 150ns of bus inactiv-ity even if Chip Enable is Low, V IL, and the supplycurrent is reduced to IDD1. The data Inputs/Out-puts will still output data if a bus Read operation isin progress.

Reset. During Reset mode when Output Enableis Low, VIL, the memory is deselected and the out-puts are high impedance. The memory is in Resetmode when Reset is at VIL. The power consump-tion is reduced to the Standby level, independentlyfrom the Chip Enable, Output Enable or Write En-able inputs. If Reset is pulled to VSS during a Pro-gram or Erase, this operation is aborted and the

memory content is no longer valid.

Table 2. Bus Operations

Note: X = VIL or VIH, VPPH = 12V 5%.

Operation E G W RP WP VPP DQ0-DQ15

Bus Read VIL VIL VIH VIH X Don't Care Data Output

Bus Write VIL VIH VIL VIH X VDD or VPPH Data Input

Output Disable VIL VIH VIH VIH X Don't Care Hi-Z

Standby VIH X X VIH X Don't Care Hi-Z

Reset X X X VIL X Don't Care Hi-Z

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COMMAND INTERFACEAll Bus Write operations to the memory are inter-preted by the Command Interface. Commandsconsist of one or more sequential Bus Write oper-

ations. An internal Program/Erase Controller han-dles all timings and verifies the correct executionof the Program and Erase commands. The Pro-gram/Erase Controller provides a Status Registerwhose output may be read at any time during, tomonitor the progress of the operation, or the Pro-gram/Erase states. See Table 3., CommandCodes, for a summary of the commands and seeAPPENDIX D., Table 32., Write State MachineCurrent/Next, sheet 1 of 2., for a summary of theCommand Interface.

The Command Interface is reset to Read modewhen power is first applied, when exiting from Re-set or whenever VDD is lower than VLKO. Com-mand sequences must be followed exactly. Anyinvalid combination of commands will reset the de-vice to Read mode. Refer to Table 4., Commands,in conjunction with the text descriptions below.

Read Memory Array Command

The Read command returns the memory to itsRead mode. One Bus Write cycle is required to is-sue the Read Memory Array command and returnthe memory to Read mode. Subsequent read op-erations will read the addressed location and out-put the data. When a device Reset occurs, thememory defaults to Read mode.

Read Status Register Command

The Status Register indicates when a program orerase operation is complete and the success orfailure of the operation itself. Issue a Read StatusRegister command to read the Status Registerscontents. Subsequent Bus Read operations readthe Status Register at any address, until anothercommand is issued. See Table 11., Status Regis-ter Bits, for details on the definitions of the bits.

The Read Status Register command may be is-sued at any time, even during a Program/Eraseoperation. Any Read attempt during a Program/Erase operation will automatically output the con-tent of the Status Register.

Read Electronic Signature CommandThe Read Electronic Signature command readsthe Manufacturer and Device Codes and the BlockLocking Status, or the Protection Register.

The Read Electronic Signature command consistsof one write cycle, a subsequent read will outputthe Manufacturer Code, the Device Code, theBlock Lock and Lock-Down Status, or the Protec-tion and Lock Register. See Tables 5, 6 and 7 forthe valid address.

Table 3. Command Codes

Read CFI Query Command

The Read Query Command is used to read datafrom the Common Flash Interface (CFI) MemoryArea, allowing programming equipment or appli-cations to automatically match their interface tothe characteristics of the device. One Bus Writecycle is required to issue the Read Query Com-mand. Once the command is issued subsequentBus Read operations read from the CommonFlash Interface Memory Area. See APPENDIXB., COMMON FLASH INTERFACE (CFI), Tables26, 27, 28, 29, 30 and 31 for details on the infor-mation contained in the Common Flash Interfacememory area.

Block Erase CommandThe Block Erase command can be used to erasea block. It sets all the bits within the selected blockto 1. All previous data in the block is lost. If theblock is protected then the Erase operation willabort, the data in the block will not be changed andthe Status Register will output the error.

Two Bus Write cycles are required to issue thecommand.

The first bus cycle sets up the Erasecommand.

Hex Code Command

01h Block Lock confirm

10h Program

20h Erase

2Fh Block Lock-Down confirm

30h Double Word Program

40h Program

50h Clear Status Register

56h Quadruple Word Program

60hBlock Lock, Block Unlock, Block Lock-

Down

70h Read Status Register

90h Read Electronic Signature

98h Read CFI Query

B0h Program/Erase Suspend

C0h Protection Register Program

D0hProgram/Erase Resume, Block Unlockconfirm

FFh Read Memory Array

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The second latches the block address in theinternal state machine and starts the Program/Erase Controller.

If the second bus cycle is not Write Erase Confirm

(D0h), Status Register bits b4 and b5 are set andthe command aborts.

Erase aborts if Reset turns to VIL. As data integritycannot be guaranteed when the Erase operation isaborted, the block must be erased again.

During Erase operations the memory will acceptthe Read Status Register command and the Pro-gram/Erase Suspend command, all other com-mands will be ignored. Typical Erase times aregiven in Table 8., Program, Erase Times and Pro-gram/Erase Endurance Cycles.

See APPENDIX C., Figure 21., Erase Flowchartand Pseudo Code, for a suggested flowchart for

using the Erase command.Program Command

The memory array can be programmed word-by-word. Two bus write cycles are required to issuethe Program Command.

The first bus cycle sets up the Programcommand.

The second latches the Address and the Datato be written and starts the Program/EraseController.

During Program operations the memory will ac-cept the Read Status Register command and theProgram/Erase Suspend command. Typical Pro-

gram times are given in Table 8., Program, EraseTimes and Program/Erase Endurance Cycles.

Programming aborts if Reset goes to VIL. As dataintegrity cannot be guaranteed when the programoperation is aborted, the block containing thememory location must be erased and repro-grammed.

See APPENDIX C., Figure 17., Program Flow-chart and Pseudo Code, for the flowchart for usingthe Program command.

Double Word Program Command

This feature is offered to improve the programmingthroughput, writing a page of two adjacent words

in parallel.The two words must differ only for theaddress A0. Programming should not be attempt-ed when VPP is not at VPPH.

Three bus write cycles are necessary to issue theDouble Word Program command.

The first bus cycle sets up the Double WordProgram Command.

The second bus cycle latches the Address andthe Data of the first word to be written.

The third bus cycle latches the Address andthe Data of the second word to be written andstarts the Program/Erase Controller.

Read operations output the Status Register con-tent after the programming has started. Program-ming aborts if Reset goes to VIL. As data integritycannot be guaranteed when the program opera-

tion is aborted, the block containing the memorylocation must be erased and reprogrammed.

See APPENDIX C., Figure 18., Double Word Pro-gram Flowchart and Pseudo Code for the flow-chart for using the Double Word Programcommand.

Quadruple Word Program Command

This feature is offered to improve the programmingthroughput, writing a page of four adjacent wordsin parallel.The four words must differ only for theaddresses A0 and A1. Programming should not beattempted when VPP is not at VPPH.

Five bus write cycles are necessary to issue the

Quadruple Word Program command. The first bus cycle sets up the Quadruple

Word Program Command.

The second bus cycle latches the Address andthe Data of the first word to be written.

The third bus cycle latches the Address andthe Data of the second word to be written.

The fourth bus cycle latches the Address andthe Data of the third word to be written.

The fifth bus cycle latches the Address and theData of the fourth word to be written and startsthe Program/Erase Controller.

Read operations output the Status Register con-tent after the programming has started. Program-ming aborts if Reset goes to VIL. As data integritycannot be guaranteed when the program opera-tion is aborted, the block containing the memorylocation must be erased and reprogrammed.

See APPENDIX C., Figure 19., Quadruple WordProgram Flowchart and Pseudo Code, for theflowchart for using the Quadruple Word Programcommand.

Clear Status Register Command

The Clear Status Register command can be usedto reset bits 1, 3, 4 and 5 in the Status Register to0. One bus write cycle is required to issue the

Clear Status Register command.The bits in the Status Register do not automatical-ly return to 0 when a new Program or Erase com-mand is issued. The error bits in the StatusRegister should be cleared before attempting anew Program or Erase command.

Program/Erase Suspend Command

The Program/Erase Suspend command is used topause a Program or Erase operation. One buswrite cycle is required to issue the Program/Erasecommand and pause the Program/Erase control-ler.

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During Program/Erase Suspend the Command In-terface will accept the Program/Erase Resume,Read Array, Read Status Register, Read Electron-ic Signature and Read CFI Query commands. Ad-

ditionally, if the suspend operation was Erase thenthe Program, Double Word Program, QuadrupleWord Program, Block Lock, Block Lock-Down orProtection Program commands will also be ac-cepted. The block being erased may be protectedby issuing the Block Protect, Block Lock or Protec-tion Program commands. When the Program/Erase Resume command is issued the operationwill complete. Only the blocks not being erasedmay be read or programmed correctly.

During a Program/Erase Suspend, the device canbe placed in a pseudo-standby mode by takingChip Enable to VIH. Program/Erase is aborted ifReset turns to VIL.

See APPENDIX C., Figure 20., Program Suspend& Resume Flowchart and Pseudo Code, and Fig-ure 22., Erase Suspend & Resume Flowchart andPseudo Code, for flowcharts for using the Pro-gram/Erase Suspend command.

Program/Erase Resume Command

The Program/Erase Resume command can beused to restart the Program/Erase Controller aftera Program/Erase Suspend operation has pausedit. One Bus Write cycle is required to issue thecommand. Once the command is issued subse-quent Bus Read operations read the Status Reg-ister.

See APPENDIX C., Figure 20., Program Suspend& Resume Flowchart and Pseudo Code, and Fig-ure 22., Erase Suspend & Resume Flowchart andPseudo Code, for flowcharts for using the Pro-gram/Erase Resume command.

Protection Register Program Command

The Protection Register Program command isused to Program the 128 bit user One-Time-Pro-grammable (OTP) segment of the Protection Reg-ister. The segment is programmed 16 bits at atime. When shipped all bits in the segment are setto 1. The user can only program the bits to 0.

Two write cycles are required to issue the Protec-

tion Register Program command. The first bus cycle sets up the Protection

Register Program command.

The second latches the Address and the Datato be written to the Protection Register andstarts the Program/Erase Controller.

Read operations output the Status Register con-tent after the programming has started.

The segment can be protected by programming bit1 of the Protection Lock Register (see Figure6., Protection Register Memory Map). Attemptingto program a previously protected Protection Reg-

ister will result in a Status Register error. The pro-tection of the Protection Register is not reversible.

The Protection Register Program cannot be sus-pended.

Block Lock CommandThe Block Lock command is used to lock a blockand prevent Program or Erase operations fromchanging the data in it. All blocks are locked atpower-up or reset.

Two Bus Write cycles are required to issue theBlock Lock command.

The first bus cycle sets up the Block Lockcommand.

The second Bus Write cycle latches the blockaddress.

The lock status can be monitored for each block

using the Read Electronic Signature command.Table 10. shows the protection status after issuinga Block Lock command.

The Block Lock bits are volatile, once set they re-main set until a hardware reset or power-down/power-up. They are cleared by a Blocks Unlockcommand. Refer to the section, Block Locking, fora detailed explanation.

Block Unlock Command

The Block Unlock command is used to unlock ablock, allowing the block to be programmed orerased. Two Bus Write cycles are required to is-sue the Block Unlock command.

The first bus cycle sets up the Block Unlockcommand.


The lock status can be monitored for each blockusing the Read Electronic Signature command.Table 10. shows the protection status after issuinga Block Unlock command. Refer to the section,Block Locking, for a detailed explanation.

Block Lock-Down Command

A locked block cannot be Programmed or Erased,or have its protection status changed when WP islow, VIL. When WP is high, VIH, the Lock-Down

function is disabled and the locked blocks can beindividually unlocked by the Block Unlock com-mand.

Two Bus Write cycles are required to issue theBlock Lock-Down command.

The first bus cycle sets up the Block Lockcommand.


The lock status can be monitored for each blockusing the Read Electronic Signature command.Locked-Down blocks revert to the locked (and not

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locked-down) state when the device is reset onpower-down. Table 10. shows the protection sta-tus after issuing a Block Lock-Down command.

Refer to the section, Block Locking, for a detailedexplanation.

Table 4. Commands

Note: 1. X = Don't Care, RA=Read Address, RD=Read Data, SRD=Status Register Data, ID=Identifier (Manufacture and Device Code),QA=Query Address, QD=Query Data, BA=Block Address, PA=Program Address, PD=Program Data, PRA=Protection Register Ad-dress, PRD=Protection Register Data.

2. The signature addresses are listed in Tables 5,6 and 7.

3. Program Addresses 1 and 2 must be consecutive Addresses differing only for A0.4. Program Addresses 1,2,3 and 4 must be consecutive Addresses differing only for A0 and A1.

Table 5. Read Electronic Signature

Note: RP = VIH.

Commands

Cycles

Bus Write Operations

1st Cycle 2nd Cycle 3rd Cycle 4th Cycle 5th Cycle

Op. Add Data Op. Add Data Op. Add Data Op. Add Data Op. Add Data

Read MemoryArray

1+ Write X FFh Read RA RD

Read StatusRegister

1+ Write X 70h Read X SRD

Read ElectronicSignature

1+ Write X 90h Read SA(2) IDh

Read CFI Query 1+ Write X 98h Read QA QD

Erase 2 Write X 20h Write BA D0h

Program 2 Write X40h or

10hWrite PA PD

Double Word

Program(3)3 Write X 30h Write PA1 PD1 Write PA2 PD2

Quadruple Word

Program(4)5 Write X 56h Write PA1 PD1 Write PA2 PD2 Write PA3 PD3 Write PA4 PD4

Clear StatusRegister

1 Write X 50h

Program/EraseSuspend

1 Write X B0h

Program/EraseResume

1 Write X D0h

Block Lock 2 Write X 60h Write BA 01h

Block Unlock 2 Write X 60h Write BA D0h

Block Lock-Down 2 Write X 60h Write BA 2Fh

ProtectionRegister Program

2 Write X C0h Write PRA PRD

Code Device E G W A0 A1 A2-A7 A8-A21 DQ0-DQ7 DQ8-DQ15

ManufactureCode

VIL VIL VIH VIL VIL 0 Don't Care 20h 00h

Device CodeM28W640FCT VIL VIL VIH VIH VIL 0 Don't Care 48h 88h

M28W640FCB VIL VIL VIH VIH VIL 0 Don't Care 49h 88h

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Table 6. Read Block Lock Signature

Note: 1. A Locked-Down Block can be locked "DQ0 = 1" or unlocked "DQ0 = 0"; see Block Locking section.

Table 7. Read Protection Register and Lock Register

Block Status E G W A0 A1 A2-A7 A8-A11 A12-A21 DQ0 DQ1 DQ2-DQ15

Locked Block VIL VIL VIH VIL VIH 0 Don't Care Block Address 1 0 00h

Unlocked Block VIL VIL VIH VIL VIH 0 Don't Care Block Address 0 0 00h

Locked-DownBlock

VIL VIL VIH VIL VIH 0 Don't Care Block Address X (1) 1 00h

Word E G W A0-A7 A8-A21 DQ0 DQ1 DQ2 DQ3-DQ7 DQ8-DQ15

Lock VIL VIL VIH 80h Don't Care 0OTP Prot.

data0 00h 00h

Unique ID 0 VIL VIL VIH 81h Don't Care ID data ID data ID data ID data ID data




OTP 0 VIL VIL VIH 85h Don't Care OTP data OTP data OTP data OTP data OTP data





OTP 5 VIL VIL VIH 8Ah Don't Care OTP data OTP data OTP data OTP data OTP data

OTP 6 VIL VIL VIH 8Bh Don't Care OTP data OTP data OTP data OTP data OTP data

OTP 7 VIL VIL VIH 8Ch Don't Care OTP data OTP data OTP data OTP data OTP data

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Table 8. Program, Erase Times and Program/Erase Endurance Cycles

Note: 1. Typical time to program a Main or Parameter Block using the Double Word Program and the Quadruple Word Program commandsrespectively.

Parameter Test ConditionsM28W640FCT, M28W640FCB

UnitMin Typ Max

Word Program VPP = VDD 10 200 s

Double Word Program VPP = 12V 5% 10 200 s

Quadruple Word Program VPP = 12V 5% 10 200 s

Main Block ProgramVPP = 12V 5% 0.16/0.08 (1) 5 s

VPP = VDD 0.32 5 s

Parameter Block ProgramVPP = 12V 5% 0.02/0.01 (1) 4 s

VPP = VDD 0.04 4 s

Main Block EraseVPP = 12V 5% 1 10 s

VPP = VDD 1 10 s

Parameter Block EraseVPP = 12V 5% 0.4 10 s

VPP = VDD 0.4 10 s

Program/Erase Cycles (per Block) 100,000 cycles

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BLOCK LOCKINGThe M28W640FCT and M28W640FCB feature aninstant, individual block locking scheme that al-lows any block to be locked or unlocked with no la-

tency. This locking scheme has three levels ofprotection.

Lock/Unlock - this first level allows software-only control of block locking.

Lock-Down - this second level requireshardware interaction before locking can bechanged.

VPP VPPLK - the third level offers a completehardware protection against program anderase on all blocks.

The protection status of each block can be set toLocked, Unlocked, and Lock-Down. Table 10., de-fines all of the possible protection states (WP,

DQ1, DQ0), and APPENDIX C., Figure 23., showsa flowchart for the locking operations.

Reading a Blocks Lock Status

The lock status of every block can be read in theRead Electronic Signature mode of the device. Toenter this mode write 90h to the device. Subse-quent reads at the address specified in Table 6.,will output the protection status of that block. Thelock status is represented by DQ0 and DQ1. DQ0indicates the Block Lock/Unlock status and is setby the Lock command and cleared by the Unlockcommand. It is also automatically set when enter-ing Lock-Down. DQ1 indicates the Lock-Down sta-

tus and is set by the Lock-Down command. Itcannot be cleared by software, only by a hardwarereset or power-down.

The following sections explain the operation of thelocking system.

Locked State

The default status of all blocks on power-up or af-ter a hardware reset is Locked (states (0,0,1) or(1,0,1)). Locked blocks are fully protected fromany program or erase. Any program or erase oper-ations attempted on a locked block will return anerror in the Status Register. The Status of aLocked block can be changed to Unlocked or

Lock-Down using the appropriate software com-mands. An Unlocked block can be Locked by issu-ing the Lock command.

Unlocked State

Unlocked blocks (states (0,0,0), (1,0,0) (1,1,0)),can be programmed or erased. All unlockedblocks return to the Locked state after a hardwarereset or when the device is powered-down. Thestatus of an unlocked block can be changed toLocked or Locked-Down using the appropriate

software commands. A locked block can be un-locked by issuing the Unlock command.

Lock-Down State

Blocks that are Locked-Down (state (0,1,x))areprotected from program and erase operations (asfor Locked blocks) but their protection status can-not be changed using software commands alone.A Locked or Unlocked block can be Locked-Downby issuing the Lock-Down command. Locked-Down blocks revert to the Locked state when thedevice is reset or powered-down.

The Lock-Down function is dependent on the WPinput pin. When WP=0 (VIL), the blocks in theLock-Down state (0,1,x) are protected from pro-gram, erase and protection status changes. WhenWP=1 (VIH) the Lock-Down function is disabled

(1,1,1) and Locked-Down blocks can be individu-ally unlocked to the (1,1,0) state by issuing thesoftware command, where they can be erased andprogrammed. These blocks can then be relocked(1,1,1) and unlocked (1,1,0) as desired while WPremains high. When WP is low , blocks that werepreviously Locked-Down return to the Lock-Downstate (0,1,x) regardless of any changes madewhile WP was high. Device reset or power-downresets all blocks , including those in Lock-Down, tothe Locked state.

Locking Operations During Erase Suspend

Changes to block lock status can be performedduring an erase suspend by using the standardlocking command sequences to unlock, lock orlock-down a block. This is useful in the case whenanother block needs to be updated while an eraseoperation is in progress.

To change block locking during an erase opera-tion, first write the Erase Suspend command, thencheck the status register until it indicates that theerase operation has been suspended. Next writethe desired Lock command sequence to a blockand the lock status will be changed. After complet-ing any desired lock, read, or program operations,resume the erase operation with the Erase Re-sume command.

If a block is locked or locked-down during an erasesuspend of the same block, the locking status bitswill be changed immediately, but when the eraseis resumed, the erase operation will complete.

Locking operations cannot be performed during aprogram suspend. Refer to APPENDIX D., Com-mand Interface and Program/Erase ControllerState, for detailed information on which com-mands are valid during erase suspend.

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Table 9. Block Lock Status

Table 10. Protection Status

Note: 1. The lock status is defined by the write protect pin and by DQ1 (1 for a locked-down block) and DQ0 (1 for a locked block) as readin the Read Electronic Signature command with A1 = VIH and A0 = VIL.

2. All blocks are locked at power-up, so the default configuration is 001 or 101 according to WP status.3. A WP transition to VIH on a locked block will restore the previous DQ0 value, giving a 111 or 110.

Item Address Data

Block Lock Configuration

xx002

LOCK

Block is Unlocked DQ0=0

Block is Locked DQ0=1

Block is Locked-Down DQ1=1

Current Protection Status(1)

(WP, DQ1, DQ0)Next Protection Status(1)

(WP, DQ1, DQ0)

Current StateProgram/Erase

AllowedAfter Block

Lock Command

After BlockUnlock

Command

After Block Lock-Down Command

After WPtransition

1,0,0 yes 1,0,1 1,0,0 1,1,1 0,0,0

1,0,1(2) no 1,0,1 1,0,0 1,1,1 0,0,1

1,1,0 yes 1,1,1 1,1,0 1,1,1 0,1,1

1,1,1 no 1,1,1 1,1,0 1,1,1 0,1,1

0,0,0 yes 0,0,1 0,0,0 0,1,1 1,0,0

0,0,1(2) no 0,0,1 0,0,0 0,1,1 1,0,1

0,1,1 no 0,1,1 0,1,1 0,1,1 1,1,1 or 1,1,0 (3)

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STATUS REGISTERThe Status Register provides information on thecurrent or previous Program or Erase operation.The various bits convey information and errors on

the operation. To read the Status register theRead Status Register command can be issued, re-fer to Read Status Register Command section. Tooutput the contents, the Status Register is latchedon the falling edge of the Chip Enable or OutputEnable signals, and can be read until Chip Enableor Output Enable returns to VIH. Either Chip En-able or Output Enable must be toggled to updatethe latched data.

Bus Read operations from any address alwaysread the Status Register during Program andErase operations.

The bits in the Status Register are summarized in

Table 11., Status Register Bits. Refer to Table 11.in conjunction with the following text descriptions.

Program/Erase Controller Status (Bit 7). TheProgram/Erase Controller Status bit indicateswhether the Program/Erase Controller is active orinactive. When the Program/Erase Controller Sta-tus bit is Low (set to 0), the Program/Erase Con-troller is active; when the bit is High (set to 1), theProgram/Erase Controller is inactive, and the de-vice is ready to process a new command.

The Program/Erase Controller Status is Low im-mediately after a Program/Erase Suspend com-mand is issued until the Program/Erase Controllerpauses. After the Program/Erase Controller paus-

es the bit is High .During Program, Erase, operations the Program/Erase Controller Status bit can be polled to find theend of the operation. Other bits in the Status Reg-ister should not be tested until the Program/EraseController completes the operation and the bit isHigh.

After the Program/Erase Controller completes itsoperation the Erase Status, Program Status, VPPStatus and Block Lock Status bits should be testedfor errors.

Erase Suspend Status (Bit 6). The Erase Sus-pend Status bit indicates that an Erase operation

has been suspended or is going to be suspended.When the Erase Suspend Status bit is High (set to1), a Program/Erase Suspend command hasbeen issued and the memory is waiting for a Pro-gram/Erase Resume command.

The Erase Suspend Status should only be consid-ered valid when the Program/Erase Controller Sta-tus bit is High (Program/Erase Controller inactive).Bit 7 is set within 30s of the Program/Erase Sus-pend command being issued therefore the memo-ry may still complete the operation rather thanentering the Suspend mode.

When a Program/Erase Resume command is is-sued the Erase Suspend Status bit returns Low.

Erase Status (Bit 5). The Erase Status bit can beused to identify if the memory has failed to verifythat the block has erased correctly. When theErase Status bit is High (set to 1), the Program/Erase Controller has applied the maximum num-ber of pulses to the block and still failed to verifythat the block has erased correctly. The Erase Sta-tus bit should be read once the Program/EraseController Status bit is High (Program/Erase Con-troller inactive).

Once set High, the Erase Status bit can only be re-set Low by a Clear Status Register command or ahardware reset. If set High it should be reset be-fore a new Program or Erase command is issued,

otherwise the new command will appear to fail.Program Status (Bit 4). The Program Status bitis used to identify a Program failure. When theProgram Status bit is High (set to 1), the Pro-gram/Erase Controller has applied the maximumnumber of pulses to the byte and still failed to ver-ify that it has programmed correctly. The ProgramStatus bit should be read once the Program/EraseController Status bit is High (Program/Erase Con-troller inactive).

Once set High, the Program Status bit can only bereset Low by a Clear Status Register command ora hardware reset. If set High it should be reset be-fore a new command is issued, otherwise the new

command will appear to fail.VPP Status (Bit 3). The VPP Status bit can beused to identify an invalid voltage on the VPP pinduring Program and Erase operations. The VPPpin is only sampled at the beginning of a Programor Erase operation. Indeterminate results can oc-cur if VPP becomes invalid during an operation.

When the VPP Status bit is Low (set to 0), the volt-age on the VPP pin was sampled at a valid voltage;when the VPP Status bit is High (set to 1), the VPPpin has a voltage that is below the VPP LockoutVoltage, VPPLK, the memory is protected and Pro-gram and Erase operations cannot be performed.

Once set High, the VPP Status bit can only be resetLow by a Clear Status Register command or ahardware reset. If set High it should be reset be-fore a new Program or Erase command is issued,otherwise the new command will appear to fail.

Program Suspend Status (Bit 2). The ProgramSuspend Status bit indicates that a Program oper-ation has been suspended. When the ProgramSuspend Status bit is High (set to 1), a Program/Erase Suspend command has been issued andthe memory is waiting for a Program/Erase Re-sume command. The Program Suspend Statusshould only be considered valid when the Pro-

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gram/Erase Controller Status bit is High (Program/Erase Controller inactive). Bit 2 is set within 5s ofthe Program/Erase Suspend command being is-sued therefore the memory may still complete the

operation rather than entering the Suspend mode.When a Program/Erase Resume command is is-sued the Program Suspend Status bit returns Low.

Block Protection Status (Bit 1). The Block Pro-tection Status bit can be used to identify if a Pro-gram or Erase operation has tried to modify thecontents of a locked block.

When the Block Protection Status bit is High (setto 1), a Program or Erase operation has been at-tempted on a locked block.

Once set High, the Block Protection Status bit can

only be reset Low by a Clear Status Register com-mand or a hardware reset. If set High it should bereset before a new command is issued, otherwisethe new command will appear to fail.

Reserved (Bit 0). Bit 0 of the Status Register isreserved. Its value must be masked.

Note: Refer to APPENDIX C., FLOWCHARTSAND PSEUDO CODES, for using the StatusRegister.

Table 11. Status Register Bits

Note: Logic level '1' is High, '0' is Low.

Bit Name Logic Level Definition

7 P/E.C. Status '1' Ready

'0' Busy

6 Erase Suspend Status'1' Suspended

'0' In progress or Completed

5 Erase Status'1' Erase Error

'0' Erase Success

4 Program Status'1' Program Error

'0' Program Success

3 VPP

Status'1' VPP Invalid, Abort

'0' VPP OK

2 Program Suspend Status'1' Suspended

'0' In Progress or Completed

1 Block Protection Status'1' Program/Erase on protected Block, Abort

'0' No operation to protected blocks

0 Reserved

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MAXIMUM RATINGStressing the device above the rating listed in theAbsolute Maximum Ratings table may cause per-manent damage to the device. These are stress

ratings only and operation of the device at these orany other conditions above those indicated in theOperating sections of this specification is not im-

plied. Exposure to Absolute Maximum Rating con-ditions for extended periods may affect devicereliability. Refer also to the STMicroelectronics

SURE Program and other relevant quality docu-ments.

Table 12. Absolute Maximum Ratings

Note: 1. Depends on range.2. Compliant with the JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assermbly), the ST ECOPACK7191395 specification,

and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU.

Symbol ParameterValue

UnitMin Max

TA Ambient Operating Temperature (1) 40 85 C

TBIAS Temperature Under Bias 40 125 C

TSTG Storage Temperature 55 155 C

TLEAD Lead Temperature during Soldering (2) C

VIO Input or Output Voltage 0.6 VDDQ+0.6 V

VDD, VDDQ Supply Voltage 0.6 4.1 V

VPP Program Voltage 0.6 13 V

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DC AND AC PARAMETERSThis section summarizes the operating and mea-surement conditions, and the DC and AC charac-teristics of the device. The parameters in the DC

and AC characteristics Tables that follow, are de-rived from tests performed under the Measure-

ment Conditions summarized in Table13., Operating and AC Measurement Conditions.Designers should check that the operating condi-

tions in their circuit match the measurement condi-tions when relying on the quoted parameters.

Table 13. Operating and AC Measurement Conditions

Figure 7. AC Measurement I/O Waveform Figure 8. AC Measurement Load Circuit

Table 14. Capacitance

Note: Sampled only, not 100% tested.

Parameter


70 85 90 10Units

Min Max Min Max Min Max Min Max

VDD Supply Voltage 2.7 3.6 2.7 3.6 2.7 3.6 2.7 3.6 V

VDDQ Supply Voltage (VDDQ VDD)

2.7 3.6 2.7 3.6 2.7 3.6 1.65 3.6 V

Ambient Operating Temperature 40 85 40 85 40 85 40 85 C

Load Capacitance (CL) 50 50 50 50 pF

Input Rise and Fall Times 5 5 5 5 ns

Input Pulse Voltages 0 to VDDQ 0 to VDDQ 0 to VDDQ 0 to VDDQ V

Input and Output Timing Ref.Voltages

VDDQ/2 VDDQ/2 VDDQ/2 VDDQ/2 V

AI00610

VDDQ

0V

VDDQ/2

AI00609C

VDDQ

CL

CL includes JIG capacitance

25k

DEVICEUNDERTEST

0.1F

VDD

0.1F

VDDQ

25k

Symbol Parameter Test Condition Min Max Unit

CIN Input Capacitance VIN = 0V 6 pF

COUT Output Capacitance VOUT = 0V 12 pF

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Table 15. DC Characteristics

Symbol Parameter Test Condition Min Typ Max Unit

ILI Input Leakage Current 0V VIN VDDQ 1 A

ILO Output Leakage Current 0V

VOUTVDDQ 10 A

IDD Supply Current (Read) E = VSS, G = VIH, f = 5MHz 9 18 mA

IDD1Supply Current (Stand-by orAutomatic Stand-by)

E = VDDQ 0.2V,

RP = VDDQ 0.2V15 50 A

IDD2Supply Current(Reset)

RP = VSS 0.2V 15 50 A

IDD3 Supply Current (Program)

Program in progressVPP = 12V 5%

5 10 mA

Program in progressVPP = VDD

10 20 mA

IDD4 Supply Current (Erase)

Erase in progressVPP = 12V 5%

5 20 mA

Erase in progressVPP = VDD

10 20 mA

IDD5Supply Current(Program/Erase Suspend)

E = VDDQ 0.2V,

Erase suspended15 50 A

IPPProgram Current(Read or Stand-by)

VPP > VDD 400 A

IPP1Program Current(Read or Stand-by)

VPP VDD 1 5 A

IPP2 Program Current (Reset) RP = VSS 0.2V 1 5 A

IPP3 Program Current (Program)

Program in progressVPP = 12V 5%

1 10 mA

Program in progress

VPP = VDD

1 5 A

IPP4 Program Current (Erase)

Erase in progressVPP = 12V 5%

3 10 mA

Erase in progressVPP = VDD

1 5 A

VIL Input Low Voltage0.5 0.4 V

VDDQ 2.7V 0.5 0.8 V

VIH Input High VoltageVDDQ0.4 VDDQ +0.4 V

VDDQ 2.7V 0.7 VDDQ VDDQ +0.4 V

VOL Output Low VoltageIOL = 100A, VDD = VDD min,

VDDQ = VDDQ min0.1 V

VOH Output High VoltageIOH = 100A, VDD = VDD min,

VDDQ = VDDQ min VDDQ 0.1 V

VPP1Program Voltage (Program orErase operations)

1.65 3.6 V

VPPH

Program Voltage(Program or Eraseoperations)

11.4 12.6 V

VPPLKProgram Voltage(Program and Erase lock-out)

1 V

VLKOVDD Supply Voltage (Program

and Erase lock-out)2 V

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Figure 9. Read AC Waveforms

Table 16. Read AC Characteristics

Note: 1. Sampled only, not 100% tested.2. G may be delayed by up to tELQV - tGLQV after the falling edge of E without increasing tELQV.

Symbol Alt ParameterM28W640FCT, M28W640FCB

Unit70 85 90 10

tAVAV tRC Address Valid to Next Address Valid Min 70 85 90 100 ns

tAVQV tACC Address Valid to Output Valid Max 70 85 90 100 ns

tAXQX(1) tOH Address Transition to Output Transition Min 0 0 0 0 ns

tEHQX(1) tOH Chip Enable High to Output Transition Min 0 0 0 0 ns

tEHQZ(1) tHZ Chip Enable High to Output Hi-Z Max 20 20 25 25 ns

tELQV(2) tCE Chip Enable Low to Output Valid Max 70 85 90 100 ns

tELQX(1) tLZ Chip Enable Low to Output Transition Min 0 0 0 0 ns

tGHQX(1) tOH Output Enable High to Output Transition Min 0 0 0 0 ns

tGHQZ(1) tDF Output Enable High to Output Hi-Z Max 20 20 25 25 ns

tGLQV(2) tOE Output Enable Low to Output Valid Max 20 20 30 30 ns

tGLQX(1) tOLZ Output Enable Low to Output Transition Min 0 0 0 0 ns

DQ0-DQ15

AI04387

VALIDA0-A21

E

tAXQX

tAVAV

VALID

tAVQV

tELQV

tELQX

tGLQV

tGLQX

ADDR. VALIDCHIP ENABLE

OUTPUTSENABLED

DATA VALID STANDBY

G

tGHQX

tGHQZ

tEHQX

tEHQZ

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Figure 10. Write AC Waveforms, Write Enable Controlled

E G W DQ0-DQ15

COMMAND

CMDorDATA

STATUSREGISTER

VPP

VALID

A0-A21

tAVAV

tQVVPL

tAVWH

tWHAX

PROGRAMOR

ERASE

tELWL

tWHEH

tWHDX

tDVWH

tWLWH

tWHWL

tVPHWH

SET-UP

COMMAND

CONFIRMCOMMAND

ORDATAINPUT

STATUSREGISTER

READ

1stPOLLING

tELQV

AI04388

tWPHWH

WP

tWHGL

tQVWPL

tWHEL

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Table 17. Write AC Characteristics, Write Enable Controlled

Note: 1. Sampled only, not 100% tested.

2. Applicable if VPP is seen as a logic input (VPP < 3.6V).


Unit70 85 90 10

tAVAV tWC Write Cycle Time Min 70 85 90 100 ns

tAVWH tAS Address Valid to Write Enable High Min 45 45 50 50 ns

tDVWH tDS Data Valid to Write Enable High Min 45 45 50 50 ns

tELWL tCS Chip Enable Low to Write Enable Low Min 0 0 0 0 ns

tELQV Chip Enable Low to Output Valid Min 70 85 90 100 ns

tQVVPL(1,2) Output Valid to VPP Low Min 0 0 0 0 ns

tQVWPL Output Valid to Write Protect Low Min 0 0 0 0 ns

tVPHWH(1) tVPS VPP High to Write Enable High Min 200 200 200 200 ns

tWHAX tAH Write Enable High to Address Transition Min 0 0 0 0 ns

tWHDX tDH Write Enable High to Data Transition Min 0 0 0 0 ns

tWHEH tCH Write Enable High to Chip Enable High Min 0 0 0 0 ns

tWHEL Write Enable High to Chip Enable Low Min 25 25 30 30 ns

tWHGL Write Enable High to Output Enable Low Min 20 20 30 30 ns

tWHWL tWPH Write Enable High to Write Enable Low Min 25 25 30 30 ns

tWLWH tWP Write Enable Low to Write Enable High Min 45 45 50 50 ns

tWPHWH Write Protect High to Write Enable High Min 45 45 50 50 ns

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Figure 11. Write AC Waveforms, Chip Enable Controlled

EG DQ0-DQ15

COMMAND

CMDorDATA

STATUSREGISTER

VPP

VALID

A0-A21

tAVAV

tQVVPL

tAVEH

tEHAX

PROGRAMOR

ERASE

tWL

EL

tEHWH

tEHDX

tDVEH

tELEH

tEHEL

tVPHEH

POWER-UPAND

SET-UPCOMMAND

CONFIRMCOMMAND

ORDATAINPUT

STATUSREGISTER

READ

1stPOLLING

tELQV

AI04389

W

tWPHEH

WP

tEHGL

tQVWPL

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Table 18. Write AC Characteristics, Chip Enable Controlled

Note: 1. Sampled only, not 100% tested.

2. Applicable if VPP is seen as a logic input (VPP < 3.6V).


Unit70 85 90 10

tAVAV tWC Write Cycle Time Min 70 85 90 100 ns

tAVEH tAS Address Valid to Chip Enable High Min 45 45 50 50 ns

tDVEH tDS Data Valid to Chip Enable High Min 45 45 50 50 ns

tEHAX tAHChip Enable High to AddressTransition

Min 0 0 0 0 ns

tEHDX tDH Chip Enable High to Data Transition Min 0 0 0 0 ns

tEHEL tCPH Chip Enable High to Chip Enable Low Min 25 25 30 30 ns

tEHGLChip Enable High to Output EnableLow

Min 25 25 30 30 ns

tEHWH tWH Chip Enable High to Write Enable High Min 0 0 0 0 nstELEH tCP Chip Enable Low to Chip Enable High Min 45 45 50 50 ns

tELQV Chip Enable Low to Output Valid Min 70 85 90 100 ns

tQVVPL(1,2) Output Valid to VPP Low Min 0 0 0 0 ns

tQVWPL Data Valid to Write Protect Low Min 0 0 0 0 ns

tVPHEH(1) tVPS VPP High to Chip Enable High Min 200 200 200 200 ns

tWLEL tCS Write Enable Low to Chip Enable Low Min 0 0 0 0 ns

tWPHEH Write Protect High to Chip Enable High Min 45 45 50 50 ns

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Figure 12. Power-Up and Reset AC Waveforms

Table 19. Power-Up and Reset AC Characteristics

Note: 1. The device Reset is possible but not guaranteed if tPLPH < 100ns.2. Sampled only, not 100% tested.3. It is important to assert RP in order to allow proper CPU initialization during power up or reset.

Symbol Parameter Test ConditionM28W640FCT, M28W640FCB

Unit70 85 90 10

tPHWLtPHELtPHGL

Reset High to Write Enable Low, ChipEnable Low, Output Enable Low

During Programand Erase

Min 50 50 50 50 s

others Min 30 30 30 30 ns

tPLPH(1,2) Reset Low to Reset High Min 100 100 100 100 ns

tVDHPH(3) Supply Voltages High to Reset High Min 50 50 50 50 s

AI03537b

W,

RP

tPHWLtPHEL

tPHGL

E, G

VDD, VDDQ

tVDHPH

tPHWLtPHELtPHGL

tPLPH

Power-Up Reset

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PACKAGE MECHANICAL

Figure 13. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline

Note: Drawing is not to scale.

Table 20. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data

Symbolmillimeters inches

Typ Min Max Typ Min Max

A 1.200 0.0472

A1 0.100 0.050 0.150 0.0039 0.0020 0.0059

A2 1.000 0.950 1.050 0.0394 0.0374 0.0413

B 0.220 0.170 0.270 0.0087 0.0067 0.0106

C 0.100 0.210 0.0039 0.0083

CP 0.100 0.0039

D1 12.000 11.900 12.100 0.4724 0.4685 0.4764

E 20.000 19.800 20.200 0.7874 0.7795 0.7953

E1 18.400 18.300 18.500 0.7244 0.7205 0.7283

e 0.500 0.0197

L 0.600 0.500 0.700 0.0236 0.0197 0.0276

L1 0.800 0.0315

3 0 5 3 0 5

TSOP-G

B

e

DIE

C

LA1

E1

E

AA2

1

24

48

25

D1

L1

CP

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Figure 14. TFBGA48 6.39x10.5mm - 8x6 ball array, 0.75mm pitch, Bottom View Package Outline

Note: Drawing is not to scale.

Table 21. TFBGA48 6.39x10.5mm - 8x6 ball array, 0.75mm pitch, Package Mechanical Data

Symbolmillimeters inches

Typ Min Max Typ Min Max

A 1.200 0.0472

A1 0.260 0.0102

A2 1.000 0.0394

b 0.400 0.350 0.450 0.0157 0.0138 0.0177

D 6.390 6.290 6.490 0.2516 0.2476 0.2555

D1 5.250 0.2067

ddd 0.100 0.0039

E 10.500 10.400 10.600 0.4134 0.4094 0.4173

E1 3.750 0.1476

e 0.750 0.0295

FD 0.570 0.0224

FE 3.375 0.1329

SD 0.375 0.0148

SE 0.375 0.0148

E1E

D1

D

A2

A1A

BGA-Z34

ddd

e

e

SD

SE

b

FE

FD

BALL "A1"

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Figure 15. TFBGA48 Daisy Chain - Package Connections (Top view through package)

Figure 16. TFBGA48 Daisy Chain - PCB Connections proposal (Top view through package)

AI04390

C

B

A

87654321

E

D

F

AI04391

C

B

A

87654321

E

D

F

START

POINT

END

POINT

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PART NUMBERING

Table 22. Ordering Information Scheme

Example: M28W640FCT 90 N 6 T

Device Type

M28

Operating Voltage

W = VDD = 2.7V to 3.6V; VDDQ = 1.65V to 3.6V

Device Function

640FC = 64 Mbit (4 Mb x16), Boot Block, 0.13m

Array Matrix

T = Top BootB = Bottom Boot

Speed

70 = 70ns

85 = 85ns

90 = 90ns

10 = 100ns

Package

N = TSOP48: 12 x 20 mm

ZB = TFBGA48: 6.39 x 10.5mm, 0.75 mm pitch

Temperature Range

1 = 0 to 70 C

6 = 40 to 85 C

Option

Blank = Standard Package

T = Tape & Reel Packing

E = Lead-Free and RoHS Package, Standard Packing

F = Lead-Free and RoHS Package, Tape & Reel Packing

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Table 23. Daisy Chain Ordering Scheme

Note:Devices are shipped from the factory with the memory content bits erased to 1. For a list of available

options (Speed, Package, etc.) or for further information on any aspect of this device, please contact

the ST Sales Office nearest to you.

Example: M28W640FC -ZB T

Device TypeM28W640FC

Daisy Chain

-ZB = TFBGA48: 6.39 x 10.5mm, 0.75 mm pitch

Option

Blank = Standard Packing

E = Lead-Free and RoHS Package, Standard Packing

F = Lead-Free and RoHS Package, Tape & Reel Packing, 24mm

T = Tape & Reel Packing, 24mm

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APPENDIX A. BLOCK ADDRESS TABLES

Table 24. Top Boot Block Addresses,M28W640FCT

#Size

(KWord)Address Range

0 4 3FF000-3FFFFF

1 4 3FE000-3FEFFF

2 4 3FD000-3FDFFF

3 4 3FC000-3FCFFF

4 4 3FB000-3FBFFF

5 4 3FA000-3FAFFF

6 4 3F9000-3F9FFF

7 4 3F8000-3F8FFF

8 32 3F0000-3F7FFF

9 32 3E8000-3EFFFF

10 32 3E0000-3E7FFF

11 32 3D8000-3DFFFF

12 32 3D0000-3D7FFF

13 32 3C8000-3CFFFF

14 32 3C0000-3C7FFF

15 32 3B8000-3BFFFF

16 32 3B0000-3B7FFF

17 32 3A8000-3AFFFF

18 32 3A0000-3A7FFF

19 32 398000-39FFFF

20 32 390000-397FFF

21 32 388000-38FFFF

22 32 380000-387FFF

23 32 378000-37FFFF

24 32 370000-377FFF

25 32 368000-36FFFF

26 32 360000-367FFF

27 32 358000-35FFFF

28 32 350000-357FFF

29 32 348000-34FFFF

30 32 340000-347FFF31 32 338000-33FFFF

32 32 330000-337FFF

33 32 328000-32FFFF

34 32 320000-327FFF

35 32 318000-31FFFF

36 32 310000-317FFF

37 32 308000-30FFFF

38 32 300000-307FFF

39 32 2F8000-2FFFFF

40 32 2F0000-2F7FFF

41 32 2E8000-2EFFFF

42 32 2E0000-2E7FFF

43 32 2D8000-2DFFFF

44 32 2D0000-2D7FFF

45 32 2C8000-2CFFFF

46 32 2C0000-2C7FFF

47 32 2B8000-2BFFFF

48 32 2B0000-2B7FFF

49 32 2A8000-2AFFFF

50 32 2A0000-2A7FFF51 32 298000-29FFFF

52 32 290000-297FFF

53 32 288000-28FFFF

54 32 280000-287FFF

55 32 278000-27FFFF

56 32 270000-277FFF

57 32 268000-26FFFF

58 32 260000-267FFF

59 32 258000-25FFFF

60 32 250000-257FFF

61 32 248000-24FFFF62 32 240000-247FFF

63 32 238000-23FFFF

64 32 230000-237FFF

65 32 228000-22FFFF

66 32 220000-227FFF

67 32 218000-21FFFF

68 32 210000-217FFF

69 32 208000-20FFFF

70 32 200000-207FFF

71 32 1F8000-1FFFFF

72 32 1F0000-1F7FFF

73 32 1E8000-1EFFFF

74 32 1E0000-1E7FFF

75 32 1D8000-1DFFFF

76 32 1D0000-1D7FFF

77 32 1C8000-1CFFFF

78 32 1C0000-1C7FFF

79 32 1B8000-1BFFFF

80 32 1B0000-1B7FFF

81 32 1A8000-1AFFFF

#Size


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82 32 1A0000-1A7FFF

83 32 198000-19FFFF

84 32 190000-197FFF

85 32 188000-18FFFF

86 32 180000-187FFF

87 32 178000-17FFFF

88 32 170000-177FFF

89 32 168000-16FFFF

90 32 160000-167FFF

91 32 158000-15FFFF

92 32 150000-157FFF

93 32 148000-14FFFF

94 32 140000-147FFF95 32 138000-13FFFF

96 32 130000-137FFF

97 32 128000-12FFFF

98 32 120000-127FFF

99 32 118000-11FFFF

100 32 110000-117FFF

101 32 108000-10FFFF

102 32 100000-107FFF

103 32 0F8000-0FFFFF

104 32 0F0000-0F7FFF

105 32 0E8000-0EFFFF106 32 0E0000-0E7FFF

107 32 0D8000-0DFFFF

108 32 0D0000-0D7FFF

109 32 0C8000-0CFFFF

110 32 0C0000-0C7FFF

111 32 0B8000-0BFFFF

112 32 0B0000-0B7FFF

113 32 0A8000-0AFFFF

114 32 0A0000-0A7FFF

115 32 098000-09FFFF

116 32 090000-097FFF

117 32 088000-08FFFF

118 32 080000-087FFF

119 32 078000-07FFFF

120 32 070000-077FFF

121 32 068000-06FFFF

122 32 060000-067FFF

123 32 058000-05FFFF

124 32 050000-057FFF

125 32 048000-04FFFF

#Size


126 32 040000-047FFF

127 32 038000-03FFFF

128 32 030000-037FFF

129 32 028000-02FFFF

130 32 020000-027FFF

131 32 018000-01FFFF

132 32 010000-017FFF

133 32 008000-00FFFF

134 32 000000-007FFF

#Size


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Table 25. Bottom Boot Block Addresses,M28W640FCB

#Size


134 32 3F8000-3FFFFF

133 32 3F0000-3F7FFF

132 32 3E8000-3EFFFF

131 32 3E0000-3E7FFF

130 32 3D8000-3DFFFF

129 32 3D0000-3D7FFF

128 32 3C8000-3CFFFF

127 32 3C0000-3C7FFF

126 32 3B8000-3BFFFF

125 32 3B0000-3B7FFF

124 32 3A8000-3AFFFF

123 32 3A0000-3A7FFF

122 32 398000-39FFFF

121 32 390000-397FFF

120 32 388000-38FFFF

119 32 380000-387FFF

118 32 378000-37FFFF

117 32 370000-377FFF

116 32 368000-36FFFF

115 32 360000-367FFF

114 32 358000-35FFFF

113 32 350000-357FFF

112 32 348000-34FFFF

111 32 340000-347FFF

110 32 338000-33FFFF

109 32 330000-337FFF

108 32 328000-32FFFF

107 32 320000-327FFF

106 32 318000-31FFFF

105 32 310000-317FFF

104 32 308000-30FFFF

103 32 300000-307FFF

102 32 2F8000-2FFFFF101 32 2F0000-2F7FFF

100 32 2E8000-2EFFFF

99 32 2E0000-2E7FFF

98 32 2D8000-2DFFFF

97 32 2D0000-2D7FFF

96 32 2C8000-2CFFFF

95 32 2C0000-2C7FFF

94 32 2B8000-2BFFFF

93 32 2B0000-2B7FFF

92 32 2A8000-2AFFFF

91 32 2A0000-2A7FFF

90 32 298000-29FFFF

89 32 290000-297FFF

88 32 288000-28FFFF

87 32 280000-287FFF

86 32 278000-27FFFF

85 32 270000-277FFF

84 32 268000-26FFFF

83 32 260000-267FFF

82 32 258000-25FFFF

81 32 250000-257FFF

80 32 248000-24FFFF79 32 240000-247FFF

78 32 238000-23FFFF

77 32 230000-237FFF

76 32 228000-22FFFF

75 32 220000-227FFF

74 32 218000-21FFFF

73 32 210000-217FFF

72 32 208000-20FFFF

71 32 200000-207FFF

70 32 1F8000-1FFFFF

69 32 1F0000-1F7FFF68 32 1E8000-1EFFFF

67 32 1E0000-1E7FFF

66 32 1D8000-1DFFFF

65 32 1D0000-1D7FFF

64 32 1C8000-1CFFFF

63 32 1C0000-1C7FFF

62 32 1B8000-1BFFFF

61 32 1B0000-1B7FFF

60 32 1A8000-1AFFFF

59 32 1A0000-1A7FFF

58 32 198000-19FFFF

57 32 190000-197FFF

56 32 188000-18FFFF

55 32 180000-187FFF

54 32 178000-17FFFF

53 32 170000-177FFF

52 32 168000-16FFFF

51 32 160000-167FFF

50 32 158000-15FFFF

49 32 150000-157FFF

#Size


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48 32 148000-14FFFF

47 32 140000-147FFF

46 32 138000-13FFFF

45 32 130000-137FFF

44 32 128000-12FFFF

43 32 120000-127FFF

42 32 118000-11FFFF

41 32 110000-117FFF

40 32 108000-10FFFF

39 32 100000-107FFF

38 32 0F8000-0FFFFF

37 32 0F0000-0F7FFF

36 32 0E8000-0EFFFF35 32 0E0000-0E7FFF

34 32 0D8000-0DFFFF

33 32 0D0000-0D7FFF

32 32 0C8000-0CFFFF

31 32 0C0000-0C7FFF

30 32 0B8000-0BFFFF

29 32 0B0000-0B7FFF

28 32 0A8000-0AFFFF

27 32 0A0000-0A7FFF

26 32 098000-09FFFF

25 32 090000-097FFF24 32 088000-08FFFF

23 32 080000-087FFF

22 32 078000-07FFFF

21 32 070000-077FFF

20 32 068000-06FFFF

19 32 060000-067FFF

18 32 058000-05FFFF

17 32 050000-057FFF

16 32 048000-04FFFF

15 32 040000-047FFF

14 32 038000-03FFFF

13 32 030000-037FFF

12 32 028000-02FFFF

11 32 020000-027FFF

10 32 018000-01FFFF

9 32 010000-017FFF

8 32 008000-00FFFF

7 4 007000-007FFF

6 4 006000-006FFF

5 4 005000-005FFF

#Size


4 4 004000-004FFF

3 4 003000-003FFF

2 4 002000-002FFF

1 4 001000-001FFF

0 4 000000-000FFF

#Size


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APPENDIX B. COMMON FLASH INTERFACE (CFI)The Common Flash Interface is a JEDEC ap-proved, standardized data structure that can beread from the Flash memory device. It allows a

system software to query the device to determinevarious electrical and timing parameters, densityinformation and functions supported by the mem-ory. The system can interface easily with the de-vice, enabling the software to upgrade itself whennecessary.

When the CFI Query Command (RCFI) is issuedthe device enters CFI Query mode and the data

structure is read from the memory. Tables 26, 27,28, 29, 30 and 31 show the addresses used to re-trieve the data.

The CFI data structure also contains a securityarea where a 64 bit unique security number is writ-ten (see Table 31., Security Code Area). This areacan be accessed only in Read mode by the finaluser. It is impossible to change the security num-ber after it has been written by ST. Issue a Readcommand to return to Read mode.

Table 26. Query Structure Overview

Note: Query data are always presented on the lowest order data outputs.

Table 27. CFI Query Identification String

Note: Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are 0.

Offset Sub-section Name Description

00h Reserved Reserved for algorithm-specific information

10h CFI Query Identification String Command set ID and algorithm data offset

1Bh System Interface Information Device timing & voltage information

27h Device Geometry Definition Flash device layout

P Primary Algorithm-specific Extended Query tableAdditional information specific to the PrimaryAlgorithm (optional)

A Alternate Algorithm-specific Extended Query tableAdditional information specific to the AlternateAlgorithm (optional)

Offset Data Description Value

00h 0020h Manufacturer Code ST

01h8848h8849h

Device CodeTop

Bottom

02h-0Fh reserved Reserved

10h 0051h "Q"

11h 0052h Query Unique ASCII String "QRY" "R"

12h 0059h "Y"

13h 0003h Primary Algorithm Command Set and Control Interface ID code 16 bit ID codedefining a specific algorithm

Intelcompatible14h 0000h

15h 0035hAddress for Primary Algorithm extended Query table (see Table 29.) P = 35h

16h 0000h

17h 0000h Alternate Vendor Command Set and Control Interface ID Code second vendor -specified algorithm supported (0000h means none exists)

NA18h 0000h

19h 0000h Address for Alternate Algorithm extended Query table(0000h means none exists)

NA1Ah 0000h

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Table 28. CFI Query System Interface Information

Offset Data Description Value

1Bh 0027h

VDD Logic Supply Minimum Program/Erase or Write voltage

bit 7 to 4BCD value in voltsbit 3 to 0BCD value in 100 mV 2.7V

1Ch 0036hVDD Logic Supply Maximum Program/Erase or Write voltage

bit 7 to 4BCD value in voltsbit 3 to 0BCD value in 100 mV

3.6V

1Dh 00B4hVPP [Programming] Supply Minimum Program/Erase voltage

bit 7 to 4HEX value in voltsbit 3 to 0BCD value in 100 mV

11.4V

1Eh 00C6hVPP [Programming] Supply Maximum Program/Erase voltage

bit 7 to 4HEX value in voltsbit 3 to 0BCD value in 100 mV

12.6V

1Fh 0004h Typical time-out per single word program = 2n s 16s

20h 0004h Typical time-out for Double/Quadruple Word Program = 2n s 16s

21h 000Ah Typical time-out per individual block erase = 2n ms 1s

22h 0000h Typical time-out for full chip erase = 2n ms NA

23h 0005h Maximum time-out for Word program = 2n times typical 512s

24h 0005h Maximum time-out for Double/Quadruple Word Program = 2n times typical 512s

25h 0003h Maximum time-out per individual block erase = 2n times typical 8s

26h 0000h Maximum time-out for chip erase = 2n times typical NA

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