M2: Team Paradigm

:: Milestone 7 2-D Discrete Cosine Transform

Group M2:Tommy Taylor Brandon HsiungChangshi XiaoBongkwan Kim

Project Manager: Yaping Zhan

M2: Team Paradigm

Team Paradigm

M2: Team Paradigm

Project Status

18-525, Integrated Circuits Design Project

Design Proposal (Done)Architecture Proposal (Done)Gate level Design(Done)Component Layout (DRC & LVS): (Done)Component Simulation: (Done)Component Layout (Corrected)

Updated Floor planTo be done:

Chip LayoutSpice Simulation of Entire Chip

Still Speed but alsoReduction of size

Design Goals

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Updated components

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16:1 Mux - Schematic

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16:1 Mux - Layout

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16:1 Mux – Rise Delay (387pS)

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16:1 Mux – Rise time (208pS)

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16:1 Mux – Fall delay (402pS)

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16:1 Mux – Fall time (218pS)

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4:1 Mux – Layout (old)

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4:1 Mux – Layout (new)

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64x16 Dual Port SRAM

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64x16 dual port SRAM --- update

1. Get rid of floating word line, changed to pseudo-NMOS

2. Resize decoder transistors and sense amplifiers to ensure low noise margin

3. Relayout decoder to save a little area, reduced from 130x440 to 120x440

4. LVS, Extract and simulated extracted SRAM circuits

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64x16 dual port SRAM --- old decoder layout

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64x16 dual port SRAM --- new decoder layout

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64x16 dual port SRAM --- extracted simulation, read 0

Delay = 860.58 ps

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64x16 dual port SRAM --- extracted simulation, read 1

Delay = 907.14 ps

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Shift Register

: Dimensions- 87u x 13.9u

: Metals- M1, M2, M3

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::Mid-Buffer

: Dimensions: - 82.9u X 87.4u

: Metals: - M1, M2, M3

: Directionality:- Left to Right and Down

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Control Logic

85u by 21u

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1D-DCT Floorplan (old)

Total Area:

315u x 264u

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1D-DCT – Floorplan (new) 270u by 200u

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2D-DCT Floorplan (old)

Total Area:

505u x 484u

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2D-DCT – Floorplan (new) 430u by 400u

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::conclusion & questions