Luca Maria CassanoDate of birth May 3, 1985Citizenship ItalianLanguages Italian (native), English (fluent), Spanish (fluent),

Portuguese (fluent), French (basic), German (elementary)Current position Assistant Professor Senior (According to the Italian Law

n. 240/2010 - art. 24, par. 3, letter B)Italian National Qualification as Associate Professor in Information Processing SystemsScientific Qualification (Settore Concorsuale 09/H1 - Sistemi di elaborazione dell’informazione

from 26/07/2018 to 26/07/2024)Affiliation Dipartimento Elettronica, Informazione e Bioingegneria

Politecnico di Milano, Piazza L. Da Vinci, 32 - 20133 Milano - ItalyAddress Piazza L. Da Vinci, 32 - 20133 Milano - ItalyEmail luca.cassano@polimi.it

Web page http://cassano.faculty.polimi.it/

Main facts• Research interests: design, test, diagnosis and verification of reliable, secure and power-efficient embed-

ded systems.

• 6 papers in IEEE Transactions journals (two in the IEEE Trans. on Computers, one in the IEEE Trans.on Industrial Informatics, one in the IEEE Trans. on Emerging Topics in Computing and two in theIEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems) 4 papers at the Design,Automation & Test in Europe (DATE) Conference and 1 paper at the International Test Conference (ITC).In total 14 journal papers, 1 book chapter, 1 tutorial and 26 refereed conference and workshop paperssince the beginning of the academic career, in 2010 (First publication 2011: Academic age: 9 years).h-index: 10 � Total citations: 281 (source: Google Scholar, February 2020).h-index: 9 � Total citations: 199 (source: Scopus, February 2020).

• Winner of the European semi-finals (runner-up at the world finals) of the 2014 TTTC’s E. J. McCluskeyDoctoral Thesis Award for the best doctoral thesis in the field of electronic test technology

• Associate Editor of IEEE Access and of Integration, the VLSI Journal (Elsevier) from 2018 and of theJournal of Electronic Testing (Springer) from 2019. Member of the Technical Program Committee ofDATE, ETS, DFTS, IOLTS, GLSVLSI, DSD. Publicity Chair for DFTS 2019.

• Principal Investigator of “Adaptive Application-oriented Fault Detection for Reliable Image Processing”,a 55,000e grant from Intel Corporation. Co-Principal investigator of “OLTRE: On-Line Testing andHealing Permanent Radiation Effects in Reconfigurable Systems”, a 50,000e research project funded bythe European Space Agency with University of Pisa, Politecnico di Torino and University of Bielefeld(PI: Prof. M. Porrmann). Scientific co-Principal investigator of “FIND2: A flexible functional diagnosisframework based on machine-learning technique”, a 100,000US$ grant from Cisco University ResearchProgram Fund of Silicon Valley Community Foundation (PI: Prof. C. Bolchini).

• BS, MS and Ph.D. from the University of Pisa. Visiting research periods at the Politecnico di Torino,Italy (March 2012) and at the University of Bielefeld, Germany (April 2012→ September 2012).

Position and EducationRECORD OF EMPLOYMENT

March 2020 – present

Assistant Professor Senior (According to the Italian Law n. 240/2010 - art. 24, par. 3, letter B) atPolitecnico di Milano.

Sept. 2017 – Feb. 2020

Assistant Professor Junior (According to the Italian Law n. 240/2010 - art. 24, par. 3, letter A) atPolitecnico di Milano.

Feb. 2017 – Sept. 2017

Associate Member of the Technical Staff at Maxim Integrated mainly working as a Functional Verifica-tion Engineer.

Nov. 2016 – Jan. 2017

Teacher of “Sistemi e Reti” and “Tecnologie e Progettazione di Sistemi Informatici e di Telecomuni-cazioni” at Istituto Tecnico Tecnologico Paritario “S. Freud”.

Nov. 2014 – Jan. 2016

Temporary research assistant at the Dipartimento di Elettronica, Informazione e Bioingegneria of thePolitecnico di Milano, Italy, working on “FIND2: A flexible functional diagnosis framework based onmachine-learning techniques”.Advisor: Prof. C. Bolchini.

July 2013 – July 2014

Temporary research assistant at the Dipartimento di Elettronica, Informazione e Bioingegneria of thePolitecnico di Milano, Italy, working on “Exploiting (historical) test output data to improve functionaldiagnosis”.Advisor: Prof. C. Bolchini.

Mar. 2013 – June 2013

Temporary research assistant at the Istituto di Scienza e Tecnologie dellInformazione A. Faedo of theConsiglio Nazionale delle Ricerche, Pisa, Italy, working on “TRACE-IT - Train Control Enhancementvia Information Technology”.Advisor: Doc. S. Gnesi.

EDUCATION

Jul. 2018 – Jul. 2024

Italian national scientific qualification as Associate Professor in Information Processing Systems (SettoreConcorsuale 09/H1 - Sistemi di elaborazione dell’informazione)

Jan. 2010 – Dec. 2012

Ph.D. in Information Engineering from the Department of Information Engineering of the University ofPisa, Italy.Thesis title: Analysis and Test of the Effects of Single Event Upsets Affecting the Configuration Memoryof SRAM-based FPGAs.Advisor: Prof. C. Bernardeschi.

Jun. 2010

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Italian engineering licence (Professional practice examination), University of Pisa.

Sept. 2006 – July 2009

M.Sc. in Computer Engineering from the University of Pisa, Italy.Thesis title: Servizi di Sicurezza per Sistemi Publish/Subscribe Applicati a Reti Subacquee.Advisor: prof. G. Dini.Grade: 109/110.

Sept. 2003 – July 2006

B.Sc. in Computer Engineering from the University of Pisa, Italy.Thesis title: Sistema di Gestione di Risorse Condivise.Advisor: prof. F. Marcelloni.Grade: 103/110.

Sept. 1998 – July 2003

Scientific high school diploma from Liceo Scientifico F. Bruno, Corigliano Calabro, Italy.Grade: 100/100.

VISITING EXPERIENCES

Apr. 2012 – Sept. 2012

Cognitive Interaction Technology - Center of Excellence (CITEC) of the University of Bielefeld, Ger-many.Topic: Development of communication services for a dynamically reconfigurable satellite payload pro-cessing system based on FPGAs.Supervisor: Prof. M. Porrmann.

Mar. 2012

Department of Automation and Informatics of the Politecnico di Torino, Italy.Topic: Integration of a high-level model for Single Event Upset (SEU) faults into a SEU simulator forFPGA-based systems developed during the Ph.D. period at the University of Pisa.Supervisor: Prof. L. Sterpone.

SCHOLARSHIPS AND FUNDING

• Ph.D. scholarship from the Italian Ministry of University and Research (Jan 2010 – Dec. 2012).

AWARDS

• Winner of the European semi-finals (runner-up at the world finals) of the 2014 TTTC’s E. J. McCluskeyDoctoral Thesis Award with the PhD thesis “Analysis and Test of the Effects of Single Event UpsetsAffecting the Configuration Memory of SRAM-based FPGAs,”.

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Research interestsLuca Maria Cassano’s research interests fall into the area of embedded systems design methodologies, withparticular emphasis on the development of innovative methodologies to support system designers in dealingwith reliability, security and energy-related issues.

At present, the main research activity carried out by Luca Maria Cassano focuses on the definition of in-novative fault detection and management techniques specifically tailored for image processing and machinelearning-based applications. The idea is to exploit the intrinsic fault/error tolerance of such applications tomove from the classical corrupted/uncorrupted output detection to a usable/unusable output classification. Inthis way it would be possible to identify those output that, although corrupted by a fault, can still be effectivelyexploited by the end user, thus avoiding unnecessary re-executions and, as a consequence, saving time andpower. The first already published results of this research line raised the interest of several companies, such asIntel and Airbus, and research institutions, such as the European Space Agency. More in general, the researchactivity carried out by Luca Maria Cassano focuses on the development of methodologies for fault simula-tion, automatic test pattern generation, untestability analysis, functional diagnosis and formal verification ofelectronic circuits and systems as well as on the definition of novel methodologies for fault detection and man-agement. The main goal is to provide system designers with effective and efficient mechanisms (to be appliedboth during the design process and at runtime) to verify the correctness of the system, to study the behaviourof the system in the presence of faults, and to provide the system with fault detection, tolerance and diagnosiscapabilities. This is particularly important when the system is meant to be employed in application fields, suchas railways and aerospace, where a failure may cause severe damages to human operators, to equipment and tothe environment.

Moreover, Luca Maria Cassano is interested in developing novel methodologies to protect circuits fromsecurity attacks. In particular, the interest is on protecting systems against Differential Fault Analysis andHardware Trojans. The goal is to provide embedded systems designers with both hardware and softwaremechanisms (both circuit- and system-level) to prevent and detect the occurrence of fault attacks and thetriggering of hardware Trojans during system functioning. Such solutions are more and more required giventhe ubiquitous use and the globalized supply chain of digital devices.

On the energy side, the research activity is focused on the development of methodologies to support thedesigner in the assessment of the energy feasibility of the system before a prototype is available for on-the-field analysis. Such tools are vital when the system under design is a very-low-power device with no energyharvesting capabilities, as in the case of wireless sensor networks (WSNs), and when the system is meant tobe deployed in harsh environments, such as Antarctic, deserts and high mountains, where post-deploymentmaintenance is either very difficult and expensive or even impossible, as in the case of automatic weatherstations (AWSs).

RELIABILITY-RELATED ISSUES

Currently, Luca Maria Cassano is working at the definition of cost-effective and adaptive fault detection andmanagement techniques based on machine learning for image processing applications. In the past, Luca MariaCassano worked on the analysis and test of the effects of Single Event Upset (SEU) faults in the configurationmemory of SRAM-based FPGA systems (investigated during the Ph.D. period at the University of Pisa) andon the adaptive incremental functional fault diagnosis at the board-level (tackled during the PostDoc period atthe Politecnico di Milano). In both cases, the interest has been in using formal methods (stochastic Petri netsand model checking) and machine learning techniques (data mining, decision trees, genetic algorithms andartificial neural networks) in the field of embedded systems reliability.

Moreover, Luca Maria Cassano also started several scientific collaborations outside the above-mentionedresearch topics, investigating other reliability-related issues.

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Adaptive Fault Management for Image Processing Applications

The idea behind such research activity is that when considering image processing applications, the commonlyadopted fault detection/tolerance methods, e.g., the Duplication With Comparison (DWC), may produce worst-case conservative results since they discard processed data as soon as a single pixel in the output differs fromthe expected output. Indeed, in certain cases, the fault that affects the pipeline may cause the output imageto be only slightly altered, such that it may still be usable by the end user/application. In such a scenario, itwould be possible to continue the processing and transmission of the result using the slightly altered imagewithout any re-computation, thus saving time/power. On the other hand, heavily corrupted images shouldstill be discarded, triggering a pipeline re-execution. To achieve such a smart and adaptive fault detectionand management Luca Maria Cassano designed and implemented a novel checking methodologies based onconvolutional neural networks that proved to be extremely effective in identifying those images that, althoughaltered, are still usable by the specific application under analysis. In other words, this research proposes astrong paradigm shift, moving fault management mechanisms from faulty/unfaulty to usable/unusable imageidentification.Publications: [JR.2], [IC.4].

Board-level diagnosis

Big effort has been devoted to improve the board-level fault diagnosis process. Much work has been done toexploit historic log of previously performed testing activities to build an accurate model of the board and itscomponents and of the available tests. On the other hand, very few work addressed the runtime diagnosis pro-cess. The research activity carried out by Luca Maria Cassano in the field of board-level functional diagnosisfocuses on the design of novel methodologies meant to support design/test engineers during the runtime diag-nosis process. The idea is to exploit statistical and machine learning-based techniques (mainly decision treesand data mining) to drive the runtime diagnosis process by determining an efficient test execution order and byidentifying the faulty component(s) as early as possible. The final goal is to reduce the number of tests neededto be executed (and thus reduce the diagnosis time and cost) to determine the faulty component(s) on the boardby executing tests in an incremental and adaptive way. More in details, incremental test execution means thatafter the execution of each test the CAD tool decides whether to execute more tests or to stop the diagnosisprocess and determine the faulty component; adaptive test execution means that the CAD tools adapts the testexecution order based on the outcomes of the previously executed tests. This research activity allowed LucaMaria Cassano to get in touch with Prof. Krishnendu Chakrabarty from the Duke University, Durham, USAthat is one of the most recognized experts in the field of board-level diagnosis. Luca Maria Cassano, Prof.Chakrabarty and Doc. Bill Eklow from Cisco Systems, USA, organized a tutorial titled “Board-level func-tional fault diagnosis: industry needs and research solutions” at the Design, Automation and Test in EuropeConference (DATE) 2016 [TU.1].Publications: [JR.4] [JR.6] [JR.9] [IC.6] [IC.9].

SRAM-based FPGAs

In the last two decades, SRAM-based FPGA devices have been more and more employed in safety-criticalapplication fields. For this reason it is vital to provide designers of such systems with effective tools to analysethe reliability of the system, as well as to test whether the system is affected by faults or not. The analysis of thereliability of SRAM-based systems is generally performed with CAD tools that were originally designed forASIC systems. These CAD tools are not able to capture all the technological features of the FPGA technologyand thus they can hardly be adapted to the analysis of FPGA systems. The main novelty introduced by theactivity carried out by Luca Maria Cassano is the design and development of a set of analysis methodologiesthat adopt a different fault model than the stuck-at fault model (that is typically considered for digital circuits).The considered fault model has been demonstrated to be much more accurate than the classical stuck-at fault

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model when the focus is on SEU faults affecting the configuration memory of FPGA devices. An additionalnovelty of the research is that the engine of the designed tools relies on formal methods (stochastic Petri netsand model checking). A summary of the research activity carried out in the field of reliability analysis andtest of SRAM-based FPGA systems has been published in [IC.10] and [IC.17]. More in details, the activitiescarried out in this field are:

• the design, development and experimental validation (through the use of a fault injection board) of AS-SESS: an accurate SEU simulation environment based on the stochastic Petri nets formalism. ASSESShas been used to estimate the SEU sensitivity of SRAM-based FPGA systems as well as to assess thefault coverage achieved by externally generated test patterns for fault detection.Publications: [JR.11] [IC.20] [IC.22] [IC.24] [IC.25].

• the design and development of GABES: an environment for automatic test pattern generation address-ing SEUs in the configuration memory of FPGA systems. More in details, the approach addressed theconfiguration bits actually used by the design (application-dependent testing) and it relied on a geneticalgorithm for the generation of the test patterns and on the previously developed SEU simulator for theevaluation of the fault coverage achieved by the test patterns.Publications: [JR.13]

• the design and development of a tool for the analysis of the testability of SEUs in the configurationmemory used by an FPGA-based system. The designed tool relied on model-checking (the SAL formalspecification language and model-checker) and aimed at identifying the configuration bits that could bedemonstrated to be formally untestable. The output of this tool has then been used to speed-up the testpattern generation process carried out by the previously designed GABES environment.Publications: [JR.5] [IC.18] [IC.21].

• the design and development of a technique for on-line on-demand self-testing and self-healing for per-manent faults induced by radiation in reconfigurable systems. The methodology relied on a set of testcircuits and to be placed in the area of the device under test and on a custom place and route algorithm.The methodology exploited partial dynamic reconfigurability capabilities offered by todays SRAM-basedFPGAs to place the test circuits at run-time. The goal of of the methodology was to test unprogrammedareas of the FPGA before using them, thus preventing functional modules of the reconfigurable systemto be placed on areas with faulty resources.Publications: [JR.3] [IC.8] [IC.12] [IC.19]

An overview of the existing design standards, research proposals and lessons learned about the design andverification of SRAM-based FPGA systems in safety-critical application fields has been published in [JR.8].

HARDWARE SECURITY-RELATED ISSUES

Given the ubiquitous use and the globalized supply chain of modern integrated circuits, embedded systemsare more and more prone to security attacks. Luca Maria Cassano’s research activity in the field of hardwaresecurity focuses on the protection of embedded systems against differential fault analysis (DFA) and hardwaretrojans (HWTs). HWTs are malicious modifications of a circuit (introduced by designers, third-party intellec-tual property cores providers or foundries) that, under rare functioning conditions, activate and either modifythe behavior of the system or steal information. Several techniques for preventing, detecting and toleratingHWTs have been proposed in the last two decades while very few work has been done to provide benchmarksof HWT-infested circuits to evaluate such countermeasures. In this area, Luca Maria Cassano, together withDoc. Giorgio Di Natale from TIMA, Grenoble, France, proposed an emulation environment for HWTs intomicroprocessors.Publications: [IC.3].

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On the other hand, DFA aims at discovering the secret key used by a cryptographic hardware acceleratorby injecting faults into the circuit during encryption/decryption and by analysing the corrupted outputs. LucaMaria Cassano, together with Prof. Ramon Canal from the Universitat Politecnica de Catalunya, Barcelona,Spain, designed and developed a circuit-level countermeasure based on residue checking against DFA in RSAhardware accelerators. The proposed countermeasure allows to detect the 100% of the possible fault attackswith an extremely small area, power and delay overhead. Moreover, in order to make DFA unfeasible, thecircuit outputs a random value whenever a fault is detected.Publications: [IC.2].

Other works

Luca Maria Cassano has been also involved in the following research activities related to reliability and securityof digital systems and VLSI:

• The design, verification and reliability analysis of the safety-critical logic driver of a battery managementsystem for Li-ion batteries.Publications: [JR.12] [IC.15].

• The design and development of a CAD tool for an early analysis of the untestability of stuck-at faults inVLSI systems based on the use of model-checking.Publications: [IC.11].

• The design of an adaptive fault-tolerant flip-flop architecture.Publications: [IC.13].

• The experimental analysis of the effectiveness of several lifetime-aware load distribution policies for formulti-core systems [IC.5].

ENERGY-RELATED ISSUES

Within the field of energy feasibility analysis of embedded systems, Luca Maria Cassano worked on the evalua-tion of the energy feasibility of both wireless sensor networks (WSNs) and automatic weather stations (AWSs).A simulator of WSNs has been developed and then used to evaluate the effectiveness of Adaptive-BMAC+,a previously designed energy-aware adaptive MAC protocol. Further, Luca Maria Cassano participated at thedesign and development of AENEAS: an energy-aware simulator of AWSs. AENEAS is meant to support thedesigner in the study of the energy behaviour of the system before a prototype is available for energy analysison the field. The main feature of AENEAS is the ability to perform an holistic simulation of the system underanalysis, taking into account the effects on the energy behaviour of both a large variety of hardware compo-nents (batteries, microcontrollers, solar panels, wind turbines) and of the software tasks executed by the AWSmicrocontroller.Publications: [JR.10] [JR.7] [IB.1] [IC.7] [IC.14] [IC.16].

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SCIENTIFIC COLLABORATIONS

Ongoing

• Prof. Marco Ottavi from University Tor vergata, Rome, Italy, on the definition of a protection architec-ture for microprocessor-based systems against the activation of HW Trojan Horses infesting the dataand instruction memories.

• Prof. Erdem Koyuncu from the University of Illinois Chicago, USA, on the definition of innovativemachine learning-based techniques for an adaptive fault detection and management in image processingapplications.

• Prof. R. Canal from the Universitat Politecnica de Catalunya, Barcelona, Spain, on the design and de-velopment of circuit-level countermeasures against differential fault analysis in cryptographic hardwareaccelerators.

• Doc. G. Di Natale from TIMA, Grenoble, France, on the design and development of runtime counter-measures against HW Trojans in microprocessors based on assembly-level software diversification andobfuscation.Past

• Prof. M. Porrmann from the University of Bielefeld, Germany, and Prof. L. Sterpone from the Po-litecnico di Torino, Italy, on the design and development of a self-testing and self-healing processingplatform based on reconfigurable computing.

• Prof. M. Angel Aguirre and Prof. H. Guzman-Miranda from University of Sevilla, Spain, on theanalysis of the untestability of SEU faults in VLSI systems.

• Doc. G. Di Natale and Prof. A. Bosio from the Laboratoire d’Informatique, de Robotique et deMicrolectronique de Montpellier, France on the design of an adaptive flip-flop architecture for hardwaresystems having dynamically changing reliability requirements.

• Prof. Krishnendu Chakrabarty from the Duke University, Durham, USA, and Doc. Bill Eklow fromCisco Systems, USA, on the organization of a tutorial about board-level functional fault diagnosis heldat the Design, Automation and Test in Europe Conference (DATE) 2016.

• Prof. M. Avvenuti from the University of Pisa, Italy, Doc. D. Cesarini from the Scuola SuperioreSant’Anna, Pisa, Italy, and Prof. V. Bilas and Doc. M. Kuri from the University of Zagreb, Croatia, onthe design and development of an energy-aware simulator of automatic weather stations.

• Prof. R. Saletti, Prof. R. Roncella and Prof. F. Baronti from the University of Pisa, Italy, on the designand formal verification of the safety driver of a battery management system for Li-ion batteries.

• Prof. L. Sterpone from the Politecnico di Torino, Italy, on the development of an accurate fault simula-tor for SRAM-based FPGA-based systems.

• Prof. M. Avvenuti and Prof. A. Vecchio from the University of Pisa, Italy, on the performance evalua-tion of an adaptive MAC protocol for wireless sensor networks.

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Professional ActivitiesNATIONAL AND INTERNATIONAL RESEARCH PROJECTS

Luca Maria Cassano is/has been principle investigator for the following funded research projects/grants:

• Adaptive Application-oriented Fault Detection for Reliable Image Processing, an INTEL CORPORATION

55,000e grant running from January 2020 till January 2021.

Luca Maria Cassano is/has been directly responsible for the following funded research projects/grants:

• OLTRE: On-Line Testing and Healing Permanent Radiation Effects in Reconfigurable Systems, an EU-ROPEAN SPACE AGENCY ITI PROJECT, 50,000e, ESA Contract ITT AO/1-6067/09/NL/CBI (ReferenceNumber: A00016022), running from Jan. 2015 till Sept. 2015. Local co-principal investigator and WPleader for WP4 ”Fault Injection Experimental Evaluation” (PI: Prof. Mario Porrmann)

Luca Maria Cassano also contributes/contributed actively in funded research projects, more precisely:

• FIND2: A flexible functional diagnosis framework based on machine-learning techniques. Cisco Univer-sity Research Program Fund Gift #2014-130689 (3696). 100,000US$. (PI: Prof. C. Bolchini)

• Exploiting (historical) test output data to improve functional diagnosis. Cisco University Research Pro-gram Fund Gift #2012-101762 (3696). (PI: Prof. C. Bolchini)

• TRACE-IT - Train Control Enhancement via Information Technology, TUSCANY REGIONAL RESEARCH

PROJECT (TRACE-IT, PAR-FAS-2007-2013). (PI: Doc. S. Gnesi)

EDITORIAL BOARD MEMBERSHIPS

• Associate Editor of IEEE Access (2018 – present).

• Associate Editor of Integration, the VLSI Journal (2018 – present).

• Associate Editor of Journal of Electronic Testing (2019 – present).

ORGANIZING COMMITTEE MEMBERSHIPS

• Publicity/Web Chair for the IEEE International Symposium on Defect and Fault Tolerance in VLSI andNanotechnology Systems (2019 – present).

• Registration Chair for the IEEE International Symposium on On-Line Testing and Robust System Design(2020).

TECHNICAL PROGRAM COMMITTEE MEMBERSHIPS

• The T4 “System-Level Reliability Design, Analysis and On-line Test” track of the Design, Automationand Test in Europe Conference (2019 – present).

• The IEEE European Test Symposium (2015, 2016, 2018).

• The IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems(2018 – present).

• The IEEE International Symposium on On-Line Testing and Robust System Design (2018 – present).

• The IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (2019– present).

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• The ACM Great Lakes Symposium on VLSI (2018).

• The Dependability, Testing, and Fault Tolerance in Digital Systems Session within the Euromicro Con-ference on Digital System Design (2018 – present).

• The Architecture and Hardware for Security Applications Session within the Euromicro Conference onDigital System Design (2018 – present).

• The IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era(2014).

• The Hipeac Workshop on Reconfigurable Computing (2014 – 2016).

• The Symposium on Modelling and Simulation in Computer Sciences and Engineering (2015)

REFEREE SERVICES

Luca Maria Cassano is a reviewer for several journals and conferences in the field of Computer Aided Designand embedded systems: IEEE Trans. on Computers, IEEE Trans. on VLSI, IEEE Trans. on CAD, IEEETrans. on Emerging Topics in Computing, IEEE Access, Elsevier International Journal on Microprocessorsand Microsystems, ICCAD, ICIT, IOLTS, DFTS, ARC and ARCS.

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Teaching activity2019 – 2020

Fundamental of Computer Science (Lecturer) - Mechanical and Energetic Engineering - Undergraduatelevel, Politecnico di Milano. 7 CFU (35 hours Lecturer)

2019 – 2020

Reti Logiche (Teaching Assistant) - Computer Engineering - Undergraduate level, Politecnico di Milano.7 CFU (20 hours Teaching Assistant)

2018 – 2019

Fundamental of Computer Science (Lecturer) - Mechanical and Energetic Engineering - Undergraduatelevel, Politecnico di Milano. 7 CFU (35 hours Lecturer)

2018 – 2019

Reti Logiche (Teaching Assistant) - Computer Engineering - Undergraduate level, Politecnico di Milano.7 CFU (20 hours Teaching Assistant)

2017 – 2018

Fundamental of Computer Science (Lecturer) - Mechanical and Energetic Engineering - Undergraduatelevel, Politecnico di Milano. 7 CFU (35 hours Lecturer + 10 hours Teaching Assistant)

2013 – 2014, 2014 – 2015, 2015 – 2016

Fundamental of Computer Science (Lab. Supervisor) - Computer Engineering - Undergraduate level,Politecnico di Milano. 10 CFU (18 hours Lab. Supervisor)

2010 – 2011, 2011 – 2012, 2012 – 2013

Fundamental of Computer Science (Lab. supervisor) - Computer Engineering - Undergraduate level,University of Pisa. 12 CFU (18 hours Lab. Supervisor)

STUDENTS’ SUPERVISION

• Andrea Mazzeo, 2019, “A Hybrid Fault Injection Framework for Image Processing Applications inFPGA”. Politecnico di Milano, Italy.

• Matteo Biasielli, 2019, “A Neural Network Based Fault Detection/Management Scheme For ReliableImage Processing Applications”. Politecnico di Milano, Italy.

• Matteo Biasielli, 2019, “A Neural Network Based Fault Management Scheme for Reliable Image Pro-cessing”. University of Illinois Chicago, USA.

• Riccardo Cattaneo, 2019, “Runtime Resource Management Middleware for Heterogenous EmbeddedSystems”. Politecnico di Milano, Italy.

• Filippo Mascolo, 2015, “Design and implementation of a routing algorithm to maximize test coverage ofpermanent faults in FPGAs”. University of Pisa, Italy.

• Luca Santangelo, 2014, “Viv2XDL: a bridge between Vivado and XDL based software”. University ofPisa, Italy.

• Domenico Sorrenti, 2014, “Exploiting Partial Dynamic Reconfiguration for On-Line On-Demand Detec-tion of Permanent Faults in SRAM-based FPGAs”. University of Pisa, Italy.

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• Alessio Fagioli, 2013, “Modeling and Simulation of Automatic Weather Stations with mixed energysources for the design of Sensing and Communication policies”. University of Pisa, Italy.

• Silvia Mandala, 2013, “Verso l’autonomic sensing: simulazione e valutazione energetica di una Auto-matic Weather Station”. University of Pisa, Italy.

• Alessio Amato, 2011, “Simulazione e valutazione di un protocollo MAC adattivo per reti di sensoritramite Stochastic Activity Networks”. University of Pisa, Italy.

• Massimiliano Leone Itria, 2011, “Progetto e realizzazione di un traduttore per il linguaggio EDIF orien-tato a sistemi FPGA”. University of Pisa, Italy.

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Selected publications1

These are the 5 selected publications.

1. M. Biasielli, C. Bolchini, L. Cassano, E. Koyuncu, A. Miele, A Neural Network Based Fault ManagementScheme for Reliable Image Processing”, To appear in IEEE Trans. on Computers.

2. D. Cozzi, S. Korf, L. Cassano, J. Hagemeyer, A. Domenici, C. Bernardeschi, M. Porrmann and L. Ster-pone, “OLT(RE)2: an On-Line on-demand Testing approach for permanent Radiation Effects in RE-congurable systems”, In IEEE Trans. on Emerging Topics in Computing Vol. 6, no. 4 (2018), pp.511-523.

[doi: http://dx.doi.org/10.1109/TETC.2016.2586195]

3. C. Bolchini and L. Cassano, “A Novel Approach to Incremental Functional Diagnosis for Complex Elec-tronic Boards,” IEEE Transactions on Computers Vol. 65, no. 1, (2016), pp. 42-52, (ISSN: 0018-9340)

[doi: http://dx.doi.org/10.1109/TC.2015.2417537]

4. C. Bernardeschi, L. Cassano, A. Domenici, and L. Sterpone, “ASSESS: A Simulator of Soft Errors inthe Configuration Memory of SRAM-based FPGAs,” IEEE Transactions on Computer-Aided Design ofIntegrated Circuits and Systems Vol. 33, no. 9, (2014), pp. 1342-1355, (ISSN: 0278-0070)

[doi: http://dx.doi.org/10.1109/TCAD.2014.2329419]

5. F. Baronti, C. Bernardeschi, L. Cassano, A. Domenici, R. Roncella, R. Saletti, “Design and Safety Verifi-cation of a Distributed Charge Equalizer for Modular Li-ion Batteries,” IEEE Transactions on IndustrialInformatics Vol. 10, no. 2, (2014), pp. 1003-1011, (ISSN: 1551-3203)

[doi: http://dx.doi.org/10.1109/TII.2014.2299236]

Complete publication listPUBLICATION LIST

Refereed international journals 14Refereed international books and book chapters 1Tutorials 1Refereed international conferences/symposia/workshops with formal proceedings 26Refereed international workshops and poster presentations without formal proceedings 8Invited talks and seminars 6Awards 2

h-index: 10 � Total citations: 281 (source: Google Scholar, February 2020).h-index: 9 � Total citations: 199 (source: December, February 2020).

1In Italy, authors typically appear in alphabetical order

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REFEREED INTERNATIONAL JOURNALS

JR.1. Giacomo Tanganelli, Luca Cassano, Antonio Miele, Carlo Vallati “A Methodology for the Design and Deployment ofDistributed Cyber-Physical Systems for Smart Environments”, To appear in Future Generation Computer Systems

JR.2. M. Biasielli, C. Bolchini, L. Cassano, E. Koyuncu, A. Miele, “A Neural Network Based Fault Management Scheme forReliable Image Processing”, To appear in IEEE Trans. on Computers.

JR.3. D. Cozzi, S. Korf, L. Cassano, J. Hagemeyer, A. Domenici, C. Bernardeschi, M. Porrmann and L. Sterpone, “OLT(RE)2:an On-Line on-demand Testing approach for permanent Radiation Effects in REcongurable systems”, In IEEE Trans.on Emerging Topics in Computing Vol. 6, no. 4 (2018), pp. 511-523.[doi: http://dx.doi.org/10.1109/TETC.2016.2586195]

JR.4. C. Bolchini and L. Cassano, “A Fully Automated and Congurable Cost-Aware Framework for Adaptive FunctionalDiagnosis”, IEEE Design & Test, Vol. 34, no. 2, (2017), pp. 79-86[doi: http://dx.doi.org/10.1109/MDAT.2016.2550584]

JR.5. C. Bernardeschi, L. Cassano, A. Domenici and L. Sterpone, UA2TPG: “An untestability analyzer and test pattern gener-ator for SEUs in the configuration memory of SRAM-based FPGAs,” Integration, the VLSI Journal vol. 55 (2016), pp.85-97 [doi: http://dx.doi.org/10.1016/j.vlsi.2016.03.004]

JR.6. C. Bolchini and L. Cassano, “A Novel Approach to Incremental Functional Diagnosis for Complex Electronic Boards,”IEEE Transactions on Computers Vol. 65, no. 1, (2016), pp. 42-52, (ISSN: 0018-9340)[doi: http://dx.doi.org/10.1109/TC.2015.2417537]

JR.7. M. Avvenuti, C. Bernardeschi, L. Cassano, and A. Vecchio, “Adapting the duty cycle to traffic load in a preamblesampling MAC for WSNs,” Ad Hoc & Sensor Wireless Networks Vol. 31, no. 1-4, (2016), pp. 101-129, (ISSN: 1552-0633)

JR.8. C. Bernardeschi, L. Cassano, and A. Domenici, “SRAM-based FPGA Systems for Safety-Critical Applications: ASurvey on Design Standards and Proposed Methodologies,” Journal of Computer Science and Technology Vol. 30, no.2, (2015), pp. 373-390, (ISSN: 1000-9000), (ISSN: 1860-4749)[doi: http://dx.doi.org/10.1007/s11390-015-1530-5]

JR.9. C. Bolchini, L. Cassano, P. Garza, E. Quintarelli, and F. Salice, “An Expert CAD Flow for Incremental FunctionalDiagnosis of Complex Electronic Boards,” IEEE Transactions on Computer-Aided Design of Integrated Circuits andSystems Vol. 34, no. 5, (2015), pp. 835-848, (ISSN: 0278-0070)[doi: http://dx.doi.org/10.1109/TCAD.2015.2396997]

JR.10. D. Cesarini, L. Cassano, M. Avvenuti, M. Kuri, V. Bilas, “AENEAS: an Energy-Aware Simulator of Automatic WeatherStations,” IEEE Sensors Journal Vol. 14, no. 11, (2014), pp. 3932-3943, (ISSN: 1530-437X)[doi: http://dx.doi.org/10.1109/JSEN.2014.2353011]

JR.11. C. Bernardeschi, L. Cassano, A. Domenici, and L. Sterpone, “ASSESS: A Simulator of Soft Errors in the ConfigurationMemory of SRAM-based FPGAs,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and SystemsVol. 33, no. 9, (2014), pp. 1342-1355, (ISSN: 0278-0070)[doi: http://dx.doi.org/10.1109/TCAD.2014.2329419]

JR.12. F. Baronti, C. Bernardeschi, L. Cassano, A. Domenici, R. Roncella, R. Saletti, “Design and Safety Verification of aDistributed Charge Equalizer for Modular Li-ion Batteries,” IEEE Transactions on Industrial Informatics Vol. 10, no.2, (2014), pp. 1003-1011, (ISSN: 1551-3203)[doi: http://dx.doi.org/10.1109/TII.2014.2299236]

JR.13. C. Bernardeschi, L. Cassano, M.G.C.A. Cimino, A. Domenici, “GABES: a Genetic Algorithm Based Environment forSEU Testing in SRAM-FPGAs,” Journal of Systems Architecture Vol. 59, no. 10, part D, (2013), pp. 1243-1254, (ISSN:1383-7621)[doi: http://dx.doi.org/10.1016/j.sysarc.2013.10.006]

JR.14. C. Bernardeschi, L. Cassano, A. Domenici, P. Masci, “Simulation and Test-Case Generation for PVS Specificationsof Control Logics,” International Journal On Advances in Software Vol. 5, no. 1&2, (2011), pp. 327-341, (ISSN:1942-2628)

REFEREED CHAPTERS IN INTERNATIONAL BOOKS

IB.1. L. Cassano, D. Cesarini, M. Avvenuti, “On the use of Stochastic Activity Networks for an Energy-aware Simulation ofAutomatic Weather Stations,” In Handbook of Research on Computational Simulation and Modeling in Engineering,ed. Francisco Miranda and Carlos Abreu, pp. 184-207 (2016)[doi: http://dx.doi.org/10.4018/978-1-4666-8823-0.ch006]

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TUTORIAL

TU.1. L. Cassano, K. Chakrabarty, B. Eklow, “Board-level functional fault diagnosis: industry needs and research solutions,”DATE 2016, Design Automation & Test in Europe

REFEREED INTERNATIONAL CONFERENCES/SYMPOSIA/WORKSHOPS WITH FORMAL PROCEED-INGS

IC.1. M. Biasielli, L. Cassano, A. Miele, “An Approximation-based Fault Detection Scheme for Image Processing Appli-cations,” Accepeted at DATE 2020, Design Automation & Test in Europe, Grenoble, France, March 9-13, 2020, pp.1-6.

IC.2. A. Lasheras, R. Canal, E. Rodriguez and L. Cassano, “Protecting RSA Hardware Accelerators against Differential FaultAnalysis through Residue Checking,” Proc. DFTS’19, the IEEE International Symposium on Defect and Fault Tolerancein VLSI and Nanotechnology Systems, October 2 - October 4, 2019, ESA-ESTEC & TU Delft, Netherlands[doi: http://dx.doi.org/10.1109/DFT.2019.8875320]

IC.3. C. Bolchini, L. Cassano, I. Montalbano, G. Repole, A. Zanetti, G. Di Natale, “HATE: a HArdware Trojan EmulationEnvironment for Microprocessor-based Systems,” Proc. IOLTS’19, the 25th IEEE International Symposium on On-LineTesting and Robust System Design, Rhodes Island, Greece, July 1-3, 2019.[doi: http://dx.doi.org/10.1109/IOLTS.2019.8854414]

IC.4. M. Biasielli, C. Bolchini, L. Cassano, A. Miele, “A Smart Fault Detection Scheme for Reliable Image ProcessingApplications,” Proc. DATE 2019, Design Automation & Test in Europe, Florence, Italy, March 25-29, 2019, pp. 1-6.[doi: http://dx.doi.org/10.23919/DATE.2019.8714945]

IC.5. C. Bolchini, L. Cassano, A. Miele, “Lifetime-aware Load Distribution Policies in Multi-core Systems: An In-depthAnalysis,” Proc. DATE 2016, Design Automation & Test in Europe, Dresden, Germany, March 14-18, 2016, pp. 804-809.

IC.6. C. Bolchini and L. Cassano, “A Configurable Board-level Adaptive Incremental Diagnosis Technique based on DecisionTrees,” Proc. IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems(DFT), University of Massachusetts Amherst, USA, October 12-14, 2015.[doi: http://dx.doi.org/10.1109/DFT.2015.7315167]

IC.7. L. Cassano, D. Cesarini, M. Avvenuti, “Using Stochastic Activity Networks to Study the Energy Feasibility of AutomaticWeather Stations,” Proc. Symposium on Modelling and Simulation in Computer Sciences and Engineering (MSCSE),Rhodes, Greece, September 22-28, 2014, pp. 1 - 4.[doi: http://dx.doi.org/10.1063/1.4912935]

IC.8. D. Sorrenti, D. Cozzi, S. Korf, L. Cassano, J. Hagemeyer, M. Porrmann and C. Bernardeschi, “Exploiting DynamicPartial Reconfiguration for On-Line On-Demand Testing of Permanent Faults in Reconfigurable Systems,” Proc. IEEEInternational Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), Amsterdam, TheNetherlands, October 1-3, 2014, pp. 203 - 208.[doi: http://dx.doi.org/10.1109/DFT.2014.6962065]

IC.9. C. Bolchini and L. Cassano, “Machine Learning-based Techniques for Board-level Incremental Functional Diagnosis: aComparative Analysis,” Proc. IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnol-ogy Systems (DFT), Amsterdam, The Netherlands, October 1-3, 2014, pp. 246 - 251.[doi: http://dx.doi.org/10.1109/DFT.2014.6962064]

IC.10. L. Cassano, “Analysis and Test of the Effects of Single Event Upsets Affecting the Configuration Memory of SRAM-based FPGAs,” Proc. IEEE International Test Conference (ITC), Seattle, Washington, USA, October 21-23, 2014, pp.1 - 10.[doi: http://dx.doi.org/10.1109/TEST.2014.7035366]

IC.11. L. Cassano, H. Guzman-Miranda and M.A. Aguirre, “Early Assessment of SEU Sensitivity through Untestable FaultsIdentification,” Proc. IEEE International On-Line Testing Symposium (IOLTS), Platja d’Aro, Catalunya, Spain, July7-9, 2014, pp. 186 - 189.[doi: http://dx.doi.org/10.1109/IOLTS.2014.6873692]

IC.12. L. Cassano, D. Cozzi, D. Jungewelter, S. Korf, J. Hagemeyer, M. Porrmann and C. Bernardeschi, “An Inter-ProcessorCommunication Interface for Data-Flow Centric Heterogeneous Embedded Multiprocessor Systems,” Proc. IEEE Inter-national Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), Santorini, Greece, May6-8, 2014, pp. 1 - 6.[doi: http://dx.doi.org/10.1109/DTIS.2014.6850669]

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IC.13. L. Cassano, A. Bosio and G. Di Natale, “A novel Adaptive Fault Tolerant Flip-Flop Architecture based on TMR,” Proc.IEEE European Test Symposium (ETS), Paderborn, Germany, May 26-30, 2014, pp. 1 - 2.[doi: http://dx.doi.org/10.1109/ETS.2014.6847831]

IC.14. D. Cesarini, L. Cassano, A. Fagioli and M. Avvenuti, “Modeling and Simulation of Energy-Aware Adaptive Policiesfor Automatic Weather Stations,” Proc. DATE 2014 Workshop on Engineering Simulations for Cyber-Physical Systems(ES4CPS), Bremen, Germany, March 28, 2014, pp. 44 - 47.[doi: http://dx.doi.org/10.1145/2559627.2559631]

IC.15. F. Baronti, C. Bernardeschi, L. Cassano, A. Domenici, R. Roncella, R. Saletti, “Mitigation of Single Event Upsets in theControl Logic of a Charge Equalizer for Li-ion Batteries,” Proc. Annual Conference of the IEEE Industrial ElectronicsSociety (IECON), Vienna, Austria, November 10-13, 2013, pp. 6758 - 6763.[doi: http://dx.doi.org/10.1109/IECON.2013.6700251]

IC.16. M. Avvenuti, L. Cassano, D. Cesarini and S. Mandala, “Simulation of Automatic Weather Stations for the EnergyEstimation of Sensing and Communication Software Policies,” Proc. Extreme Conference on Communication (Ex-tremeCom), Iceland, August 24-30, 2013, pp. 1 - 6.

IC.17. C. Bernardeschi, L. Cassano and A. Domenici, “Formal approaches to SEU testing in FPGAs,” Proc. NASA/ESAConference on Adaptive Hardware and Systems (AHS), Torino, Italy, June 25-27, 2013, pp. 209 - 216.[doi: http://dx.doi.org/10.1109/AHS.2013.6604248]

IC.18. C. Bernardeschi, L. Cassano, A. Domenici and L. Sterpone, “Unexcitability Analysis of SEUs Affecting the RoutingStructure of SRAM-based FPGAs,” Proc. Great Lakes Symposium on Very Large Scale of Integration (GLSVLSI),Paris, France, May 2-3, 2013, pp. 7 - 12.[doi: http://dx.doi.org/10.1145/2483028.2483050]

IC.19. L. Cassano, D. Cozzi, S. Korf, J. Hagemeyer, M. Porrmann and L. Sterpone, “On-Line Testing of Permanent RadiationEffects in Reconfigurable Systems,” Proc. Design Automation & Test in Europe (DATE), Grenoble, France, March18-22, 2013, pp. 717 - 720.[doi: http://dx.doi.org/10.7873/DATE.2013.154]

IC.20. C. Bernardeschi, L. Cassano, A. Domenici, L. Sterpone, “Accurate Simulation of SEUs in the Configuration Memoryof SRAM-based FPGAs,” Proc. IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotech-nology Systems (DFT), Austin, Texas, USA, October 3-5, 2012, pp. 115 - 120.[doi: http://dx.doi.org/10.1109/DFT.2012.6378210]

IC.21. C. Bernardeschi, L. Cassano, A. Domenici, “SEU-X: a SEu Un-eXcitability prover for SRAM-FPGAs,” Proc. IEEEInternational On-Line Testing Symposium (IOLTS), Sitges, Spain, June 27-29, 2012, pp. 25 - 30.[doi: http://dx.doi.org/10.1109/IOLTS.2012.6313836]

IC.22. C. Bernardeschi, L. Cassano, A. Domenici, G. Gennaro, M. Pasquariello, “Simulated Injection of Radiation-InducedLogic Faults in FPGAs,” Proc. International Conference on Advances in System Testing and Validation Lifecycle(VALID), SBarcelona, Spain, October 23-28, 2011, pp. 84 - 89.

IC.23. C. Bernardeschi, L. Cassano, A. Domenici, P. Masci, “A Tool for Signal Probability Analysis of FPGA-Based Sys-tems,” Proc. International Conference on Computational Logics, Algebras, Programming, Tools, and Benchmarking(COMPUTATION TOOLS), Rome, Italy, September 25-30, 2011, pp. 13 - 18,.

IC.24. C. Bernardeschi, L. Cassano, A. Domenici, “Failure Probability and Fault Observability of SRAM-FPGA Systems,”Proc. International Conference on Field Programmable Logic and Applications (FPL), Chania, Crete, Greece, Septem-ber 5-7, 2011, pp. 385 - 388.[doi: http://dx.doi.org/10.1109/FPL.2011.75]

IC.25. C. Bernardeschi, L. Cassano, A. Domenici, “Failure Probability of SRAM-FPGA Systems with Stochastic ActivityNetworks,” Proc. IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), Cottbus,Germany, April 13-15, 2011, pp. 293 - 296.[doi: http://dx.doi.org/10.1109/DDECS.2011.5783098]

IC.26. C. Bernardeschi, L. Cassano, A. Domenici, P. Masci, “Debugging PVS Specifications of Control Logics via Event-driven Simulation,” Proc. International Conference on Computational Logics, Algebras, Programming, Tools, andBenchmarking (COMPUTATION TOOLS), Lisbon, Portugal, November 21-26, 2010, pp. 1 - 7.

REFEREED INTERNATIONAL WORKSHOPS AND POSTER PRESENTATIONS WITHOUT FORMAL PRO-CEEDINGS

WS.1. C. Bolchini, L. Cassano, “Reducing the Effort for Board-level Functional Diagnosis through Incremental Test Execu-tion,” International Test Conference (ITC), Seattle, Washington, USA, October 21-23, 2014.

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WS.2. C. Bolchini, L. Cassano, G. Di Natale, “Multi-stage Cross-layer Hardware Trojan Prevention, Detection and Tolerance,”Joint MEDIAN-TRUDEVICE Open Forum, Amsterdam, The Netherlands, September 30, 2014.

WS.3. C. Bolchini, L. Cassano,, “Detecting Possible Locations for Hardware Trojans by Identifying Untestable Faults,” Work-shop on Test and Fault Tolerance for Secure Devices (TRUDEVICE), Paderborn, Germany, May 29-30, 2014.

WS.4. L. Cassano, “Analysis and Test of the Effects of Single Event Upsets Affecting the Configuration Memory of SRAM-based FPGAs,” E.J. McCluskey Doctoral Thesis Award Semifinals, Paderborn, Germany, May 26-30, 2014.

WS.5. L. Cassano, “Analysis and Test of the Effects of Single Event Upsets Affecting the Configuration Memory of SRAM-based FPGAs,” EDAA/ACM SIGDA PhD Forum at DATE 2014, Bremen, Germany, March 24-28, 2014.

WS.6. L. Cassano, D. Cozzi, S. Korf, J. Hagemeyer, M. Porrmann and L. Sterpone, “A CAD Flow for On-Line Testing andPatching Permanent Radiation Effects in Reconfigurable Systems,” SEE/MAPLD 2013 joint session of the Single EventEffects Symposium and Military and Aerospace Programmable Logic Devices Conference, San Diego, California, USA,April 9-12, 2013.

WS.7. L. Cassano, “A CAD Flow for the Analysis of the Sensitivity to SEUs of SRAM-FPGAs,” ESA SpacE FPGA UsersWorkshop (SEFUW), Nordwjik, The Netherlands, November 6-7, 2012.

WS.8. C. Bernardeschi, L. Cassano, M.G.C.A. Cimino, A. Domenici, “Application of a Genetic Algorithm for Testing SEUsin SRAM-FPGA Systems,” HiPEAC Workshop on Reconfigurable Computing (WRC), Paris, France, January 24, 2012.

INVITED TALKS AND SEMINARS

IN.1. Cristiana Bolchini, Luca Cassano, Antonio Miele, “Reliability Analysis and Design for ML-based Applications,” heldat Agenzia Spaziale Italiana, Rome, Italy, February 13, 2020

IN.2. “Fault Tolerant and Secure Embedded Systems,” held at Department of Electronic Engineering of the University ofRome Tor Vergata, January 31, 2020

IN.3. “Analysis and Test of the Effects of Single Event Upsets in the Configuration Memory of SRAM-based FPGA Systems,”held at Istituto di Scienza e Tecnologie dellInformazione A. Faedo - National Research Council of Italy (CNR), Pisa, Italy,March 1, 2013.

IN.4. “Reconfigurable Systems: the Dynamically Reconfigurable Processing Module Project,” held at Department of Infor-mation Engineering, University of Pisa, Italy, October 22, 2012.

IN.5. “Tools for the Analysis of SEU Effects into SRAM-FPGA Systems,” held at Cluster of Excellence Center in CognitiveInteractive Technology (CITEC) - University of Bielefeld, Germany, April 20, 2012.

IN.6. “An Introduction to Fault Detection in FPGA Systems,” held at Department of Information Engineering, University ofPisa, Italy, January 31, 2012.

AWARDS

AW.1. Winner of the European semi-finals (runner-up at the world finals) of the 2014 TTTC’s E. J. McCluskey Doctoral ThesisAward with the PhD thesis “Analysis and Test of the Effects of Single Event Upsets Affecting the Configuration Memoryof SRAM-based FPGAs,”.

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