LTC3305 - Lead-Acid Battery Balancer€¦ · Lead-Acid Battery Balancer The LTC®3305 balances up to 4 lead-acid batteries connected in series. It is intended to be used in conjunction

LTC3305

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For more information www.linear.com/LTC3305

TYPICAL APPLICATION

FEATURES DESCRIPTION

Lead-Acid Battery Balancer

The LTC®3305 balances up to 4 lead-acid batteries connected in series. It is intended to be used in conjunction with a separate pre-existing battery charger as part of a high performance battery system. All voltage monitoring, gate drive, and fault detection circuitry is integrated.

The LTC3305 employs an auxiliary battery or an alternative storage cell to transfer charge to or from each individual battery in the stack. A mode pin provides two operating modes, timer mode and continuous mode. In timer mode, once the balancing operation is completed, the LTC3305 goes into a low power state for a programmed time and then periodically rebalances the batteries. In continuous mode, the balancing operation continues even after the batteries are balanced to their programmed termination voltage.

The LTC3305 is available in a thermally enhanced 38-lead TSSOP package.

4-Battery Balancer with Programmed High and Low Battery Voltage Faults

Battery Voltages Converge Over Time

APPLICATIONS

n Single IC Balances Up to Four 12V Lead-Acid Batteries in Series

n All NFET Designn Stackable to Balance Larger Series Battery Packsn Standalone Balancing Operation: Requires No

External μP or Additional Control Circuitryn Balancing Current Limited by External PTC Thermistorn Continuous Mode and Timer Moden Programmable UV and OV Fault Thresholdsn Programmable Termination Time and Termination

Voltagen Thermally Enhanced 38-Lead TSSOP Package

n Telecom Backup Systemsn Home Battery Powered Backup Systemsn Industrial Electric Vehiclesn Energy Storage Systems (ESS)n Medical Equipment

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.

BATTERY 4BATTERY 3BATTERY 2BATTERY 1

TIME3305 TA01a

16

14

12

10

8

6

4

2

0

BATT

ERY

VOLT

AGE

(V)

VREGEN1EN2MODETERM1TERM2

DONE

BATXBATYCTON

CTOFF

CTBAT

VL

VH

GND

LTC3305

AUXN

AUXP

V1

V2

V3

V4

CM CP

BOOST

NGATE1-9

ISET

UVFLTOVFLT

BALPTCFLT

10µF25V

10µF25V

10µF25V

10nF

100nF

10nF

27.4k

6.04k

1.33k

100k EACH

249Ω

6.04k

3.01k

6.04k

6.04k

42.2k

12.1k

10µF25V

10µF25V

9

6.04k

6.04k

6.04k

6.04k

1µF6V

10µF25V

NGATE5

NGATE6

NGATE7

NGATE8

NGATE9

3305 TA01

PTC

AUX10µF25V

NGATE4

NGATE3

NGATE2

NGATE1

BAT4

BAT3

BAT2

BAT1+

+

+

+

+

ICHARGE BATTERYSTACK

CHARGER

CHARGERSUPPLY

http://www.linear.com/LTC3305


LTC3305

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PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS

Stack Voltage, V4 to GND .........................................68VBattery Voltages, V4 to V3, V3 to V2, V2 to V1, V1 to GND .................................................. –0.3V to 20VAuxiliary Cell Voltage, AUXP to AUXN ........ –0.3V to 20VVREG Voltage ................................................ –0.3V to 6VVH, VL Voltage ..... –0.3V to Lesser of 6V or (VREG+0.3V)UVFLT, OVFLT, PTCFLT, BAL, DONE, BATX, BATY Voltage ............................................... –0.3V to 6VEN1, EN2, MODE, TERM1, TERM2 Voltage ................ –0.3V to Lesser of 6V or (VREG+0.3V)NGATE1, NGATE2, NGATE3, NGATE4, NGATE8, NGATE9

Voltage .............. –0.3V to Lesser of 68V or (V4+0.3V)NGATE5, NGATE6, NGATE7

Voltage .............. (Greater of –0.3V or BOOST–68V) to (BOOST+0.3V)*

UVFLT, OVFLT, PTCFLT, BAL, DONE, BATX, BATY Current .........................................................10mAISET Current ..............................................................1mACP, CM Current.......................................................50mAOperating Junction Temperature Range (Notes 2, 3) ............................................ –40°C to 125°CStorage Temperature Range .................. –65°C to 150°CLead Temperature (Soldering, 10 sec) ................... 300°C

*The BOOST voltage is generated by the LTC3305 and is typically 8.45V higher than V4.

(Note 1)

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

TOP VIEW

FE PACKAGE38-LEAD PLASTIC TSSOP

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

BOOST

V4

V3

AUXP

AUXN

V2

V1

NGATE1

NGATE2

NGATE3

NGATE4

NGATE5

NGATE6

NGATE7

NGATE8

NGATE9

BATX

BATY

OVFLT

CM

CP

NC

MODE

EN1

EN2

TERM1

TERM2

VREG

ISET

VH

VL

CTBAT

CTON

CTOFF

PTCFLT

DONE

BAL

UVFLT

39GND

θJA = 28°C/W

EXPOSED PAD (PIN 39) IS GND, MUST BE SOLDERED TO PCBNC = No Connect

ORDER INFORMATION

LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC3305EFE#PBF LTC3305EFE#TRPBF LTC3305 FE 38-Lead Plastic TSSOP –40ºC to 125°C

LTC3305IFE#PBF LTC3305IFE#TRPBF LTC3305 FE 38-Lead Plastic TSSOP –40ºC to 125°C

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.

(http://www.linear.com/product/LTC3305#orderinfo)


http://www.linear.com/product/LTC3305#orderinfo

LTC3305

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ELECTRICAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VBAT Individual Battery Voltage l 4 16 V

V4 Voltage at the Top of the Battery Stack l 12 64 V

VREG Regulator Output Voltage IVREG = 200µA l 2.4 2.5 2.6 V

VREG,UV Regulator Undervoltage Threshold Regulator Voltage Falling l 1.7 2.1 V

Hysteresis 125 mV

Maximum Guaranteed Load Current VREG > VREG,UV l 3 mA

Regulator Short Circuit Current Limit VREG = 0V 8 15 22 mA

Shutdown Current Measured at V4, BOOST-V4 = 0V Measured at V3, V2, V1, AUXP, BOOST

l

16 33 0

50 1

µA µA

Supply Current While Balancing Battery 1 (Notes 4, 5)

Measured at V4 Measured at V3 Measured at V2 Measured at V1

900 0 0

150

1350 1 1

225

µA µA µA µA



–70

900 0

150 –45

1350 1

225

µA µA µA µA



–70

900 150 –45 0

1350 225

1

µA µA µA µA



–70

1050 –45 0 0

1575 1 1

µA µA µA µA

Supply Current While Balancing any Battery Measured at AUXP Measured at AUXN

–195

165 –130

245 µA µA

Supply Current in OFF State (MODE = 0) Measured at V4, BOOST-V4 = 0V Measured at V3, V2, V1, AUXP, BOOST

100 0

150 1

µA µA

Boost Pin Current While Balancing any Battery (Notes 4, 5)

220 330 µA

VISET ISET Servo Voltage 50µA< IISET< 150µA l 1.18 1.2 1.22 V

IVH, IVL Current Out of VH and VL Pins IISET = 100µA l 31.3 33.3 35.3 µA

INGATE Current For External NMOS Turn On (Note 5) Leakage Current in Shutdown

NGATE3 Current, IISET = 100µA All Other NGATE Currents, IISET = 100µA EN1 = EN2 = 0

l

l

l

2.0 1.0 –2

2.2 1.1

2.4 1.2 2

mA mA µA

Current Programmable Range NGATE3 Current All Other NGATE Currents

l

l

1 0.5

3 1.5

mA mA

VBAT,UV Undervoltage Falling Battery Threshold (Note 6) VL = 0.4V VL = 1.6V

l

l

3.9 15.6

4 16

4.1 16.4

V V

Undervoltage Hysteresis 120 mV

Undervoltage Falling Programmable Range l 4 16 V

VBAT,OV Overvoltage Rising Battery Threshold (Note 6) VH = 0.4V VH = 1.6V

l

l

3.9 15.6

4 16

4.1 16.4

V V

Overvoltage Hysteresis 150 mV

Overvoltage Rising Programmable Range l 4 16 V

The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C. (Note 2) V1 = 13.2V, V2 = 26.4V, V3 = 39.6V, V4 = 52.8V, AUXP - AUXN = 13.2V, RISET = 12.1kΩ


LTC3305

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The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C. (Note 2) V1 = 13.2V, V2 = 26.4V, V3 = 39.6V, V4 = 52.8V, AUXP - AUXN = 13.2V, RISET = 12.1kΩ

Note 1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime.Note 2. The LTC3305 is tested under pulsed load conditions such that TJ ≈ TA. The LTC3305E is guaranteed to meet specifications from 0ºC to 85ºC junction temperature. Specifications over the –40ºC to 125ºC operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LTC3305I is guaranteed over the –40°C to 125°C operating junction temperature range. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance, and other environmental factors. The junction temperature (TJ, in °C) is calculated from the ambient temperature (TA, in °C) and power dissipation (PD, in Watts) according to the formula: TJ = TA + (PD • θJA), where θJA (in °C/W) is the package thermal impedance.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

PTC Fault Threshold |BAT-AUXP| Falling 0.8 1 1.2 V

Hysteresis 100 mV

VTERMINATE |BAT-AUXP| for Which Balancing Is Terminated TERM2 = 0, TERM1 = 0 TERM2 = 0, TERM1 = 1 TERM2 = 1, TERM1 = 0 TERM2 = 1, TERM1 = 1

l

l

l

l

5.0 17.5 40 85

12.5 25 50

100

20.0 32.5 60

115

mV mV mV mV

Minimum (BOOST-V4) Voltage for Operation l 6.7 6.95 7.2 V

Hysteresis 180 mV

Maximum (BOOST-V4) Voltage Regulated l 8.45 8.75 V

Hysteresis 200 mV

RNMOS Charge Pump NMOS Switch ON Resistance Measured at 10mA 20 Ω

RPMOS Charge Pump PMOS Switch ON Resistance Measured at 10mA 55 Ω

tBAT Maximum Time a Single Battery Stays Connected to the Auxiliary Battery

CTBAT = 10nF 4.5 5 5.5 sec

tON Maximum Stack Balancing Termination Time MODE = 0, CTON = 10nF 0.43 0.48 0.53 hrs

tOFF Off Time After Stack Balance Termination MODE = 0, DONE = 0, CTOFF = 10nF 0.43 0.48 0.53 hrs

VIH Digital Input High Voltage EN1, EN2, MODE, TERM1, TERM2 Pins l 1.2 V

VIL Digital Input Low Voltage EN1, EN2, MODE, TERM1, TERM2 Pins l 0.4 V

IIH, IIL Leakage Current EN1, EN2, MODE, TERM1, TERM2 Pins; 2.5V at Pin

l –1 1 µA

VOL Output Low Voltage BATX, BATY, BAL, DONE, UVFLT, OVFLT, PTCFLT Pins; 3mA Into Pin

l 27.5 150 mV

IOH Output High Leakage Current BATX, BATY, BAL, DONE, UVFLT, OVFLT, PTCFLT Pins; 6V at Pin

1 µA

Thermal Shutdown Threshold (Note 7) Rising Temperature 155 °C

Thermal Shutdown Hysteresis 10 °C

Note 3. Continuous operation above the specified maximum operating junction temperature may result in device degradation or failure.Note 4. The NGATE pin currents are not included in this number.Note 5. The NGATE5, NGATE6, NGATE7 pin currents are drawn from the BOOST pin. All other NGATE pin currents are drawn from the V4 pin. The NGATE pin currents add to the currents drawn by V4 and BOOST.Note 6. The voltage programmed at the VH and VL pins are gained up to set the undervoltage and overvoltage thresholds of each battery. Note 7: This IC includes overtemperature protection intended to protect the device during momentary overload conditions. The maximum junction temperature may be exceeded when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may result in device degradation or failure.

ELECTRICAL CHARACTERISTICS


LTC3305

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TYPICAL PERFORMANCE CHARACTERISTICS

INGATE vs IISET INGATE vs Temperature

IISET (µA)

I NGA

TE (m

A)

3305 G07

0.4

1.21.11.00.90.80.70.60.5

1.31.41.51.61.71.8

50 60 70 80 90 100 110 120 130 140 150

ALL NGATE PIN CURRENTS

AND NGATE3 CURRENT 2

V4 = 52.8V, VNGATE = 0V

UV Threshold vs Temperature

TEMPERATURE (°C)

I NGA

TE (m

A)

3305 G08

1.00

1.16

1.14

1.12

1.10

1.08

1.06

1.04

1.02

1.18

1.20

–55 –35 –15 5 25 45 65 85 105 125

ALL NGATE PIN CURRENTS AND NGATE3 CURRENT

V4 = 52.8V, VNGATE = 0V, RISET = 12kΩ2

TEMPERATURE (°C)

BATT

ERY

VOLT

AGE

(V)

3305 G09

4.75

4.80

5.20

5.15

5.05

5.10

5.00

4.90

4.95

4.85

5.25

–55 –35 –15 255 45 65 10585 125

RISING

FALLING

RISET = 12.1kRVL = 15k

TA = 25°C, unless otherwise noted.

OFF State Current vs Temperature

TEMPERATURE (°C)

I V4

(µA)

3305 G05

75

95

90

85

80

100

105

110

115

120

125

–55 –35 –15 5 25 45 65 85 105 125

V4 = 64V

V4 = 52.8V

V4 = 12V

VISET vs Temperature

TEMPERATURE (°C)

V ISE

T (V

)

3305 G06

1.180

1.190

1.185

1.195

1.200

1.205

1.210

1.215

1.220

–55 –35 –15 5 25 45 65 85 105 125

Shutdown Current vs Temperature

VREG,UV vs Temperature

TEMPERATURE (°C)

V REG

,UV

(V)

3305 G03

1.5

1.7

1.6

1.8

1.9

2.0

2.1

2.3

2.4

2.2

2.5

–55 –35 –15 5 25 45 65 85 105 125

RISING

FALLING

TEMPERATURE (°C)

I V4

(µA)

3305 G04

15

20

25

35

30

40

45

50

55

–55 –35 –15 5 25 45 65 85 105 125

V4 = 64V

V4 = 52.8V

V4 = 12V

VREG Line and Load Regulation VREG vs Temperature

TEMPERATURE (°C)

V REG

(V)

3305 G02

2.00

2.05

2.10

2.15

2.20

2.25

2.30

2.35

2.40

2.45

2.50

2.55

–55 –35 –15 5 25 45 65 85 105 125

IVREG = 3mA, V4 = 12VIVREG = 1mA, V4 = 52.8VIVREG = 0.2mA, V4 = 52.8V

CURRENT (mA)

V REG

(V)

3305 G01

0.0

0.40.2

0.60.81.01.21.41.61.82.02.22.42.62.83.0

0 3 6 9 12 15

V4 = 12V

V4 = 52.8V


LTC3305

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25mV Termination Threshold vs Temperature

UV and OV Programming Gain

OV Threshold vs Temperature

12.5mV Termination Threshold vs Temperature

Maximum Battery Current During PTC Fault Condition

PTC Fault Threshold vs Temperature

UV Threshold vs Temperature

TEMPERATURE (°C)

BATT

ERY

VOLT

AGE

(V)

3305 G10

9.5

10.3

10.2

9.9

10.1

10.0

9.8

9.6

9.7

10.4

10.5

–55 –35 –15 255 45 65 10585 125

RISING

FALLING

RISET = 12.1kRVL = 30.1k

TEMPERATURE (°C)

I V1

(µA)

3305 G15

425

475

465

455

445

435

485

495

505

515

525

–55 –35 –15 255 45 65 10585 125

V1 = 13.2V, AUXN = AUXP = GND

TEMPERATURE (°C)

V TER

MIN

ATE

(mV)

3305 G16

2.5

18.5

16.5

14.5

12.5

10.5

8.5

6.5

4.5

20.5

22.5

–55 –35 –15 255 45 65 10585 125

TEMPERATURE (°C)

|V1-

AUXP

| (m

V)

3305 G14

900

1075

1100

1125

1150

1050

1000

1025

950

975

925

1175

1200

–55 –35 –15 255 45 65 10585 125

RISING

V1 = 13.2V, AUXN = GND

FALLING

VL OR VH (V)

V BAT

,UV/

V L o

r VBA

T,OV/

V H (V

/V)

3305 G13

9.5

10.0

10.1

10.2

10.3

9.9

9.7

9.8

9.6

10.4

10.5

0.4 0.5 0.6 1.11.00.90.7 0.8 1.2 1.3 1.51.4 1.6

UV GAIN

OV GAIN

TEMPERATURE (°C)

BATT

ERY

VOLT

AGE

(V)

3305 G12

14.4

14.9

15.0

15.1

15.2

14.8

14.6

14.7

14.5

15.3

15.4

–55 –35 654525–15 5 85 105 125

RISET = 12.1kRVH = 45.3k

RISING

FALLING

OV Threshold vs Temperature

TEMPERATURE (°C)

BATT

ERY

VOLT

AGE

(V)

3305 G11

7.20

7.55

7.60

7.65

7.50

7.40

7.35

7.30

7.45

7.25

7.70

–55 –35 654525–15 5 85 105 125

RISET = 12.1kRVH = 22.6k

RISING

FALLING

50mV Termination Threshold vs Temperature

TEMPERATURE (°C)

V TER

MIN

ATE

(mV)

3305 G17

15

31

29

27

25

23

21

19

17

33

35

–55 –35 –15 255 45 65 10585 125TEMPERATURE (°C)

V TER

MIN

ATE

(mV)

3305 G18

40

56

54

52

50

48

46

44

42

58

60

–55 –35 –15 255 45 65 10585 125



LTC3305

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Boost Charge Pump Start-Up

Minimum Boost Voltage vs Temperature

100mV Termination Threshold vs Temperature tON, tOFF vs Temperature

tBAT vs Temperature VOL vs Temperature

VREG Start-Up

100µs/DIV

500mV/DIV

CVREG = 2.2µF

0V

3305 G245ms/DIV

CH2, 0V5V/DIV

CH1, 0V2V/DIV

VOLTAGE ACROSS CBOOST

VOLTAGE ACROSS CFLY

3305 G25

TEMPERATURE (°C)

V OL

(mV)

I = 3mA

3305 G23

15.0

40.0

37.5

35.0

32.5

30.0

27.5

25.0

22.5

20.0

17.5

42.5

45.0

–55 –35 –15 255 45 65 10585 125TEMPERATURE (°C)

TIM

E (S

ECON

DS)

CTBAT = 10nF (COG)

3305 G22

4.5

5.3

5.2

5.1

5.0

4.9

4.8

4.7

4.6

5.4

5.5

–55 –35 –15 255 45 65 10585 125

TEMPERATURE (°C)

TIM

E (H

OURS

)

V4 = 52.8VCTON = CTOFF = 10nF (COG)

3305 G21

0.450

0.505

0.500

0.495

0.490

0.485

0.480

0.475

0.470

0.465

0.460

0.455

0.510

–55 –35 –15 255 45 65 10585 125TEMPERATURE (°C)

V BOO

ST-V

4 (V

)

3305 G20

6.5

7.0

6.9

6.8

6.7

6.6

7.1

7.2

–55 –35 –15 255 45 65 10585 125

RISING

FALLING

TEMPERATURE (°C)

V TER

MIN

ATE

(mV)

3305 G19

90

104

106

98

100

102

96

92

94

108

110

–55 –35 –15 255 45 65 10585 125



LTC3305

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PIN FUNCTIONSBOOST (Pin 1): Charge Pump Output. Decouple with a 10µF capacitor to V4.

V4 (Pin 2): Positive terminal of Battery 4 connects to this pin. Battery 4 is connected between V4 and V3. Decouple with at least a 10µF capacitor to V3.


AUXP (Pin 4): Positive terminal of the auxiliary cell con-nects to this pin. Decouple with at least a 10µF capacitor to AUXN.

AUXN (Pin 5): Negative Terminal of the auxiliary cell con-nects to this pin.


V1 (Pin 7): Positive terminal of Battery 1 connects to this pin. Battery 1 is connected between V1 and GND. Decouple with at least a 10µF capacitor to GND.

NGATE1 (Pin 8): NMOS1 Gate. Connect to the gate terminal of external NMOS switch.

NGATE2 (Pin 9): NMOS2 Gate. Connect to the gate terminal of external NMOS switch.

NGATE3 (Pin 10): NMOS3 Gate. Connect to the gate ter-minal of external NMOS switch.







BATX (Pin 17): This pin along with BATY indicates which battery in the stack is currently being balanced and to which the fault outputs apply. Open Drain Output.

BATY (Pin 18): This pin along with BATX indicates which battery in the stack is currently being balanced and to which the fault outputs apply. Open Drain Output.

OVFLT (Pin 19): Overvoltage Fault. This pin is pulled low when an overvoltage fault condition is detected on a bat-tery. Open Drain Output.

UVFLT (Pin 20): Undervoltage Fault. This pin is pulled low when an undervoltage fault condition is detected on a battery. Open Drain Output.

BAL (Pin 21): Balancing Indicator. This pin is pulled low while the balancing operation is being performed and is in its high impedance state when the part is disabled or the part is in the sleep state. Open Drain Output.

DONE (Pin 22): Done Indicator. This pin is pulled low when all the batteries in the stack are balanced. This pin is in its high impedance state in shutdown. Open Drain Output.

PTCFLT (Pin 23): PTC Fault. This pin is pulled low when the voltage across the PTC thermistor exceeds 1V. It is in its high impedance state at all other times. Open Drain Output.

CTOFF (Pin 24): A capacitor from this pin to GND programs the retry time in timer mode. Connect to GND if MODE = 1.

CTON (Pin 25): A capacitor from this pin to GND programs the maximum time for the balancing operation in timer mode. Connect to GND if MODE = 1.

CTBAT (Pin 26): A capacitor from this pin to GND programs the maximum time an individual battery in the stack is con-nected to the auxiliary cell during the balancing operation.

VL (Pin 27): Low Voltage Fault Threshold. A resistor from this pin to GND programs the low voltage fault threshold for each battery in the series stack. Works in conjunction with the ISET pin.

VH (Pin 28): High Voltage Fault Threshold. A resistor from this pin to GND programs the high voltage fault threshold for each battery in the series stack. Works in conjunction with the ISET pin.


LTC3305

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ISET (Pin 29): Reference Current Pin that Servos to 1.2V. A resistor from this pin to GND programs the gate charge current for the external NMOS switches. The reference current is also used to program the undervoltage and overvoltage thresholds.

VREG (Pin 30): Low Voltage Regulated Output. An inter-nally generated voltage of 2.5V is always present at this pin. The voltage at this pin may be overdriven by a higher external voltage up to 5.5V. This pin has limited current sink capability and will not pull down a higher externally applied voltage. All logic input pins must be referenced to this pin. Decouple with a 1µF capacitor to GND.

TERM2 (Pin 31): Termination Threshold Select. This pin along with TERM1 is used to set the voltage difference between the battery and auxiliary cell at which a battery is deemed balanced. High input impedance pin, do not float.

TERM1 (Pin 32): Termination Threshold Select. This pin along with TERM2 is used to set the voltage difference between the battery and auxiliary cell at which a battery is deemed balanced. High input impedance pin, do not float.

EN2 (Pin 33): Enable Input. The state of the EN1 and EN2 pins is used to indicate the number of batteries in the stack. With both pins at GND, the part is in shutdown. High input impedance pin, do not float.

EN1 (Pin 34): Enable Input. The state of the EN1 and EN2 pins is used to indicate the number of batteries in the stack. With both pins at GND, the part is in shutdown. High input impedance pin, do not float.

MODE (Pin 35): Mode Select. When held high, continuous mode is selected. When held low, timer mode is selected. High input impedance pin, do not float.

No Connect (Pin 36): This pin is not connected internally. Solder this pin to a pad electrically isolated from all other circuit nodes.

CP (Pin 37): Positive Terminal of Charge Pump Flying Capacitor. Connect a 10µF capacitor from this pin to CM for charge pump operation.

CM (Pin 38): Negative Terminal of Charge Pump Flying Capacitor. Connect a 10µF capacitor from this pin to CP for charge pump operation.

GND (Pin 39): The exposed pad is ground and must be soldered to PCB ground for electrical connectivity and rated thermal performance.

PIN FUNCTIONS


LTC3305

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BLOCK DIAGRAM

37

2

3

6

7

29

28

27

31

32

4

5

38

8

9

10

11

12

13

14

15

16

24

25

26

30

33

34

35

17

18

19

20

21

22

23

GND

CP

CM

NGATE1

V4

V3

V2

V1

ISET

VH

VL

TERM2

TERM1

AUXP

AUXN

NGATE2

NGATE3

NGATE4

NGATE5

NGATE6

NGATE7

NGATE8

NGATE9

CTOFF

CTON

CTBAT

VREG

EN2

36NO CONNECT

EN1

MODE

BATX

BATY

BAL

OVFLT

UVFLT

DONE

PTCFLT

1

GATE DRIVE

BOOST

CHARGEPUMP

LOWVOLTAGE

REGULATOR

TERMINATIONSENSE

COMPARATOR

CONTROLLOGIC

BANDGAP

REFERENCE1.2V

THERMALSHUTDOWN OT

3305 BD

MIRROR V4

UV/OV

TIMERS

39

+–

MUX


LTC3305

113305fb


OPERATIONThe LTC3305 balancer is intended to be used in conjunc-tion with a separate pre-existing battery stack charger as part of a high performance battery system. The balancing operation itself is stand-alone and can operate independent of whether the battery stack is being charged, discharged, or both. That being said, because the LTC3305 balances voltages, it works best if the voltage readings are stable, which is more true when the battery stack is not being charged or discharged. Nevertheless, it will properly bal-ance the battery voltages when the stack is being concur-rently charged and/or discharged, since the voltage across the batteries will average out over time as the LTC3305 repeatedly cycles through them. Like all balancers, the LTC3305 will slightly net-discharge the stack in the absence of a separate charger.

The LTC3305 balances batteries using an auxiliary cell or an alternate storage cell as a charge reservoir. External NMOS switches are controlled in a preprogrammed sequence to connect each battery in the stack to an auxiliary cell. Charge is transferred to or from the auxiliary cell when it is connected to a battery.

The LTC3305 can operate in one of two modes program-mable via the MODE pin.

Timer Mode (MODE = 0)

The balancing operation begins once the CBOOST capacitor is charged to at least 6.95V. The BAL pin is pulled low, indicating that the part is enabled and balancing the bat-tery stack.

The termination voltage, VTERMINATE, is the difference in voltage between the auxiliary cell and the battery connected to the auxiliary cell for which a battery is considered to be balanced. VTERMINATE is programmed via the TERM1 and TERM2 pins to one of four preset voltages as shown in Table 1. Table 1. Termination Voltages

TERM1 TERM2 VTERMINATE

0 0 ±12.5mV

1 0 ±25mV

0 1 ±50mV

1 1 ±100mV

The balancing operation begins with the negative terminal of the auxiliary cell connected to the negative terminal of BAT1, the lowest battery in the stack. Referring to Figure 1, the bottom switches N1 and N9 that connect the negative terminal of BAT1 to the auxiliary cell’s negative terminal are first turned on. To turn on an external NMOS switch, the current source at the NGATE pin connected to the gate of the external NMOS is turned on and a gate source voltage is developed across an external resistor.

After an internally set delay of 35ms, the voltages across the auxiliary cell and BAT1 are compared by the termina-tion sense comparator.

If the voltage difference between the auxiliary cell and BAT1 is less than the selected termination voltage, the battery is deemed to be balanced with respect to the auxiliary cell and the bottom switches are turned off by turning off the corresponding NGATE pin currents. The next battery in the stack is then connected to the auxiliary cell.

Figure 1. External Switch Arrangement for a 4- Battery Balancing Application

NGATE5

N5

N4

N6

NGATE4BAT4

N3B

NGATE3

NGATE2N3A

BAT3

BAT2

BAT1

3305 F01

+

+

+

+

+AUX

PTC

NGATE6

NGATE1-9

LTC3305

AUXP

AUXN N2

N7

N8

N9

NGATE7

NGATE8 NGATE1

N1NGATE9

9


LTC3305

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OPERATION

Table 2. Top and Bottom Switch Arrangement

EN1, EN2BATTERY BEING

BALANCEDTOP

SWITCHESBOTTOM

SWITCHES

1,1 (4 Bat App)

Battery 1 N2, N7 N1, N9




1,0 (3 Bat App)




0,1 (2 Bat App)

Battery 1 N7 N9

Battery 2 N5 N8

If the voltage difference between the auxiliary cell and BAT1 is greater than the selected termination voltage, the top NMOS switches N2 and N7 that connect the positive terminal of BAT1 to the auxiliary cell’s positive terminal through the PTC thermistor are turned on. After a second internally set delay of 35ms, the termination sense com-parator starts monitoring the voltages across the auxiliary cell and the battery. The battery stays connected to the auxiliary cell until the voltage difference decreases to VTERMINATE or a tBAT timeout occurs (tBAT is the maximum time that a battery remains connected to the auxiliary cell and is programmed by a capacitor on the CTBAT pin). This timer is reset each time the auxiliary cell is connected to a different battery.

At this point, all switches are turned off and the next bat-tery in the stack is connected to the auxiliary cell. After the switches have been turned off, an internal 40ms delay provides a break-before-make time after which the nega-tive terminal of the next battery in the stack is connected to the negative terminal of the auxiliary cell via its bottom switches. Table 2 shows the top and bottom switches used to connect each battery for different battery stack configurations. When only the bottom switches are on, there is a conduction path between the auxiliary cell and the battery through the body diodes of the top switches. Current will flow through this conduction path if the aux-iliary cell and the battery are more than two diode drops apart. The current is limited by the PTC resistor.

In this fashion each battery in the stack is connected to the auxiliary cell and the batteries in the stack will be balanced.

An internal clamp circuit protects the LTC3305 when the voltage difference between the battery being balanced and the auxiliary cell is greater than 1V. With a 13.2V difference, the clamp draws 475µA of current. In the worst case scenario, a 16V difference may appear between the auxiliary cell and a battery. The internal clamp draws 600µA of current in this scenario.

In the state when both the top and bottom side switches are turned on, the PTCFLT pin will be pulled low if the voltage difference between the battery being balanced and the auxiliary cell is greater than 1V. If during the balancing operation the voltage difference becomes less than 1V, the PTCFLT pin returns to its high impedance state.

The BATX and BATY pins indicate which battery in the stack is currently connected to the auxiliary cell as shown in Table 3. In shutdown, the BATX and BATY pins are in a High Z state and the BAL pin is also in a High Z state.

Table 3. State of BATX and BATY Pins STATE OF OPERATION BATX BATY

Battery 1 Connected High Z High Z

Battery 2 Connected High Z 0

Battery 3 Connected 0 0

Battery 4 Connected 0 High Z

Once all batteries in the stack are balanced the DONE pin is pulled low, the BAL pin is in its high impedance state and the part is put in a low power OFF state.

A four-battery stack is deemed balanced when the ter-mination sense comparator detects VTERMINATE on five consecutive cycles that connect each of the batteries to the auxiliary cell using the bottom switches only.


LTC3305

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In timer mode, a capacitor at the CTON pin programs the maximum time, tON, that the balancing operation can run for. The balancing operation is terminated either when the batteries in the stack are deemed to be balanced or a tON time out occurs. After the balancing operation has been terminated, the LTC3305 is put in a low power OFF state for a fixed time, tOFF. The tOFF time is programmed by a capacitor at the CTOFF pin. In the OFF state, the BAL pin is put in its high impedance state. Once tOFF times out, the LTC3305 is put back in its ON state and the balancing operation begins again. The tON timer may be defeated by tying the CTON pin to GND. In this scenario, the LTC3305 will enter the OFF state only when all the batteries in the stack are deemed to be balanced.

Continuous Mode (MODE = 1)

In the continuous mode of operation the part functions in much the same way as in timer mode with the following differences.

1. There is no ON or OFF state. The CTON and CTOFF pins must be tied to GND in continuous mode. The balanc-ing operation continues even if the stack is in balance. The balancing operation is terminated only if the part is put in shutdown. The BAL pin is always pulled low in continuous mode.

2. In timer mode, if the termination comparator senses that a battery is balanced to the auxiliary cell with only the bottom plates connected, the balancing operation on that battery is terminated. This is not the case in continuous mode. In continuous mode the top switches are turned on and the balancing operation on a battery is terminated only by a tBAT time out. Since the auxiliary cell remains connected to the battery until a tBAT time out occurs, its voltage can change before it connects to the next battery in the stack. As a result, when the stack is balanced and the DONE pin is pulled low, the voltages across the individual batteries in the stack may differ by more than the programmed VTERMINATE. In the worst case when the capacity of the auxiliary cell is much smaller than the battery, the individual battery

OPERATIONvoltages could differ by up to twice the programmed VTERMINATE when balanced.

Charge Pump Operation

The LTC3305 uses external NMOS devices as switches to connect a battery to the auxiliary cell. The LTC3305 has a charge pump that generates the higher voltage required to turn on some of the external NMOS switches.

Two external capacitors CFLY and CBOOST, two diodes D1 and D2, and resistors R1 and R2 are required for charge pump operation as shown in Figure 2. When the LTC3305 is enabled, the charge pump is turned on. CFLY initially charges with a current ICHG through external diode D1, resistor R1, and the internal NMOS switch N1 to GND. When CFLY is charged to 10.5V, an internal comparator switches the internal NMOS switch off and turns on switch P1. CFLY connects to CBOOST through diode D2, resistor R2 and the internal PMOS switch P1. Charge is transferred from CFLY to CBOOST with a current IDISCHG. When CFLY is discharged to 9.5V, it is disconnected from CBOOST, recharged back up to 10.5V, and then reconnected to CBOOST. In this fashion the voltage across CBOOST is built up.

Figure 2. Charge Pump Operation

ICHG

R1

R2

D1

D2

V4

P1

N1BOOST

CBOOST

3305 F02

CFLY

CM CP

IDISCHG

LTC3305


LTC3305

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OPERATIONOnce the CBOOST capacitor has 6.95V across it, balancing begins. When CBOOST is charged to 8.45V, the charge pump operation is disabled and CFLY remains connected to CBOOST. Charge pump operation resumes when CBOOST discharges to 8.25V.

Undervoltage and Overvoltage Fault Detection

The undervoltage and overvoltage thresholds can be programmed using the resistor at the ISET pin in con-junction with resistors at the VL and VH pins. The voltage present at the VL or VH pin programs the corresponding fault threshold to 10× that voltage for each battery in the stack. An internal amplifier accurately gains up the voltage at the VL and VH pins and shifts the threshold voltage to the appropriate battery common mode level. The VL and VH pins have a programming range from 0.4V to 1.6V. The internal undervoltage and overvoltage comparators may not trip correctly for a program voltage outside this range. An internal clamp prevents the thresholds from being programmed to greater than 20V.

When an undervoltage or overvoltage fault condition is detected, the corresponding UVFLT or OVFLT pin is pulled to GND. The balancing operation is not interrupted during this time. If an undervoltage or overvoltage fault condition goes away during the balancing operation, the correspond-ing fault pin returns to its high impedance state.

If the undervoltage and overvoltage fault detection is not needed, the VL and VH pins must be tied to GND. The UVFLT and OVFLT pins may either be tied to GND or left floating.

Low Voltage Regulator

The LTC3305 has an always on regulator that provides 2.5V at the VREG pin. The VREG pin may be driven externally up to 5.5V. The VREG pin cannot sink current and will not pull down an externally applied voltage. The regulator can source up to 3mA of current. If more than 3mA of current

is drawn from the regulator, the VREG voltage will drop below its undervoltage threshold, disabling the LTC3305 and terminating the balancing operation. The balancing operation restarts when the regulator recovers from its undervoltage state. In short circuit, the VREG current is limited to 15mA. The VREG pin should be decoupled with at least a 1µF capacitor to GND.

Thermal Shutdown

The LTC3305 has an overtemperature detect circuit that shuts down the balancing operation when the internal silicon junction temperature exceeds 155°C. The LTC3305 resumes balancing when the temperature drops to 145°C. In thermal shutdown, the low voltage regulator remains powered.

Balancing Battery Stacks with Two or Three Batteries

The LTC3305 can also be configured to balance battery stacks of two or three batteries. The state of the enable pins tells the LTC3305 to select the correct switch sequencing. For a two battery stack, the LTC3305 must be enabled with EN1 = 0 and EN2 = 1. For a three battery stack, the LTC3305 must be enabled with EN1 = 1 and EN2 = 0. The external NMOS switch arrangements for a two-battery and three-battery application are shown in Figures 3 and 4 respectively. If pin NGATE6 is unused, it must be con-nected to the BOOST pin. All other unused NGATE pins must be connected to V4 as shown in Figures 3 and 4.

A two battery stack is deemed balanced if the termination sense comparator senses the voltage difference between the auxiliary cell and the battery is less than VTERMINATE on three successive cycles when the auxiliary cell and a battery are connected using only the bottom switches.

In the case of a three battery stack, four successive cycles are required to deem the stack balanced.


LTC3305

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Figure 3. Two-Battery Application Showing External Switch Arrangement

4

4

BAT2

22µF25V

10µF25V

249Ω 1.33k

6.04k

10µF25V

10µF25V

10µF25V

6.04k

6.04k

6.04k

D2

D1

BAT1

3305 F03

AUX

AUXP

LTC3305

NGATE5, 7, 8, 9

NGATE1-4

NGATE6

BOOST

V1

V2

V3

V4

AUXN

GND

PTC

+

VREGEN1

EN2MODE

TERM1TERM2

DONE

BATXBATYCTON

CTOFF

CTBAT

VL

VH

ISET

UVFLTOVFLT

BALPTCFLT

10nF

100k EACH

100nF

22nF

27.4k

42.2k

12.1k

1µF6V

+

+

NGATE5

ALL NMOS DEVICES = SiR882DPD1, D2 = CMMSH1-100

CM CP

NGATE7

NGATE8

NGATE9

OPERATION


LTC3305

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Figure 4. Three-Battery Application Showing External Switch Arrangement

10µF25V

10µF25V

10µF25V

10µF25V

10µF25V

249Ω

D1

D2

6.04k

6.04k

6.04k

6.04k6.04k

6.04k

6.04k

6.04k

1.33k

3305 F04

AUXP

LTC3305

NGATE1, 2, 4-9

BOOST

V1

V2

V4

V3NGATE3

AUXNGND

VREGEN1EN2

MODE

TERM1TERM2

DONE

BATXBATYCTON

CTOFF

CTBAT

VL

VH

ISET

UVFLTOVFLT

BALPTCFLT

1µF6V

CM CP

8

BAT2

BAT3+

+

+BAT1

AUX+PTC

10nF

100k EACH

100nF

22nF

10µF25V

27.4k

42.2k

12.1k

NGATE6

NGATE8

NGATE7

NGATE9

NGATE1

NGATE2

NGATE4

NGATE5

ALL NMOS SWITCHES = SiR882DPD1, D2 = CMMSH1-100

OPERATION


LTC3305

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Selecting the PTC Thermistor

A PTC thermistor is a type of resistor with a Positive Tem-perature Coefficient that serves as a protection device by limiting its current above a certain threshold. The PTC device limits the peak current that transfers charge between the auxiliary cell and the battery. When the voltage across the PTC is small, the power dissipated in the PTC is small and the PTC resistance remains constant. As the voltage across the PTC increases, power dissipation in the PTC increases which causes the PTC temperature to rise. When the tem-perature reaches the Curie Temperature, further increases in voltage will cause the PTC resistance to increase rapidly, which limits the current through the device and thus limits the power dissipation in the PTC. This behavior is shown in the PTC Current Voltage Characteristics in Figure 5a. In this fashion the PTC serves to protect the external NMOS switches from operating outside of their SOA region.

As seen in the PTC Current Voltage Characteristics in Figure 5a, when the PTC has a small voltage or a high voltage across it, the current flowing through it is small. For small voltages, this is OK since the battery and the auxiliary cell are close to balance. For high voltages, this slows down balancing. To increase balance currents at high voltages a power resistor can be placed in parallel with the PTC device, as shown in Figure 5b. Additionally, multiple PTC resistors may be connected in parallel to increase current flow at all voltages.

PTC devices are manufactured in two styles: ceramic and poly fuse. Only a ceramic style PTC device should be used in this application. Poly fuse devices have a very limited number of lifetime trip cycles and are not suitable in a balancing application.

The PTC must be selected such that power dissipation through the external NMOS switches never exceeds their rated SOA power dissipation value. Refer to Table 4 for a list of recommended PTC thermistors.

APPLICATIONS INFORMATION

Table 4. Recommended Ceramic PTC Thermistors

PART NUMBER MANUFACTURER VOLTAGERESISTANCE

(Ω)

PTGL7SARR47M1B51B0 Murata 16V 0.47

PTGLASARR27M1B51B0 Murata 16V 0.27

PTGLESARR15M1B51B0 Murata 16V 0.15

PTGL12AR1R2H2B51B0 Murata 30V 1.2

2381 663 51121 Vishay 30V 0.7

2381 663 51321 Vishay 30V 0.5

2381 664 52021 Vishay 30V 0.3

VOLTAGE →

CURR

ENT

→

3305 F05a

CURIE POINT

VOLTAGE →

CURR

ENT

→

3305 F05b

PTC RESISTOR IN PARALLEL WITH A RESISTOR

SINGLE PTC RESISTOR

RESISTOR ONLY

PTC Current Voltage Characteristics

Increasing Current at Large Voltage

Figure 5. PTC Behavior

(a)

(b)


LTC3305

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APPLICATIONS INFORMATIONSelecting the Auxiliary Cell

The auxiliary cell must be capable of sourcing and sink-ing current and withstand the maximum voltage of any individual battery in the stack. The ESR of the auxiliary cell must be small compared to the PTC thermistor. Any voltage dropped across the auxiliary cell ESR appears as an offset voltage at the input of the termination comparator.

The auxiliary cell used may be a lead-acid battery, a stacked supercapacitor, or a low leakage, high voltage capacitor. When using a supercapacitor stack, the voltage across each individual supercapacitor must not exceed its rated operating voltage.

Figure 6a shows a battery stack made of 4 batteries, each with a nominal capacity of 50Ah, but with a 10% capacity mismatch. With no balancing, the stack capacity is determined by the weakest battery in the stack and is limited to 45Ah.

In Figure 6b, a small capacity auxiliary cell, such as a supercapacitor stack, is used to balance the battery stack. When balanced the stack capacity can be made to approach the nominal capacity of 50Ah despite the 10% mismatch.

In Figure 6c, the auxiliary cell has the same capacity as the batteries in the stack. Each of the batteries in Figure 6c has a nominal capacity of only 40Ah but the stack capac-ity approaches 50Ah since the auxiliary cell supplements

the capacity of the battery stack. Using a large capacity auxiliary cell supplements stack capacity. Smaller capac-ity batteries may be used in the stack which helps reduce system costs.

Precharging the Auxiliary Cell

When using stacked supercapacitors or a single high volt-age capacitor as the auxiliary cell, the auxiliary cell may be initially discharged with a voltage of 0V. At startup, a large voltage exists across the PTC resistor, which will cause the PTC resistance to increase. This limits the cur-rent and hence the charge transfer between the auxiliary cell and the battery it is connected to. The auxiliary cell will be charged very slowly with an indeterminate time, as it sequentially connects to each battery in the stack. Once the auxiliary cell has been charged to a point where the PTC device operates as a low resistance device, the balancing process is sped up.

A more time efficient solution is to precharge the auxiliary cell to the average voltage of the batteries in the stack. Figure 7a shows a circuit using a high voltage buck regulator to precharge the auxiliary cell to V4/4 volts. NMOS devices N2A and N2B eliminate a parasitic charging path from BATTERY1 to the auxiliary cell when AUXN is connected to GND through N10. Figures 7b and 7c are scope photos showing a complete precharging and balancing operation.

55Ah(+10%)

50Ah

45Ah(–10%)

STACK CAPACITY=45Ah

(a)

STACK CAPACITY≈50Ah

(b)

50Ah

55Ah(+10%)

50Ah

45Ah(–10%)

4Ah(AUX)

50Ah

PTC

STACK CAPACITY≈50Ah

(c)

44Ah(+10%)

40Ah

36Ah(–10%)

40Ah(AUX)

40Ah

PTC

Figure 6. Increasing Stack Capacity with an Auxiliary Cell


LTC3305

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Figure 7. Precharging the Auxiliary Cell Using the LTC3630A and LTC1440

BAT1, BAT2, BAT3, BAT4, AUXP-AUXN = 2V/DIVAUXN = 10V/DIV; START, EN_3305 = 5V/DIV

TIME = 20s/DIV

AUXP-AUXN = 2V/DIVAUXN = 10V/DIV; START, EN_3305 = 5V/DIV

TIME = 5s/DIV

(a)

VREG

EN1EN2

TERM2MODE

TERM1

DONE

BATXBATYCTON

CTOFF

CTBAT

VL

VH

GND

LTC3305

AUXN

AUXP

V1

V2

V3

V4

CM

10µF25V

10µF25V

1µF6V

1.33k

249Ω

6.04k

6.04k

D1, D2 = CMMSH1-100D3 = CMMSH2-80

N1A, N1B, N2, N3A, N3B, N4, N5, N6, N7, N8, N9, N10 - SiR882DP

CPBOOST

D1

D2

NGATE1-9

ISET

UVFLTOVFLT

BALPTCFLT

10µF25V

10µF25V

10µF25V

100µH

10µF25V

9

V+

V–

VIN

NGATE5

N5

NGATE6

NGATE7

NGATE8

NGATE9

N10N11

N9

N8

N7

N6

N11, N12 = FDV301N

3305 F07

PTC

AUX

12.1k

42.2k

27.4k

10nF

10nF

100nF

10µF25V

NGATE4

3.01k

6.04k

174k

6.04k

N2A N2B

N3A

N4

N3B

6.04k

6.04k

6.04k

6.04k

NGATE3

NGATE2

NGATE1

BAT4+

+

+

+

BAT3

IN– OUTREF

HYST

GND

LTC1440

IN+

5.11M D4, D5, D6 = 1N914

D3

D4

D5

D6

365k

BAT2

BAT1

SW

SSFBO ISET

VPROG1VPROG2

LTC3630A

GNDFB

RUN

S

RQ

QD

CLKSTART

+

2.2µF100V

N12

2.21M

365k2.21M

681k

40.2k

2.43M

N1

(b) (c)


LTC3305

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APPLICATIONS INFORMATIONSelection of External NMOS Switches

The external NMOS switches must be capable of with-standing a reverse voltage equal to the battery stack volt-age. They should also be capable of carrying DC current up to the PTC thermistor trip point. The maximum power dissipated in the NMOS should not cause it to operate outside of its Safe Operating Area. Refer to Table 5 for a list of recommended NMOS switches.

Programming NMOS Turn On

The NMOS switches are turned on by developing a voltage across an external resistor from the gate to the source. The current through the resistor is delivered from the NGATE pins and is programmed by the current at the ISET pin. The internal current sources that provide the NGATE pin currents operate from the V4 and BOOST supplies as shown in the Block Diagram. The BOOST pin voltage is regulated at 8.45V greater than V4. It is recommended that the gate turn on voltage be set to no more than 7.5V. The current flowing through the gate turn on resistor connected to the NGATE3 pin is given by:

INGATE3 =

26.4VRISET

The current flowing through the other NGATE pins is given by:

INGATE =13.2VRISET

The NGATE3 current has a programmed range from 1mA to 3mA. All other NGATE currents have a programmed range from 500µA to 1.5mA.

The NGATE current initially charges the gate capacitor of the NMOS device to turn it on. The external gate source resistor maintains a constant gate to source voltage on

the NMOS device. Programming a higher current reduces the NMOS device turn on time. Programming a large gate source voltage reduces the on resistance of the NMOS device. During turn off, the gate capacitor discharges through the gate source resistor.

Programming Undervoltage and Overvoltage Thresholds

Referring to the Block Diagram, the voltage at the ISET pin is servoed to 1.2V. An external resistor, RISET, from this pin to GND programs a current which is divided down and mirrored to the VL and VH pins. The ISET pin current has a programmed range from 50µA to 150µA.

The ISET pin current is given by:

IISET =

1.2VRISET

The current out of the VL and VH pins is given by:

IVL = IVH = IISET

3 External resistors RVL from the VL pin to GND and RVH from the VH pin to GND program the undervoltage and overvoltage thresholds for each battery. The undervolt-age threshold for a battery is given by:

VBAT,UV = 4V • RVL

RISET The overvoltage threshold for a battery is given by:

VBAT,OV = 4V • RVH

RISET Programming the tBAT Parameter

The tBAT parameter is programmed using a capacitor from the CTBAT pin to GND. tBAT is given by:

tBAT = 5sec• CTBAT

10nF A C0G type capacitor is recommended due to its superior temperature characteristics.

Programming the tON and tOFF Parameters

The tON parameter is programmed by a capacitor from the CTON pin to GND. tON is given by:

tON = 0.48hrs• CTON

10nF

Table 5. Recommended NMOS Switches PART NUMBER MANUFACTURER IDS(MAX) VDC(MAX)

SiR882DP Vishay 60A 100V

SiS892DN Vishay 25A 100V

IPD70N10S3-12 Infineon 70A 100V

IPB35N10S3L-26 Infineon 35A 100V

RJK1051DPB Renesas 60A 100V

RJK1054DPB Renesas 92A 100V


LTC3305

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APPLICATIONS INFORMATIONThe tOFF parameter is programmed by a capacitor from the CTOFF pin to GND. tOFF is given by:

tOFF = 0.48hrs• CTOFF

10nF

C0G type capacitors are recommended due to their superior temperature characteristics.

In the continuous operation mode (MODE = 1), the CTON and CTOFF pins are unused and should be connected to GND.

Selecting Charge Pump Components

Referring to Figure 2, recommended values for R1, R2 and CFLY are 249Ω, 1.33k & 10µF respectively for all ap-plications. For applications in which V4 is no lower than 32V a 10µF capacitor is recommended for CBOOST. For applications which may have lower voltages at V4, the recommended value for CBOOST is 22µF. Schottky diodes with a breakdown voltage larger than the maximum V4 voltage are recommended for diodes D1 and D2.

Selecting Decoupling Capacitors

Decoupling capacitors of at least 10µF must be placed across each battery, from the BOOST pin to V4 and from the AUXP pin to the AUXN pin. These capacitors must be placed as close as possible to the LTC3305. The capacitors must be capable of withstanding the maximum voltage across each battery. Capacitors with an X5R or X7R type dielectric should be used.

Thermal Considerations and Limiting On-Chip Power Dissipation

Excessive on-chip power dissipation will cause the LTC3305 to enter thermal shutdown. It is important to understand the source of the power dissipation and how power dissipation can be reduced. The two contributions of on-chip power dissipation on the LTC3305 that may be controlled by the user are the loading on the low voltage regulator and the power dissipated through the current sources that provide the NGATE pin currents.

The low voltage linear regulator provides a 2.5V output. Any current provided by the regulator will cause power

dissipation in the internal switch connected from V4 to VREG, which causes die temperature to increase. In Figure 8, an external switching regulator generates a 3.3V rail that back drives the VREG pin and provides power to the external microprocessor and other low voltage circuits. There is no on-chip loading on the VREG pin and thus no on chip power dissipation in the low voltage regulator.

In Figure 8, external resistors R1, R2, R3, R4, and R5 are in series with the on-chip current sources that provide NGATE pin current. These resistors reduce the voltage across the on-chip current sources and thus reduce on-chip power dissipation. As an example, the current source at NGATE1 delivers current from the V4 pin. When this current source is turned on, the voltage across it is V4-VNGATE1. For a typical application with V4 = 52.8V, programmed INGATE = 506µA and VNGATE1 = 6.12V, the on-chip power dissipated in the current source is 23mW. In Figure 8, resistor R1 operates with approximately 30.5V across it. The on-chip power dissipated in the current source is reduced to ap-proximately 8mW. In similar fashion resistors R2, R3, R4, and R5 reduce the on-chip power dissipation on the respective current sources. When choosing these resistors it is recommended to have the internal current sources biased with at least 6V across them under all operating conditions. Power dissipation through the on-chip current sources may be further reduced by programming a lower gate current through the NGATE pins.

Balancing Battery Stacks with more than Four Batteries

To balance battery stacks that have more than four batter-ies, multiple LTC3305 devices may be stacked together. In this scenario, it is recommended that each LTC3305 be run in continuous mode and at least one battery in each sub-stack of four is common to two LTC3305s. Each LTC3305 needs an auxiliary cell for the balancing opera-tion. Figure 9 shows an eight battery stack being balanced using three LTC3305 devices connected together. Figure 10 shows a stack of six batteries being balanced using two LTC3305 devices. To balance a battery stack with n batteries, the minimum number of LTC3305 devices required is [(n-1)/3] rounded up to the nearest integer. In this calculation, each LTC3305 is assumed to be used in a four-battery configuration and at least one battery interleaves two LTC3305 devices.


LTC3305

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Figure 8. 4-Battery Application with External Resistors to Limit Power Dissipation

VREGEN1EN2

TERM2

MODETERM1

DONE

BATXBATY

CTON

CTOFF

CTBAT

VL

VH

GND

LTC3305

AUXN

AUXP

V1

V2

V3

V4

CM

10µF25V

10µF25V

1.33k

249Ω

12.1k

12.1k

CPBOOST

D1

D2

NGATE1-9

ISET

UVFLTOVFLT

BALPTCFLT

10µF25V

10µF25V

10µF25V

10µF25V

10µF25V

9

ALL NMOS SWITCHES = SiR882DPD1, D2 = CMMSH1-100

3.3V

100k EACH

LTC3630ABUCK REGULATOR

MICROPROCESSOR

NGATE5

NGATE6

NGATE7

NGATE8

NGATE9 3305 F08

PTC = PTGL13AROR8H2B71B0

AUX

23.7k

93.1k

59k

10nF

100nF

10nF

NGATE4

6.04k

12.1k

12.1k12.1k

12.1k

12.1k

12.1k

12.1k

R4

20k

R5

NGATE3

NGATE2

NGATE1

BAT4

BAT3

10k

R3

37.4k

R2

R1

60.4k

BAT2

BAT1

+

+

+

+

+

When multiple LTC3305 devices are stacked, the logic out-put pins may need to be level shifted and ground referred. In Figure 9, optical isolators are used for level shifting.

Figure 11 shows an application in which an eight battery stack is balanced using two LTC3305 devices and two auxiliary cells. BAT1, BAT2, BAT3, and BAT4 are balanced to each other using the lower LTC3305 whereas BAT5, BAT6, BAT7, and BAT8 are balanced to each other by the upper LTC3305.

PCB Considerations

In operation the LTC3305 can dissipate large amounts of power which can increase die temperature and cause the part to enter thermal shutdown. The exposed pad of LTC3305 must be well soldered to the PCB to provide adequate heat sinking. The exposed pad also provides an electrical GND to the LTC3305.

The no-connect pin on the LTC3305 must be soldered to a pad on the PCB and must be electrically isolated from any other circuit node.

The trace that connects the AUXP pin to the positive terminal of the auxiliary source must be as close to the auxiliary source positive terminal as possible. Otherwise the trace impedance adds to the ESR of the auxiliary cell which manifests itself as an offset at the internal termina-tion comparator.

The V1, V2, V3 and V4 traces must be Kelvin connected directly to the battery terminal and must not share a com-mon trace through which high balance current will flow. Any voltage drop in these traces also manifests itself as an offset voltage at the termination comparator input.


LTC3305

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Figure 9. Three LTC3305 Devices Connected to Balance Eight Lead-Acid Batteries

3305 F07

VREG

EN1EN2MODETERM1TERM2

DONE

BATXBATY

CTON

CTOFF

CTBAT

VL

VH

GND

LTC3305

AUXN

AUXP

V1

V2

V3

V4

CM

10µF25V

10µF25V

5.49k

5.49k

CP

BOOST

NGATE1-9NGATE1C-9C

ISET

UVFLTOVFLT

BALPTCFLT

10µF25V

10µF25V

10µF25V

10µF25V

9

NGATE5C

NGATE6C

NGATE7C

NGATE8C

NGATE9C

PTC

AUX3

20k

32.4k

8.06k

10nF

NGATE4C

D5

249Ω 1.33k

D6

+

+

+

+

+

+

+

+

2.74k

5.49k5.49k

5.49k

5.49k

5.49k

NGATE3C

NGATE2C

NGATE1C

BAT8

BAT7

5.49kBAT6

BAT5

BAT4

BAT3

BAT2

BAT1

1µF6V

2.43k

CPC1301G

CPC1301G

TOµP

2.43k 2.43k 2.43k 2.43k 2.43k 2.43k

100k 100k 100k 100k 100k 100k 100k

VREG


DONE

BATXBATY

CTON

CTOFF

CTBAT

VL

VH

GND

LTC3305

AUXN

AUXP

V1

V2

V3

V4

CM

10µF25V

10µF25V

5.49k

5.49k

CP

BOOST

NGATE1-9NGATE1A-9A

ISET

UVFLTOVFLT

BALPTCFLT

10µF25V

10µF25V

10µF25V

10µF25V

9

NGATE5A

NGATE6A

NGATE7A

NGATE8A

NGATE9A

PTC

AUX1

8.06k

10nF

NGATE4A

2.74k

5.49k5.49k

5.49k

5.49k

5.49k

NGATE3A

NGATE2A

NGATE1A

5.49k

1µF6V

3.3V

VREG


DONE

BATXBATY

CTON

CTOFF

CTBAT

VL

VH

GND

LTC3305

AUXN

AUXP

V1

V2

V3

V4

CM

10µF25V

10µF25V

5.49k

5.49k

CP

BOOST

NGATE1-9NGATE1B-9B

ISET

UVFLTOVFLT

BALPTCFLT

10µF25V

10µF25V

10µF25V

10µF25V

9

NGATE5B

NGATE6B

NGATE7B

NGATE8B

NGATE9B

PTC

AUX2

20k

32.4k

8.06k

10nF

NGATE4B

2.74k

5.49k5.49k

5.49k

5.49k

5.49k

NGATE3B

NGATE2B

NGATE1B

5.49k

1µF6V

32.4k

20k

D3

D4

D1

D2

+

TOµP

100k 100k 100k 100k 100k 100k 100k

2.43k 2.43k 2.43k 2.43k 2.43k 2.43k 2.43k

TOµP

100k 100k 100k 100k 100k 100k 100k

249Ω 1.33k

249Ω 1.33k

ALL NMOS DEVICES = SiR882DPD1, D2, D3, D4, D5, D6 = CMMSH1-100

10µF25V

10µF25V

10µF25V

+

+


LTC3305

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Figure 10. Two LTC3305 Devices Connected to Balance Six Lead-Acid Batteries with AND’d DONE Indicator

VREGEN1EN2

TERM2

MODETERM1

DONE

BATXBATY

CTON

CTOFF

CTBAT

VL

VH

GND

LTC3305

AUXN

AUXP

V1

V2

V3

V4

CM

10µF25V

10µF25V

1.33k

6.04k

6.04k

ALL NMOS DEVICES = SiR882DPD1, D2, D3, D4 = CMMSH1-100

CP

BOOSTD3

249Ω

D4

NGATE1-9

ISET

UVFLTOVFLT

BALPTCFLT

10µF25V

10µF25V

10µF25V

10µF25V

NGATE5B

NGATE6B

NGATE7BNGATE1B-9B

NGATE8BNGATE1B

NGATE9B

3305 F08

PTC

AUX2

27.4k

10nF

10µF25V

42.2k

12.1k

NGATE4B

3.01k

6.04k

6.04k

9

6.04k

6.04k

6.04k

NGATE3B

NGATE2B BAT5

475k

1µF6V

10µF25V

475k

475Ω

6.04k

BAT6+

+

+

+

+

+

+

+

BAT4

BAT3VREGEN1EN2

TERM2

MODETERM1

DONE

BATXBATY

CTON

CTOFF

CTBAT

VL

VH

GND

LTC3305

AUXN

AUXP

V1

V2

V3

V4

CM

10µF25V

10µF25V

1.33k249Ω

6.04k

6.04k

CP

BOOSTD1

D2

NGATE1-9

ISET

UVFLTOVFLT

BALPTCFLT

10µF25V

10µF25V

10µF25V

10µF25V

NGATE5A

NGATE6A

NGATE7ANGATE1A-9A

NGATE8ANGATE1A

NGATE9A

PTC

9

AUX1

27.4k

10nF

42.2k

12.1k

NGATE4A

3.01k

6.04k

6.04k

6.04k

6.04k

6.04k

NGATE3A

NGATE2A BAT2

1µF6V

6.04k

BAT1


LTC3305

253305fb



100k

10nF

12.1k

VREGEN1EN2

TERM2

MODETERM1

DONE

BATXBATY

CTON

CTOFF

CTBAT

VL

VH

GND

LTC3305

AUXN

AUXP

V1

V2

V3

V4

CM CPBOOST

ISET

UVFLTOVFLT

BALPTCFLT

249Ω

10µF25V

10µF25V

10µF25V

10µF25V

10µF25V

10µF25V

10µF25V

D3

D4

1.33k

1µF6V

NGATE1-99

NGATE1B-9B

PTC

AUX2+

10µF25V

NGATE6B

NGATE7B

NGATE8B

NGATE9B

ALL NMOSDEVICES = SiR892DPD1, D2, D3, D4 = CMMSH1-100

6.04k

6.04k

6.04k

6.04k

NGATE5B6.04k

BAT8+

+

+

+

+

+

+

+

+

BAT7

BAT6

BAT5

NGATE4B6.04k

NGATE2B6.04k

NGATE1B6.04k

NGATE3B3.01k

100k

10nF

12.1k

VREGEN1EN2

TERM2

MODETERM1

DONE

BATXBATY

CTON

CTOFF

CTBAT

VL

VH

GND

LTC3305

AUXN

AUXP

V1

V2

V3

V4

CM CPBOOST

ISET

UVFLTOVFLT

BALPTCFLT

249Ω

10µF25V

10µF25V

10µF25V

10µF25V

10µF25V

D1

D2

1.33k

1µF6V

NGATE1-99

NGATE1A-9A

PTC

AUX1

3305 F11

NGATE6A

NGATE7A

NGATE8A

NGATE9A

6.04k

6.04k

6.04k

6.04k

NGATE5A6.04k

BAT4

BAT3

BAT2

BAT1

NGATE4A6.04k

NGATE2A6.04k

NGATE1A6.04k

NGATE3A3.01k

10µF25V

Figure 11. Eight Battery Balancer Using Two LTC3305 Devices


LTC3305

263305fb


PACKAGE DESCRIPTIONPlease refer to http://www.linear.com/product/LTC3305#packaging for the most recent package drawings.

4.75(.187)

REF

FE38 (AA) TSSOP REV C 0910

0.09 – 0.20(.0035 – .0079)

0° – 8°

0.25REF

0.50 – 0.75(.020 – .030)

4.30 – 4.50*(.169 – .177)

1 19

20

REF

9.60 – 9.80*(.378 – .386)

38

1.20(.047)MAX

0.05 – 0.15(.002 – .006)

0.50(.0196)

BSC0.17 – 0.27

(.0067 – .0106)TYP

RECOMMENDED SOLDER PAD LAYOUT

0.315 ±0.05

0.50 BSC

4.50 REF

6.60 ±0.10

1.05 ±0.10

4.75 REF

2.74 REF

2.74(.108)

MILLIMETERS(INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.150mm (.006") PER SIDE

NOTE:1. CONTROLLING DIMENSION: MILLIMETERS2. DIMENSIONS ARE IN

3. DRAWING NOT TO SCALE

SEE NOTE 4

4. RECOMMENDED MINIMUM PCB METAL SIZE FOR EXPOSED PAD ATTACHMENT

6.40(.252)BSC

FE Package38-Lead Plastic TSSOP (4.4mm)

(Reference LTC DWG # 05-08-1772 Rev C)Exposed Pad Variation AA


http://www.linear.com/product/LTC3305#packaging

LTC3305

273305fb


Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

REVISION HISTORYREV DATE DESCRIPTION PAGE NUMBER

A 09/15 Added timer mode section.Modified Figure 6 schematic.Modified Figure 8 schematic.Modified Figure 9 schematic.

13162223

B 03/16 Updated Feature bulleted items and descriptionUpdated Application schematicEnhanced Operation section

11

11


LTC3305

283305fb


RELATED PARTS

TYPICAL APPLICATION

PART NUMBER DESCRIPTION COMMENTS

LTC3300-1 LTC3300-2

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LTC4020 55V Buck-Boost Multi-Chemistry Battery Charger Capable of Charging 4 Lead-Acid Batteries up to 55V

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LTC3630A High Efficiency, 65V 500mA Synchronous Step Down Converter

Efficiently Generates a Low Voltage Rail. Synchronous Operation for high Efficiency

LTC2946 Wide Range I2C Power, Charge and Energy Monitor Measures Current, Voltage, Power, Charge and Energy in a Battery Stack up to 100V

VREGEN1EN2

TERM2

MODETERM1

DONE

BATXBATY

CTON

CTOFF

CTBAT

VL

VH

GND

LTC3305

AUXN

AUXP

V1

V2

V3

V4

CM

10µF25V

10µF25V

1.33k249Ω6.04k

6.04k

D1, D2 = CMMSH1-100

CP

BOOST

D1

D2

NGATE1-9

ISET

UVFLTOVFLT

BALPTCFLT

10µF25V

10µF25V

10µF25V

10µF25V

10µF25V

9

1µF6V

NGATE5

NGATE6

NGATE7

NGATE8

NGATE9 3305 TA02

PTC

AUX

12.1k

10nF

NGATE4

3.01k

6.04k

6.04k

6.04k

6.04k

6.04k

6.04k

NGATE3

NGATE2

NGATE1

ALL NMOSDEVICES = SiR882DP

BAT4+

+

+

+

BAT3

BAT2

BAT1

100Ω

+

A Minimum Component Application in Which an LED is Used to Display Status

LT 0316 REV B • PRINTED IN USALinear Technology Corporation1630 McCarthy Blvd., Milpitas, CA 95035-7417(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC3305 LINEAR TECHNOLOGY CORPORATION 2015


http://www.linear.com/LTC3300-1

http://www.linear.com/LTC3300-2

http://www.linear.com/LT8584




http://www.linear.com/LTC3630A



Documents

LTC3305 - Lead-Acid Battery Balancer€¦ · Lead-Acid Battery Balancer The LTC®3305 balances up to 4 lead-acid batteries connected in series. It is intended to be used in conjunction