LTC2242-12 - 12-Bit, 250Msps ADC - analog.com · VID Differential Input Voltage (Note 7) 0.2 V VICM Common Mode Input Voltage Internally Set Externally Set (Note 7) ... V DD Analog

LTC2242-12

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TYPICAL APPLICATION

FEATURES

APPLICATIONS

DESCRIPTION

12-Bit, 250Msps ADC

The LTC®2242-12 is a 250Msps, sampling 12-bit A/D con-verter designed for digitizing high frequency, wide dynamic range signals. The LTC2242-12 is perfect for demanding communications applications with AC performance that includes 65.4dB SNR and 78dB SFDR. Ultralow jitter of 95fsRMS allows IF undersampling with excellent noise performance.

DC specs include ±1.0LSB INL (typ), ±0.4LSB DNL (typ) and no missing codes over temperature.

The digital outputs can be either differential LVDS, or single-ended CMOS. There are three format options for the CMOS outputs: a single bus running at the full data rate or two demultiplexed buses running at half data rate with either interleaved or simultaneous update. A separate output power supply allows the CMOS output swing to range from 0.5V to 2.625V.

The ENC+ and ENC– inputs may be driven differentially or single ended with a sine wave, PECL, LVDS, TTL, or CMOS inputs. An optional clock duty cycle stabilizer allows high performance over a wide range of clock duty cycles.

SFDR vs Input Frequency

n Sample Rate: 250Mspsn 65.4dB SNRn 78dB SFDRn 1.2GHz Full Power Bandwidth S/Hn Single 2.5V Supplyn Low Power Dissipation: 740mWn LVDS, CMOS, or Demultiplexed CMOS Outputsn Selectable Input Ranges: ±0.5V or ±1Vn No Missing Codesn Optional Clock Duty Cycle Stabilizern Shutdown and Nap Modesn Data Ready Output Clockn Pin Compatible Family 250Msps: LTC2242-12 (12-Bit), LTC2242-10 (10-Bit) 210Msps: LTC2241-12 (12-Bit), LTC2241-10 (10-Bit) 170Msps: LTC2240-12 (12-Bit), LTC2240-10 (10-Bit) 185Msps: LTC2220-1 (12-Bit)* 170Msps: LTC2220 (12-Bit), LTC2230 (10-Bit)* 135Msps: LTC2221 (12-Bit), LTC2231 (10-Bit)*n 64-Pin 9mm × 9mm QFN Package

n Wireless and Wired Broadband Communicationn Cable Head-End Systemsn Power Amplifi er Linearizationn Communications Test Equipment

–

+INPUT

S/H

CORRECTIONLOGIC

OUTPUTDRIVERS

12-BITPIPELINEDADC CORE

CLOCK/DUTYCYCLE

CONTROL

FLEXIBLEREFERENCE

D11•••

D0

ENCODEINPUT

REFH

REFL

ANALOGINPUT

224212 TA01

CMOSORLVDS

0.5VTO 2.625V

2.5V

VDD

OVDD

OGND

INPUT FREQUENCY (MHz)

0

SFD

R (

dB

FS) 70

80

85

800

224212 G11

60

50

65

75

55

45

40200100 400300 600 700 900500 1000

1V RANGE

2V RANGE

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. *LTC2220-1, LTC2220, LTC2221, LTC2230, LTC2231 are 3.3V parts.

LTC2242-12

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ABSOLUTE MAXIMUM RATINGSSupply Voltage (VDD) ...............................................2.8VDigital Output Ground Voltage (OGND) ........ –0.3V to 1VAnalog Input Voltage (Note 3) .......–0.3V to (VDD + 0.3V)Digital Input Voltage ......................–0.3V to (VDD + 0.3V)Digital Output Voltage ................ –0.3V to (OVDD + 0.3V)

OVDD = VDD (Notes 1, 2)

TOP VIEW

UP PACKAGE64-LEAD (9mm × 9mm) PLASTIC QFN

EXPOSED PAD (PIN 65) IS GND, MUST BE SOLDERED TO PCB

TJMAX = 150°C, θJA = 20°C/W

AIN+ 1

AIN+ 2

AIN– 3

AIN– 4

REFHA 5

REFHA 6

REFLB 7

REFLB 8

REFHB 9

REFHB 10

REFLA 11

REFLA 12

VDD 13

VDD 14

VDD 15

GND 16

48 D9+/DA6

47 D9–/DA5

46 D8+/DA4

45 D8–/DA3

44 D7+/DA2

43 D7–/DA1

42 OVDD

41 OGND

40 D6+/DA0

39 D6–/CLKOUTA

38 D5+/CLKOUTB

37 D5–/OFB

36 CLKOUT+/DB11

35 CLKOUT–/DB10

34 OVDD

33 OGND

64 G

ND

63 V

DD

62 V

DD

61 G

ND

60 V

CM

59 S

EN

SE

58 M

OD

E

57 L

VD

S

56 O

F+/O

FA

55 O

F–/D

A11

54 D

11

+/D

A10

53 D

11

–/D

A9

52 D

10

+/D

A8

51 D

10

–/D

A7

50 O

GN

D

49 O

VD

D

EN

C+ 1

7

EN

C– 1

8

SH

DN

19

OE

20

DO

–/D

B0 2

1

DO

+/D

B1 2

2

D1

–/D

B2 2

3

D1

+/D

B3 2

4

OG

ND

25

OV

DD

26

D2

–/D

B4 2

7

D2

+/D

B5 2

8

D3

–/D

B6 2

9

D3

+/D

B7 3

0

D4

–/D

B8 3

1

D4

+/D

B9 3

265

ORDER INFORMATION

PIN CONFIGURATION

Power Dissipation .............................................1500mWOperating Temperature Range LTC2242C-12 ........................................... 0°C to 70°C LTC2242I-12 ........................................–40°C to 85°CStorage Temperature Range ................... –65°C to 150°C

LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC2242CUP-12#PBF LTC2242CUP-12#TRPBF LTC2242UP-12 64-Lead (9mm × 9mm) Plastic QFN 0°C to 70°C

LTC2242IUP-12#PBF LTC2242IUP-12#TRPBF LTC2242UP-12 64-Lead (9mm × 9mm) Plastic QFN –40°C to 85°C

LEAD BASED FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC2242CUP-12 LTC2242CUP-12#TR LTC2242UP-12 64-Lead (9mm × 9mm) Plastic QFN 0°C to 70°C

LTC2242IUP-12 LTC2242IUP-12#TR LTC2242UP-12 64-Lead (9mm × 9mm) Plastic QFN –40°C to 85°C

Consult LTC Marketing for parts specifi ed with wider operating temperature ranges. *Temperature grades are identifi ed by a label on the shipping container.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifi cations, go to: http://www.linear.com/tapeandreel/

LTC2242-12

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ANALOG INPUT The ● denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 4)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VIN Analog Input Range (AIN+ – AIN

–) 2.375V < VDD < 2.625V (Note 7) ● ±0.5 to ±1 V

VIN, CM Analog Input Common Mode (AIN+ + AIN

–)/2 Differential Input (Note 7) ● 1.2 1.25 1.3 V

IIN Analog Input Leakage Current 0 < AIN+, AIN

– < VDD ● –1 1 μA

ISENSE SENSE Input Leakage 0V < SENSE < 1V ● –1 1 μA

IMODE MODE Pin Pull-Down Current to GND 7 μA

ILVDS LVDS Pin Pull-Down Current to GND 7 μA

tAP Sample and Hold Acquisition Delay Time 0.4 ns

tJITTER Sample and Hold Acquisition Delay Time Jitter 95 fsRMS

Full Power Bandwidth Figure 8 Test Circuit 1200 MHz

DYNAMIC ACCURACY The ● denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. AIN = –1dBFS. (Note 4)


SNR Signal-to-Noise Ratio (Note 10) 10MHz Input 65.4 dB

70MHz Input l 63.4 65.3 dB

140MHz Input 65.3 dB


SFDR Spurious Free Dynamic Range2nd or 3rd Harmonic(Note 11)

10MHz Input 78 dB

70MHz Input l 65 75 dB

140MHz Input 74 dB

240MHz Input 73 dB

Spurious Free Dynamic Range4th Harmonic or Higher(Note 11)

10MHz Input 87 dB

70MHz Input l 73 87 dB

140MHz Input 87 dB

240MHz Input 87 dB

S/(N+D) Signal-to-Noise PlusDistortion Ratio(Note 12)

10MHz Input 65.3 dB

70MHz Input l 61.8 65.1 dB



IMD Intermodulation Distortion fIN1 = 135MHz, fIN2 = 140MHz 81 dBc

CONVERTER CHARACTERISTICS The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 4)

PARAMETER CONDITIONS MIN TYP MAX UNITS

Resolution (No Missing Codes) ● 12 Bits

Integral Linearity Error Differential Analog Input (Note 5) ● –2.7 ±1 2.7 LSB

Differential Linearity Error Differential Analog Input ● –1 ±0.4 1 LSB

Offset Error (Note 6) ● –17 ±5 17 mV

Gain Error External Reference ● –3.2 ±0.7 3.2 %FS

Offset Drift ±10 μV/C

Full-Scale Drift Internal ReferenceExternal Reference

±60±45

ppm/Cppm/C

Transition Noise SENSE = 1V 0.74 LSBRMS

LTC2242-12

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INTERNAL REFERENCE CHARACTERISTICS (Note 4)

PARAMETER CONDITIONS MIN TYP MAX UNITS

VCM Output Voltage IOUT = 0 1.225 1.25 1.275 V

VCM Output Tempco ±35 ppm/°C

VCM Line Regulation 2.375V < VDD < 2.625V 3 mV/V

VCM Output Resistance –1mA < IOUT < 1mA 2 Ω

DIGITAL INPUTS AND DIGITAL OUTPUTS The ● denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 4)


ENCODE INPUTS (ENC+, ENC–)

VID Differential Input Voltage (Note 7) ● 0.2 V

VICM Common Mode Input Voltage Internally SetExternally Set (Note 7) ● 1.2

1.51.5 2.0

VV

RIN Input Resistance 4.8 kΩ

CIN Input Capacitance (Note 7) 2 pF

LOGIC INPUTS (OE, SHDN)

VIH High Level Input Voltage VDD = 2.5V ● 1.7 V

VIL Low Level Input Voltage VDD = 2.5V ● 0.7 V

IIN Input Current VIN = 0V to VDD ● –10 10 μA

CIN Input Capacitance (Note 7) 3 pF

LOGIC OUTPUTS (CMOS MODE)

OVDD = 2.5V

COZ Hi-Z Output Capacitance OE = High (Note 7) 3 pF

ISOURCE Output Source Current VOUT = 0V 37 mA

ISINK Output Sink Current VOUT = 2.5V 23 mA

VOH High Level Output Voltage IO = –10μAIO = –500μA

2.4952.45

VV

VOL Low Level Output Voltage IO = 10μAIO = 500μA

0.0050.07

VV

OVDD = 1.8V

VOH High Level Output Voltage IO = –500μA 1.75 V

VOL Low Level Output Voltage IO = 500μA 0.07 V

LOGIC OUTPUTS (LVDS MODE)

VOD Differential Output Voltage 100Ω Differential Load ● 247 350 454 mV

VOS Output Common Mode Voltage 100Ω Differential Load ● 1.125 1.250 1.375 V

LTC2242-12

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POWER REQUIREMENTS


V DD Analog Supply Voltage (Note 8) ● 2.375 2.5 2.625 V

PSLEEP Sleep Mode Power SHDN = High, OE = High, No CLK 1 mW

PNAP Nap Mode Power SHDN = High, OE = Low, No CLK 28 mW

LVDS OUTPUT MODE

OVDD Output Supply Voltage (Note 8) ● 2.375 2.5 2.625 V

IVDD Analog Supply Current ● 285 320 mA

IOVDD Output Supply Current ● 58 70 mA

PDISS Power Dissipation ● 858 975 mW

CMOS OUTPUT MODE

OVDD Output Supply Voltage (Note 8) ● 0.5 2.5 2.625 V

IVDD Analog Supply Current (Note 7) ● 285 320 mA

PDISS Power Dissipation 740 mW

The ● denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 9)

TIMING CHARACTERISTICS The ● denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 4)


fS Sampling Frequency (Note 8) ● 1 250 MHz

tL ENC Low Time (Note 7) Duty Cycle Stabilizer OffDuty Cycle Stabilizer On

●

●

1.91.5

22

500500

nsns

tH ENC High Time (Note 7) Duty Cycle Stabilizer OffDuty Cycle Stabilizer On

●

●

1.91.5

22

500500

nsns

tAP Sample-and-Hold Aperture Delay 0.4 ns

tOE Output Enable Delay (Note 7) ● 5 10 ns

LVDS OUTPUT MODE

tD ENC to DATA Delay (Note 7) ● 1 1.7 2.8 ns

tC ENC to CLKOUT Delay (Note 7) ● 1 1.7 2.8 ns

DATA to CLKOUT Skew (tC – tD) (Note 7) ● –0.6 0 0.6 ns

Rise Time 0.5 ns

Fall Time 0.5 ns

Pipeline Latency 5 Cycles

CMOS OUTPUT MODE

tD ENC to DATA Delay (Note 7) ● 1 1.7 2.8 ns

tC ENC to CLKOUT Delay (Note 7) ● 1 1.7 2.8 ns

DATA to CLKOUT Skew (tC – tD) (Note 7) ● –0.6 0 0.6 ns

Pipeline Latency

Full Rate CMOS 5 Cycles

Demuxed Interleaved 5 Cycles

Demuxed Simultaneous 5 and 6 Cycles

LTC2242-12

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ELECTRICAL CHARACTERISTICSNote 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: All voltage values are with respect to ground with GND and OGND

wired together (unless otherwise noted).

Note 3: When these pin voltages are taken below GND or above VDD, they

will be clamped by internal diodes. This product can handle input currents

of greater than 100mA below GND or above VDD without latchup.

Note 4: VDD = 2.5V, fSAMPLE = 250MHz, LVDS outputs, differential

ENC+/ENC– = 2VP-P sine wave, input range = 2VP-P with differential

drive, unless otherwise noted.

Note 5: Integral nonlinearity is defi ned as the deviation of a code from

a “best straight line” fi t to the transfer curve. The deviation is measured

from the center of the quantization band.

TYPICAL PERFORMANCE CHARACTERISTICS

Note 6: Offset error is the offset voltage measured from –0.5 LSB when

the output code fl ickers between 0000 0000 0000 and 1111 1111 1111 in

2’s complement output mode.

Note 7: Guaranteed by design, not subject to test.

Note 8: Recommended operating conditions.

Note 9: VDD = 2.5V, fSAMPLE = 250MHz, differential ENC+/ENC– = 2VP-P

sine wave, input range = 1VP-P with differential drive, output CLOAD = 5pF.

Note 10: SNR minimum and typical values are for LVDS mode. Typical

values for CMOS mode are typically 0.3dB lower.

Note 11: SFDR minimum values are for LVDS mode. Typical values are for

both LVDS and CMOS modes.

Note 12: SINAD minimum and typical values are for LVDS mode. Typical

values for CMOS mode are typically 0.3dB lower.

Integral Nonlinearity Differential Nonlinearity8192 Point FFT, fIN = 5MHz, –1dB, 2V Range, LVDS Mode

(TA = 25°C unless otherwise noted, Note 4)

OUTPUT CODE

0

INL (

LS

B)

0

0.5

1.0

4096

224212 G01

–0.5

–1.0

–2.01024 2048 3072

–1.5

2.0

1.5

OUTPUT CODE

0–1.0

DN

L (

LS

B)

–0.8

–0.4

–0.2

0

1.0

0.4

1024 2048

224212 G02

–0.6

0.6

0.8

0.2

3072 4096

FREQUENCY (MHz)

0

AM

PLIT

UD

E (

dB

)

–80

–20

–10

0

20 40 60 80 100

224212 G03

–100

–40

–60

–90

–30

–110

–50

–70

120

LTC2242-12

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TYPICAL PERFORMANCE CHARACTERISTICS

8192 Point FFT, fIN = 70MHz, –1dB, 2V Range, LVDS Mode




8192 Point FFT, fIN = 1GHz, –1dB, 1V Range, LVDS Mode

8192 Point 2-Tone FFT, fIN = 135MHz and 140MHz, –1dB, 2V Range, LVDS Mode

SNR vs Input Frequency, –1dB, LVDS Mode

SFDR (HD2 and HD3) vs Input Frequency, –1dB, LVDS Mode

SFDR (HD4+) vs Input Frequency, –1dB, LVDS Mode


FREQUENCY (MHz)

0

AM

PLIT

UD

E (

dB

)

–80

–20

–10

0

20 40 60 80 100

224212 G04

–100

–40

–60

–90

–30

–110

–50

–70

120

FREQUENCY (MHz)

0

AM

PLIT

UD

E (

dB

)

–80

–20

–10

0

20 40 60 80 100

224212 G05

–100

–40

–60

–90

–30

–110

–50

–70

120

FREQUENCY (MHz)

0

AM

PLIT

UD

E (

dB

)

–80

–20

–10

0

20 40 60 80 100

224212 G06

–100

–40

–60

–90

–30

–110

–50

–70

120

FREQUENCY (MHz)

0

AM

PLIT

UD

E (

dB

)

–80

–20

–10

0

20 40 60 80 100

224212 G07

–100

–40

–60

–90

–30

–110

–50

–70

120

FREQUENCY (MHz)

0

AM

PLIT

UD

E (

dB

)

–80

–20

–10

0

20 40 60 80 100

224212 G08

–100

–40

–60

–90

–30

–110

–50

–70

120

FREQUENCY (MHz)

0

AM

PLIT

UD

E (

dB

)

–80

–20

–10

0

20 40 60 80 100

224212 G09

–100

–40

–60

–90

–30

–110

–50

–70

120


058

SN

R (

dB

FS)

59

61

62

63

600 700 800 900

67

224212 G10

60

100 200 300 400 500 1000

64

65

66

1V RANGE

2V RANGE


0

SFD

R (

dB

FS) 70

80

85

800

224212 G11

60

50

65

75

55

45

40200100 400300 600 700 900500 1000

1V RANGE

2V RANGE


060

SFD

R (

dB

FS)

65

75

80

85

95

100 500 700

224212 G12

70

90

400 9001000200 300 600 800

1V RANGE

2V RANGE

LTC2242-12

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TYPICAL PERFORMANCE CHARACTERISTICSSFDR and SNR vs Sample Rate, 2V Range, fIN = 30MHz, –1dB, LVDS Mode

SFDR vs Input Level, fIN = 70MHz, 2V Range SNR vs SENSE, fIN = 5MHz, –1dB

IVDD vs Sample Rate, 5MHz Sine Wave Input, –1dB

IOVDD vs Sample Rate, 5MHz Sine Wave Input, –1dB


SAMPLE RATE (Msps)

0

90

85

80

75

70

65

60

55150

SFDR

SNR

250

224212 G13

50 100 200 300

SFD

R A

ND

SN

R (

dB

FS)

SENSE PIN (V)

0.5

64

65

66

0.9

224212 G15

63

62

0.6 0.7 0.8 1

61

60

59

SN

R (

dB

FS)

SAMPLE RATE (Msps)

0

I VD

D (

mA

)

250

260

270

150 250

224212 G16

240

230

22050 100 200

280

290

300

2V RANGE 1V RANGE

SAMPLE RATE (Msps)

00

I OV

DD

(m

A)

10

20

30

40

60

50 100 150 200

224212 G17

250

50

CMOS OUTPUTSOVDD = 1.8V

LVDS OUTPUTSOVDD = 2.5V

INPUT LEVEL (dBFS)

–600

SFD

R (

dB

c A

ND

dB

FS)

10

30

40

50

70

–40 –20 –10

224212 G14

20

80

90

60

–50 –30

dBFS

dBc

0

LTC2242-12

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PIN FUNCTIONS(CMOS Mode)

AIN+ (Pins 1, 2): Positive Differential Analog Input.

AIN– (Pins 3, 4): Negative Differential Analog Input.

REFHA (Pins 5, 6): ADC High Reference. Bypass to Pins 7, 8 with 0.1μF ceramic chip capacitor, to Pins 11, 12 with a 2.2μF ceramic capacitor and to ground with 1μF ceramic capacitor.

REFLB (Pins 7, 8): ADC Low Reference. Bypass to Pins 5, 6 with 0.1μF ceramic chip capacitor. Do not connect to Pins 11, 12.

REFHB (Pins 9, 10): ADC High Reference. Bypass to Pins 11, 12 with 0.1μF ceramic chip capacitor. Do not connect to Pins 5, 6.

REFLA (Pins 11, 12): ADC Low Reference. Bypass to Pins 9, 10 with 0.1μF ceramic chip capacitor, to Pins 5, 6 with a 2.2μF ceramic capacitor and to ground with 1μF ceramic capacitor.

VDD (Pins 13, 14, 15, 62, 63): 2.5V Supply. Bypass to GND with 0.1μF ceramic chip capacitors.

GND (Pins 16, 61, 64): ADC Power Ground.

ENC+ (Pin 17): Encode Input. Conversion starts on the positive edge.

ENC– (Pin 18): Encode Complement Input. Conversion starts on the negative edge. Bypass to ground with 0.1μF ceramic for single-ended ENCODE signal.

SHDN (Pin 19): Shutdown Mode Selection Pin. Connecting SHDN to GND and OE to GND results in normal operation with the outputs enabled. Connecting SHDN to GND and OE to VDD results in normal operation with the outputs at high impedance. Connecting SHDN to VDD and OE to GND results in nap mode with the outputs at high impedance. Connecting SHDN to VDD and OE to VDD results in sleep mode with the outputs at high impedance.

OE (Pin 20): Output Enable Pin. Refer to SHDN pin function.

DB0 - DB11 (Pins 21, 22, 23, 24, 27, 28, 29, 30, 31, 32, 35, 36): Digital Outputs, B Bus. DB11 is the MSB. At high impedance in full rate CMOS mode.

OGND (Pins 25, 33, 41, 50): Output Driver Ground.

OVDD (Pins 26, 34, 42, 49): Positive Supply for the Output Drivers. Bypass to ground with 0.1μF ceramic chip capacitor.

OFB (Pin 37): Over/Under Flow Output for B Bus. High when an over or under fl ow has occurred. At high imped-ance in full rate CMOS mode.

CLKOUTB (Pin 38): Data Valid Output for B Bus. In demux mode with interleaved update, latch B bus data on the fall-ing edge of CLKOUTB. In demux mode with simultaneous update, latch B bus data on the rising edge of CLKOUTB. This pin does not become high impedance in full rate CMOS mode.

CLKOUTA (Pin 39): Data Valid Output for A Bus. Latch A bus data on the falling edge of CLKOUTA.

DA0 - DA11 (Pins 40, 43, 44, 45, 46, 47, 48, 51, 52, 53, 54, 55): Digital Outputs, A Bus. DA11 is the MSB.

OFA (Pin 56): Over/Under Flow Output for A Bus. High when an over or under fl ow has occurred.

LVDS (Pin 57): Output Mode Selection Pin. Connecting LVDS to 0V selects full rate CMOS mode. Connecting LVDS to 1/3VDD selects demux CMOS mode with simultaneous update. Connecting LVDS to 2/3VDD selects demux CMOS mode with interleaved update. Connecting LVDS to VDD selects LVDS mode.

MODE (Pin 58): Output Format and Clock Duty Cycle Stabilizer Selection Pin. Connecting MODE to 0V selects offset binary output format and turns the clock duty cycle stabilizer off. Connecting MODE to 1/3VDD selects offset binary output format and turns the clock duty cycle stabilizer on. Connecting MODE to 2/3VDD selects 2’s complement output format and turns the clock duty cycle stabilizer on. Connecting MODE to VDD selects 2’s complement output format and turns the clock duty cycle stabilizer off.

SENSE (Pin 59): Reference Programming Pin. Connecting SENSE to VCM selects the internal reference and a ±0.5V input range. Connecting SENSE to VDD selects the internal reference and a ±1V input range. An external reference greater than 0.5V and less than 1V applied to SENSE selects an input range of ±VSENSE. ±1V is the largest valid input range.

VCM (Pin 60): 1.25V Output and Input Common Mode Bias. Bypass to ground with 2.2μF ceramic chip capacitor.

GND (Exposed Pad) (Pin 65): ADC Power Ground. The exposed pad on the bottom of the package needs to be soldered to ground.

LTC2242-12

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PIN FUNCTIONS(LVDS Mode)

AIN+ (Pins 1, 2): Positive Differential Analog Input.

AIN– (Pins 3, 4): Negative Differential Analog Input.

REFHA (Pins 5, 6): ADC High Reference. Bypass to Pins 7, 8 with 0.1μF ceramic chip capacitor, to Pins 11, 12 with a 2.2μF ceramic capacitor and to ground with 1μF ceramic capacitor.

REFLB (Pins 7, 8): ADC Low Reference. Bypass to Pins 5, 6 with 0.1μF ceramic chip capacitor. Do not connect to Pins 11, 12.

REFHB (Pins 9, 10): ADC High Reference. Bypass to Pins 11, 12 with 0.1μF ceramic chip capacitor. Do not connect to Pins 5, 6.

REFLA (Pins 11, 12): ADC Low Reference. Bypass to Pins 9, 10 with 0.1μF ceramic chip capacitor, to Pins 5, 6 with a 2.2μF ceramic capacitor and to ground with 1μF ceramic capacitor.

VDD (Pins 13, 14, 15, 62, 63): 2.5V Supply. Bypass to GND with 0.1μF ceramic chip capacitors.

GND (Pins 16, 61, 64): ADC Power Ground.

ENC+ (Pin 17): Encode Input. Conversion starts on the positive edge.

ENC– (Pin 18): Encode Complement Input. Conversion starts on the negative edge. Bypass to ground with 0.1μF ceramic for single-ended ENCODE signal.

SHDN (Pin 19): Shutdown Mode Selection Pin. Connecting SHDN to GND and OE to GND results in normal operation with the outputs enabled. Connecting SHDN to GND and OE to VDD results in normal operation with the outputs at high impedance. Connecting SHDN to VDD and OE to GND results in nap mode with the outputs at high impedance. Connecting SHDN to VDD and OE to VDD results in sleep mode with the outputs at high impedance.

OE (Pin 20): Output Enable Pin. Refer to SHDN pin func-tion.

D0–/D0+ to D11–/D11+ (Pins 21, 22, 23, 24, 27, 28, 29, 30, 31, 32, 37, 38, 39, 40, 43, 44, 45, 46, 47, 48, 51, 52, 53, 54): LVDS Digital Outputs. All LVDS outputs require differential 100Ω termination resistors at the LVDS receiver. D11–/D11+ is the MSB.

OGND (Pins 25, 33, 41, 50): Output Driver Ground.

OVDD (Pins 26, 34, 42, 49): Positive Supply for the Out-put Drivers. Bypass to ground with 0.1μF ceramic chip capacitor.

CLKOUT–/CLKOUT+ (Pins 35 to 36): LVDS Data Valid Output. Latch data on rising edge of CLKOUT–, falling edge of CLKOUT+.

OF–/OF+ (Pins 55 to 56): LVDS Over/Under Flow Output. High when an over or under fl ow has occurred.

LVDS (Pin 57): Output Mode Selection Pin. Connecting LVDS to 0V selects full rate CMOS mode. Connecting LVDS to 1/3VDD selects demux CMOS mode with simultaneous update. Connecting LVDS to 2/3VDD selects demux CMOS mode with interleaved update. Connecting LVDS to VDD selects LVDS mode.

MODE (Pin 58): Output Format and Clock Duty Cycle Stabilizer Selection Pin. Connecting MODE to 0V selects offset binary output format and turns the clock duty cycle stabilizer off. Connecting MODE to 1/3VDD selects offset binary output format and turns the clock duty cycle stabilizer on. Connecting MODE to 2/3VDD selects 2’s complement output format and turns the clock duty cycle stabilizer on. Connecting MODE to VDD selects 2’s complement output format and turns the clock duty cycle stabilizer off.

SENSE (Pin 59): Reference Programming Pin. Connecting SENSE to VCM selects the internal reference and a ±0.5V input range. Connecting SENSE to VDD selects the internal reference and a ±1V input range. An external reference greater than 0.5V and less than 1V applied to SENSE selects an input range of ±VSENSE. ±1V is the largest valid input range.

VCM (Pin 60): 1.25V Output and Input Common Mode Bias. Bypass to ground with 2.2μF ceramic chip capacitor.

GND (Exposed Pad) (Pin 65): ADC Power Ground. The exposed pad on the bottom of the package needs to be soldered to ground.

LTC2242-12

11224212fc

FUNCTIONAL BLOCK DIAGRAM

Figure 1. Functional Block Diagram

DIFFREFAMP

REFBUF

2.2μF

1μF

0.1μF 0.1μF

1μF

INTERNAL CLOCK SIGNALSREFH REFL

DIFFERENTIALINPUT

LOW JITTERCLOCKDRIVER

RANGESELECT

1.25VREFERENCE

FIRST PIPELINEDADC STAGE

FIFTH PIPELINEDADC STAGE

FOURTH PIPELINEDADC STAGE

SECOND PIPELINEDADC STAGE

ENC+

REFHAREFLB REFLA REFHB

ENC–

SHIFT REGISTERAND CORRECTION

OEM0DE

OGND

OF

OVDD

D11

D0

CLKOUT

224212 F01

INPUTS/H

SENSE

VCM

AIN–

AIN+

2.2μF

THIRD PIPELINEDADC STAGE

OUTPUTDRIVERS

CONTROLLOGIC

LVDS SHDN

•••

+–

+–

+–+–

VDD

GND

LTC2242-12

12224212fc

TIMING DIAGRAMSLVDS Output Mode Timing

All Outputs Are Differential and Have LVDS Levels

Full-Rate CMOS Output Mode TimingAll Outputs Are Single-Ended and Have CMOS Levels

tH

tD

tC

tL

N – 5 N – 4 N – 3 N – 2 N – 1

tAP

N + 1

N + 2 N + 4

N + 3

NANALOGINPUT

ENC–

ENC+

CLKOUT–

CLKOUT+

D0-D11, OF

224212 TD01

tAP

N + 1

N + 2 N + 4

N + 3

NANALOGINPUT

tH

tD

tC

tL

N – 5 N – 4 N – 3 N – 2 N – 1

ENC–

ENC+

CLKOUTB

CLKOUTA

DA0-DA11, OFA

DB0-DB11, OFB

224212 TD02

HIGH IMPEDANCE

LTC2242-12

13224212fc

TIMING DIAGRAMSDemultiplexed CMOS Outputs with Interleaved UpdateAll Outputs Are Single-Ended and Have CMOS Levels

Demultiplexed CMOS Outputs with Simultaneous UpdateAll Outputs Are Single-Ended and Have CMOS Levels

tH

tD

tC tC

tD

tL

N – 5 N – 3 N – 1

N – 6 N – 4 N – 2

ENC–

ENC+

CLKOUTB

CLKOUTA

DA0-DA11, OFA

DB0-DB11, OFB

224212 TD03

tAP

N + 1

N + 2 N + 4

N + 3

NANALOGINPUT

tH

tD

tC

tD

tL

N – 6 N – 4 N – 2

N – 5 N – 3 N – 1

ENC–

ENC+

CLKOUTB

CLKOUTA

DA0-DA11, OFA

DB0-DB11, OFB

224212 TD04

tAP

N + 1

N + 2 N + 4

N + 3

NANALOGINPUT

LTC2242-12

14224212fc

APPLICATIONS INFORMATIONDYNAMIC PERFORMANCE

Signal-to-Noise Plus Distortion Ratio

The signal-to-noise plus distortion ratio [S/(N + D)] is the ratio between the RMS amplitude of the fundamen-tal input frequency and the RMS amplitude of all other frequency components at the ADC output. The output is band limited to frequencies above DC to below half the sampling frequency.

Signal-to-Noise Ratio

The signal-to-noise ratio (SNR) is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components except the fi rst fi ve harmonics and DC.

Total Harmonic Distortion

Total harmonic distortion is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency. THD is expressed as:

THD= 20Log V22 + V32 + V42 + ...Vn2( )/V1⎛

⎝⎜⎞⎠⎟

where V1 is the RMS amplitude of the fundamental fre-quency and V2 through Vn are the amplitudes of the second through nth harmonics. The THD calculated in this data sheet uses all the harmonics up to the fi fth.

Intermodulation Distortion

If the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearity can produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency.

If two pure sine waves of frequencies fa and fb are ap-plied to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc. The 3rd order intermodulation products are

2fa + fb, 2fb + fa, 2fa – fb and 2fb – fa. The intermodula-tion distortion is defi ned as the ratio of the RMS value of either input tone to the RMS value of the largest 3rd order intermodulation product.

Spurious Free Dynamic Range (SFDR)

Spurious free dynamic range is the peak harmonic or spuri-ous noise that is the largest spectral component excluding the input signal and DC. This value is expressed in decibels relative to the RMS value of a full scale input signal.

Full Power Bandwidth

The full power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3dB for a full scale input signal.

Aperture Delay Time

The time from when a rising ENC+ equals the ENC– voltage to the instant that the input signal is held by the sample and hold circuit.

Aperture Delay Jitter

The variation in the aperture delay time from conversion to conversion. This random variation will result in noise when sampling an AC input. The signal to noise ratio due to the jitter alone will be:

SNRJITTER = –20log (2π • fIN • tJITTER)

CONVERTER OPERATION

As shown in Figure 1, the LTC2242-12 is a CMOS pipelined multi-step converter. The converter has fi ve pipelined ADC stages; a sampled analog input will result in a digitized value fi ve cycles later (see the Timing Diagram section). For optimal performance the analog inputs should be driven differentially. The encode input is differential for improved common mode noise immunity. The LTC2242-12 has two phases of operation, determined by the state of the dif-ferential ENC+/ENC– input pins. For brevity, the text will refer to ENC+ greater than ENC– as ENC high and ENC+ less than ENC– as ENC low.

LTC2242-12

15224212fc

APPLICATIONS INFORMATIONEach pipelined stage shown in Figure 1 contains an ADC, a reconstruction DAC and an interstage residue amplifi er. In operation, the ADC quantizes the input to the stage and the quantized value is subtracted from the input by the DAC to produce a residue. The residue is amplifi ed and output by the residue amplifi er. Successive stages operate out of phase so that when the odd stages are outputting their residue, the even stages are acquiring that residue and vice versa.

When ENC is low, the analog input is sampled differentially directly onto the input sample-and-hold capacitors, inside the “Input S/H” shown in the block diagram. At the instant that ENC transitions from low to high, the sampled input is held. While ENC is high, the held input voltage is buffered by the S/H amplifi er which drives the fi rst pipelined ADC stage. The fi rst stage acquires the output of the S/H dur-ing this high phase of ENC. When ENC goes back low, the fi rst stage produces its residue which is acquired by the second stage. At the same time, the input S/H goes back to acquiring the analog input. When ENC goes back high, the second stage produces its residue which is acquired by the third stage. An identical process is repeated for the third and fourth stages, resulting in a fourth stage residue that is sent to the fi fth stage ADC for fi nal evaluation.

Each ADC stage following the fi rst has additional range to accommodate fl ash and amplifi er offset errors. Results from all of the ADC stages are digitally synchronized such that the results can be properly combined in the correction logic before being sent to the output buffer.

SAMPLE/HOLD OPERATION AND INPUT DRIVE

Sample/Hold Operation

Figure 2 shows an equivalent circuit for the LTC2242-12 CMOS differential sample-and-hold. The analog inputs are connected to the sampling capacitors (CSAMPLE) through NMOS transistors. The capacitors shown attached to each input (CPARASITIC) are the summation of all other capacitance associated with each input.

During the sample phase when ENC is low, the transistors connect the analog inputs to the sampling capacitors and they charge to, and track the differential input voltage. When ENC transitions from low to high, the sampled input

voltage is held on the sampling capacitors. During the hold phase when ENC is high, the sampling capacitors are disconnected from the input and the held voltage is passed to the ADC core for processing. As ENC transitions from high to low, the inputs are reconnected to the sampling capacitors to acquire a new sample. Since the sampling capacitors still hold the previous sample, a charging glitch proportional to the change in voltage between samples will be seen at this time. If the change between the last sample and the new sample is small, the charging glitch seen at the input will be small. If the input change is large, such as the change seen with input frequencies near Nyquist, then a larger charging glitch will be seen.

Common Mode Bias

For optimal performance the analog inputs should be driven differentially. Each input should swing ±0.5V for the 2V range or ±0.25V for the 1V range, around a common mode voltage of 1.25V. The VCM output pin (Pin 60) may be used to provide the common mode bias level. VCM can be tied directly to the center tap of a transformer to set the DC input level or as a reference level to an op amp differential

Figure 2. Equivalent Input Circuit

CSAMPLE2pFRON

14Ω

RON14Ω

VDD

VDD

LTC2242-12

AIN+

224212 F02

CSAMPLE2pF

VDD

AIN–

ENC–

ENC+

1.5V

6k

1.5V

6k

CPARASITIC1.8pF

CPARASITIC1.8pF

10Ω

10Ω

LTC2242-12

16224212fc

APPLICATIONS INFORMATIONdriver circuit. The VCM pin must be bypassed to ground close to the ADC with a 2.2μF or greater capacitor.

Input Drive Impedance

As with all high performance, high speed ADCs, the dy-namic performance of the LTC2242-12 can be infl uenced by the input drive circuitry, particularly the second and third harmonics. Source impedance and input reactance can infl uence SFDR. At the falling edge of ENC, the sample-and-hold circuit will connect the 2pF sampling capacitor to the input pin and start the sampling period. The sampling period ends when ENC rises, holding the sampled input on the sampling capacitor. Ideally the input circuitry should be fast enough to fully charge the sampling capacitor during the sampling period 1/(2fS); however, this is not always possible and the incomplete settling may degrade the SFDR. The sampling glitch has been designed to be as linear as possible to minimize the effects of incomplete settling.

For the best performance, it is recommended to have a source impedance of 100Ω or less for each input. The source impedance should be matched for the differential inputs. Poor matching will result in higher even order harmonics, especially the second.

Input Drive Circuits

Figure 3 shows the LTC2242-12 being driven by an RF transformer with a center tapped secondary. The secondary center tap is DC biased with VCM, setting the ADC input signal at its optimum DC level. Terminating on the trans-former secondary is desirable, as this provides a common mode path for charging glitches caused by the sample and hold. Figure 3 shows a 1:1 turns ratio transformer. Other turns ratios can be used if the source impedance seen by the ADC does not exceed 100Ω for each ADC input. A disadvantage of using a transformer is the loss of low frequency response. Most small RF transformers have poor performance at frequencies below 1MHz.

Figure 4 demonstrates the use of a differential amplifi er to convert a single ended input signal into a differential input signal. The advantage of this method is that it provides low frequency input response; however, the limited gain

bandwidth of most op amps will limit the SFDR at high input frequencies.

Figure 5 shows a capacitively-coupled input circuit. The im-pedance seen by the analog inputs should be matched.

The 25Ω resistors and 12pF capacitor on the analog inputs serve two purposes: isolating the drive circuitry from

Figure 3. Single-Ended to Differential Conversion Using a Transformer

Figure 4. Differential Drive with an Amplifi er

Figure 5. Capacitively-Coupled Drive

25Ω

25Ω25Ω

25Ω

10Ω

0.1μF AIN+

AIN+

AIN–

AIN–

12pF

2.2μF

VCM

LTC2242-12

ANALOGINPUT

0.1μF T11:1

T1 = MA/COM ETC1-1TRESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE

224212 F03

25Ω

25Ω

50Ω

AIN+

AIN+

AIN–

AIN–

12pF

2.2μF

3pF

VCM

LTC2242-12

224212 F04

– –

+ +CM

ANALOGINPUT

HIGH SPEEDDIFFERENTIAL

AMPLIFIER

3pF

0.1μF

25Ω0.1μF

VCM

AIN+

AIN+

AIN–

AIN–

100Ω 100Ω

ANALOGINPUT

12pF

224212 F05

2.2μF

0.1μF25Ω

LTC2242-12

LTC2242-12

17224212fc

APPLICATIONS INFORMATIONthe sample-and-hold charging glitches and limiting the wideband noise at the converter input. For input frequen-cies higher than 100MHz, the capacitor may need to be decreased to prevent excessive signal loss.

The AIN+ and AIN

– inputs each have two pins to reduce package inductance. The two AIN

+ and the two AIN– pins

should be shorted together.

For input frequencies above 100MHz the input circuits of Figure 6, 7 and 8 are recommended. The balun transformer gives better high frequency response than a fl ux coupled center-tapped transformer. The coupling capacitors allow the analog inputs to be DC biased at 1.25V. In Figure 8 the series inductors are impedance matching elements that maximize the ADC bandwidth.

Reference Operation

Figure 9 shows the LTC2242-12 reference circuitry consist-ing of a 1.25V bandgap reference, a difference amplifi er and switching and control circuit. The internal voltage reference can be confi gured for two pin selectable input ranges of 2V (±1V differential) or 1V (±0.5V differential). Tying the SENSE pin to VDD selects the 2V range; typing the SENSE pin to VCM selects the 1V range.

The 1.25V bandgap reference serves two functions: its output provides a DC bias point for setting the common mode voltage of any external input circuitry; additionally, the reference is used with a difference amplifi er to gener-ate the differential reference levels needed by the internal ADC circuitry. An external bypass capacitor is required for the 1.25V reference output, VCM. This provides a high frequency low impedance path to ground for internal and external circuitry.

The difference amplifi er generates the high and low reference for the ADC. High speed switching circuits are connected to these outputs and they must be externally bypassed. Each output has four pins: two each of REFHA and REFHB for the high reference and two each of REFLA and REFLB for the low reference. The multiple output pins are needed to reduce package inductance. Bypass capaci-tors must be connected as shown in Figure 9.

Figure 6. Recommended Front End Circuit for Input Frequencies Between 100MHz and 250MHz

Figure 7. Recommended Front End Circuit for Input Frequencies Between 250MHz and 500MHz

Figure 8. Recommended Front End Circuit for Input Frequencies Above 500MHz

25Ω

25Ω12Ω

12Ω

10Ω

0.1μF AIN+

AIN+

AIN–

AIN–

8pF

2.2μF

VCM

ANALOGINPUT

0.1μF

0.1μF

T1

T1 = MA/COM ETC1-1-13RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE

224212 F06

LTC2242-12

25Ω

10Ω

25Ω

0.1μF AIN+

AIN+

AIN–

AIN–

2.2μF

VCM

ANALOGINPUT

0.1μF

0.1μF

T1

T1 = MA/COM ETC1-1-13RESISTORS, CAPACITORSARE 0402 PACKAGE SIZE

224212 F07

LTC2242-12

25Ω

10Ω

25Ω

0.1μF AIN+

AIN+

AIN–

AIN–

2.2μF

VCM

LTC2242-12

ANALOGINPUT

0.1μF

0.1μF

T1

T1 = MA/COM ETC1-1-13RESISTORS, CAPACITORSARE 0402 PACKAGE SIZE

224212 F08

2.7nH

2.7nH

LTC2242-12

18224212fc

APPLICATIONS INFORMATION

Other voltage ranges in between the pin selectable ranges can be programmed with two external resistors as shown in Figure 10. An external reference can be used by ap-plying its output directly or through a resistor divider to SENSE. It is not recommended to drive the SENSE pin with a logic device. The SENSE pin should be tied to the appropriate level as close to the converter as possible. If

the SENSE pin is driven externally, it should be bypassed to ground as close to the device as possible with a 1μF ceramic capacitor.

Input Range

The input range can be set based on the application. The 2V input range will provide the best signal-to-noise performance while maintaining excellent SFDR. The 1V input range will have better SFDR performance, but the SNR will degrade by 5dB. See the Typical Performance Characteristics section.

Driving the Encode Inputs

The noise performance of the LTC2242-12 can depend on the encode signal quality as much as on the analog input. The ENC+/ENC– inputs are intended to be driven differentially, primarily for noise immunity from com-mon mode noise sources. Each input is biased through a 4.8k resistor to a 1.5V bias. The bias resistors set the DC operating point for transformer coupled drive circuits and can set the logic threshold for single-ended drive circuits.

Any noise present on the encode signal will result in ad-ditional aperture jitter that will be RMS summed with the inherent ADC aperture jitter.

In applications where jitter is critical (high input frequen-cies) take the following into consideration:

1. Differential drive should be used.

2. Use as large an amplitude as possible; if transformer coupled use a higher turns ratio to increase the ampli-tude.

3. If the ADC is clocked with a sinusoidal signal, fi lter the encode signal to reduce wideband noise.

4. Balance the capacitance and series resistance at both encode inputs so that any coupled noise will appear at both inputs as common mode noise. The encode inputs have a common mode range of 1.2V to 2.0V. Each input may be driven from ground to VDD for single-ended drive.

Figure 9. Equivalent Reference Circuit

Figure 10. 1.5V Range ADC

VCM

REFHA

REFLB

SENSETIE TO VDD FOR 2V RANGE;TIE TO VCM FOR 1V RANGE;

RANGE = 2 • VSENSE FOR0.5V < VSENSE < 1V

1.25V

REFLA

REFHB

2.2μF

2.2μF

INTERNAL ADCHIGH REFERENCE

BUFFER

0.1μF

224212 F09

LTC2242-12

2Ω

DIFF AMP

1μF

1μF 0.1μF

INTERNAL ADCLOW REFERENCE

1.25V BANDGAPREFERENCE

1V 0.5V

RANGEDETECT

ANDCONTROL

VCM

SENSE

1.25V

2.2μF8k

12k

0.75V

1μF

224212 F10

LTC2242-12

LTC2242-12

19224212fc


Maximum and Minimum Encode Rates

The maximum encode rate for the LTC2242-12 is 250Msps. For the ADC to operate properly, the encode signal should have a 50% (±5%) duty cycle. Each half cycle must have at least 1.9ns for the ADC internal circuitry to have enough settling time for proper operation. Achieving a precise 50% duty cycle is easy with differential sinusoidal drive using a transformer or using symmetric differential logic such as PECL or LVDS.

An optional clock duty cycle stabilizer circuit can be used if the input clock has a non 50% duty cycle. This circuit uses the rising edge of the ENC+ pin to sample the analog input. The falling edge of ENC+ is ignored and the internal falling edge is generated by a phase-locked loop. The input clock duty cycle can vary from 40% to 60% and the clock duty cycle stabilizer will maintain a constant 50% internal duty

cycle. If the clock is turned off for a long period of time, the duty cycle stabilizer circuit will require one hundred clock cycles for the PLL to lock onto the input clock. To use the clock duty cycle stabilizer, the MODE pin should be connected to 1/3VDD or 2/3VDD using external resistors.

The lower limit of the LTC2242-12 sample rate is determined by droop of the sample-and-hold circuits. The pipelined architecture of this ADC relies on storing analog signals on small valued capacitors. Junction leakage will discharge the capacitors. The specifi ed minimum operating frequency for the LTC2242-12 is 1Msps.

DIGITAL OUTPUTS

Table 1 shows the relationship between the analog input voltage, the digital data bits, and the overfl ow bit.

Figure 11. Transformer Driven ENC+/ENC–

Figure 12a. Single-Ended ENC Drive,Not Recommended for Low Jitter Figure 12b. ENC Drive Using LVDS

VDD

VDDLTC2242-12

224212 F11

VDD

ENC–

ENC+

1.5V BIAS

1.5V BIAS

0.1μF

T1MA/COM

ETC1-1-13CLOCKINPUT

100Ω8.2pF

0.1μF

0.1μF

50Ω

••

50Ω

4.8k

4.8k

TO INTERNALADC CIRCUITS

224212 F12a

ENC–1.5V

VTHRESHOLD = 1.5VENC+

0.1μF

LTC2242-12

224212 F12b

ENC–

ENC+

LVDSCLOCK

100Ω

0.1μF

LTC2242-120.1μF

LTC2242-12

20224212fc

APPLICATIONS INFORMATIONTable 1. Output Codes vs Input Voltage

AIN+ – AIN

–

(2V Range) OFD11 – D0

(Offset Binary)D11 – D0

(2’s Complement)

>+1.000000V+0.999512V+0.999024V

100

1111 1111 11111111 1111 11111111 1111 1110

0111 1111 11110111 1111 11110111 1111 1110

+0.000488V0.000000V

–0.000488V–0.000976V

0000

1000 0000 00011000 0000 00000111 1111 11110111 1111 1110

0000 0000 00010000 0000 00001111 1111 11111111 1111 1110

–0.999512V–1.000000V

<–1.000000V

001

0000 0000 00010000 0000 00000000 0000 0000

1000 0000 00011000 0000 00001000 0000 0000

Digital Output Modes

The LTC2242-12 can operate in several digital output modes: LVDS, CMOS running at full speed, and CMOS demultiplexed onto two buses, each of which runs at half speed. In the demultiplexed CMOS modes the two buses (referred to as bus A and bus B) can either be updated on alternate clock cycles (interleaved mode) or simultaneously (simultaneous mode). For details on the clock timing, refer to the timing diagrams.

The LVDS pin selects which digital output mode the part uses. This pin has a four-level logic input which should be connected to GND, 1/3VDD, 2/3VDD or VDD. An external resistor divider can be used to set the 1/3VDD or 2/3VDD logic values. Table 2 shows the logic states for the LVDS pin.

Table 2. LVDS Pin Function

LVDS DIGITAL OUTPUT MODE

GND Full-Rate CMOS

1/3VDD Demultiplexed CMOS, Simultaneous Update

2/3VDD Demultiplexed CMOS, Interleaved Update

VDD LVDS

Digital Output Buffers (CMOS Modes)

Figure 13a shows an equivalent circuit for a single output buffer in the CMOS output mode. Each buffer is powered by OVDD and OGND, which are isolated from the ADC power and ground. The additional N-channel transistor in the output driver allows operation down to voltages as low as 0.5V. The internal resistor in series with the output makes the output appear as 50Ω to external circuitry and may eliminate the need for external damping resistors.

As with all high speed/high resolution converters, the digital output loading can affect the performance. The digital outputs of the LTC2242-12 should drive a minimal capacitive load to avoid possible interaction between the digital outputs and sensitive input circuitry. The output should be buffered with a device such as an 74VCX245 CMOS latch. For full speed operation the capacitive load should be kept under 10pF.

Lower OVDD voltages will also help reduce interference from the digital outputs.

Digital Output Buffers (LVDS Mode)

Figure 13b shows an equivalent circuit for a differential output pair in the LVDS output mode. A 3.5mA current is steered from OUT+ to OUT– or vice versa which creates a ±350mV differential voltage across the 100Ω termination resistor at the LVDS receiver. A feedback loop regulates the common mode output voltage to 1.25V. For proper operation each LVDS output pair needs an external 100Ω termination resistor, even if the signal is not used (such as OF+/OF– or CLKOUT+/CLKOUT–). To minimize noise the PC board traces for each LVDS output pair should be routed close together. To minimize clock skew all LVDS PC board traces should have about the same length.

LTC2242-12

21224212fc


Data Format

The LTC2242-12 parallel digital output can be selected for offset binary or 2’s complement format. The format is selected with the MODE pin. Connecting MODE to GND or 1/3VDD selects offset binary output format. Connecting MODE to 2/3VDD or VDD selects 2’s complement output format. An external resistor divider can be used to set the 1/3VDD or 2/3VDD logic values. Table 3 shows the logic states for the MODE pin.

Table 3. MODE Pin Function

MODE PIN OUTPUT FORMATCLOCK DUTY

CYCLE STABILIZER

0 Offset Binary Off

1/3VDD Offset Binary On

2/3VDD 2’s Complement On

VDD 2’s Complement Off

Overfl ow Bit

An overfl ow output bit indicates when the converter is overranged or underranged. In CMOS mode, a logic high on the OFA pin indicates an overfl ow or underfl ow on the A data bus, while a logic high on the OFB pin indicates an overfl ow or underfl ow on the B data bus. In LVDS mode, a differential logic high on the OF+/OF– pins indicates an overfl ow or underfl ow.

Output Clock

The ADC has a delayed version of the ENC+ input available as a digital output, CLKOUT. The CLKOUT pin can be used

Figure 13b. Digital Output in LVDS Mode

Figure 13a. Digital Output Buffer in CMOS Mode

to synchronize the converter data to the digital system. This is necessary when using a sinusoidal encode. In all CMOS modes, A bus data will be updated just after CLKOUTA rises and can be latched on the falling edge of CLKOUTA. In demux CMOS mode with interleaved update, B bus data will be updated just after CLKOUTB rises and can be latched on the falling edge of CLKOUTB. In demux CMOS mode with simultaneous update, B bus data will be updated just after CLKOUTB falls and can be latched on the rising edge of CLKOUTB. In LVDS mode, data will be updated just after CLKOUT+/CLKOUT– rises and can be latched on the falling edge of CLKOUT+/CLKOUT–.

Output Driver Power

Separate output power and ground pins allow the output drivers to be isolated from the analog circuitry. The power supply for the digital output buffers, OVDD, should be tied to the same power supply as for the logic being driven. For example if the converter is driving a DSP powered by a 1.8V supply then OVDD should be tied to that same 1.8V supply.

In the CMOS output mode, OVDD can be powered with any voltage up to 2.625V. OGND can be powered with any voltage from GND up to 1V and must be less than OVDD. The logic outputs will swing between OGND and OVDD.

In the LVDS output mode, OVDD should be connected to a 2.5V supply and OGND should be connected to GND.

LTC2242-12

2242 F13a

OVDD

VDD VDD

0.1μF

43Ω TYPICALDATAOUTPUT

OGND

OVDD 0.5V TO 2.625V

PREDRIVERLOGIC

DATAFROMLATCH

OE

LTC2242-12

224212 F13b

OVDD

LVDSRECEIVER

OGND

1.25V

D

D

D

D

OUT+

0.1μF

2.5V

OUT–

100Ω+

–

3.5mA

10k 10k

LTC2242-12

22224212fc

APPLICATIONS INFORMATIONOutput Enable

The outputs may be disabled with the output enable pin, OE. In CMOS or LVDS output modes OE high disables all data outputs including OF and CLKOUT. The data access and bus relinquish times are too slow to allow the outputs to be enabled and disabled during full speed operation. The output Hi-Z state is intended for use during long periods of inactivity.

The Hi-Z state is not a truly open circuit; the output pins that make an LVDS output pair have a 20k resistance be-tween them. Therefore in the CMOS output mode, adjacent data bits will have 20k resistance in between them, even in the Hi-Z state.

Sleep and Nap Modes

The converter may be placed in shutdown or nap modes to conserve power. Connecting SHDN to GND results in normal operation. Connecting SHDN to VDD and OE to VDD results in sleep mode, which powers down all circuitry including the reference and typically dissipates 1mW. When exiting sleep mode it will take milliseconds for the output data to become valid because the reference capacitors have to recharge and stabilize. Connecting SHDN to VDD and OE to GND results in nap mode, which typically dis-sipates 28mW. In nap mode, the on-chip reference circuit is kept on, so that recovery from nap mode is faster than that from sleep mode, typically taking 100 clock cycles. In both sleep and nap mode all digital outputs are disabled and enter the Hi-Z state.

GROUNDING AND BYPASSING

The LTC2242-12 requires a printed circuit board with a clean unbroken ground plane. A multilayer board with an internal ground plane is recommended. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital signal alongside an analog signal or underneath the ADC.

High quality ceramic bypass capacitors should be used at the VDD, OVDD, VCM, REFHA, REFHB, REFLA and REFLB pins. Bypass capacitors must be located as close to the

pins as possible. Of particular importance are the capaci-tors between REFHA and REFLB and between REFHB and REFLA. These capacitors should be as close to the device as possible (1.5mm or less). Size 0402 ceramic capacitors are recommended. The 2.2μF capacitor between REFHA and REFLA can be somewhat further away. The traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible.

The LTC2242-12 differential inputs should run parallel and close to each other. The input traces should be as short as possible to minimize capacitance and to minimize noise pickup.

HEAT TRANSFER

Most of the heat generated by the LTC2242-12 is trans-ferred from the die through the bottom-side exposed pad and package leads onto the printed circuit board. For good electrical and thermal performance, the exposed pad should be soldered to a large grounded pad on the PC board. It is critical that all ground pins are connected to a ground plane of suffi cient area.

Clock Sources for Undersampling

Undersampling is especially demanding on the clock source and the higher the input frequency, the greater the sensitivity to clock jitter or phase noise. A clock source that degrades SNR of a full-scale signal by 1dB at 70MHz will degrade SNR by 3dB at 140MHz, and 4.5dB at 190MHz.

In cases where absolute clock frequency accuracy is relatively unimportant and only a single ADC is required, a canned oscillator from vendors such as Saronix or Vectron can be placed close to the ADC and simply connected directly to the ADC. If there is any distance to the ADC, some source termination to reduce ringing that may occur even over a fraction of an inch is advisable. You must not allow the clock to overshoot the supplies or performance will suffer. Do not fi lter the clock signal with a narrow band fi lter unless you have a sinusoidal clock source, as the rise and fall time artifacts present in typical digital clock signals will be translated into phase noise.

LTC2242-12

23224212fc

APPLICATIONS INFORMATIONThe lowest phase noise oscillators have single-ended sinusoidal outputs, and for these devices the use of a fi lter close to the ADC may be benefi cial. This fi lter should be close to the ADC to both reduce roundtrip refl ection times, as well as reduce the susceptibility of the traces between the fi lter and the ADC. If the circuit is sensitive to close-in phase noise, the power supply for oscillators and any buffers must be very stable, or propagation de-lay variation with supply will translate into phase noise. Even though these clock sources may be regarded as digital devices, do not operate them on a digital supply. If your clock is also used to drive digital devices such as an FPGA, you should locate the oscillator, and any clock fan-out devices close to the ADC, and give the routing to the ADC precedence. The clock signals to the FPGA should have series termination at the driver to prevent high frequency noise from the FPGA disturbing the sub-

strate of the clock fan-out device. If you use an FPGA as a programmable divider, you must re-time the signal using the original oscillator, and the re-timing fl ip-fl op as well as the oscillator should be close to the ADC, and powered with a very quiet supply.

For cases where there are multiple ADCs, or where the clock source originates some distance away, differential clock distribution is advisable. This is advisable both from the perspective of EMI, but also to avoid receiving noise from digital sources both radiated, as well as propagated in the waveguides that exist between the layers of multilayer PCBs. The differential pairs must be close together and distanced from other signals. The differential pair should be guarded on both sides with copper distanced at least 3x the distance between the traces, and grounded with vias no more than 1/4 inch apart.

LTC2242-12

24224212fc


Eval

uati

on C

ircu

it S

chem

atic

of

the

LTC

2242

-12

AIN

+

AIN

+

AIN

–

AIN

–

REFH

A

REFH

A

REFL

B

REFL

B

REFH

B

REFH

B

REFL

A

REFL

A

C19

0.1

F

2 1 4 3 6 5 8 7

10 9

12

11

56

55

54

53

52

51

48

47

46

45

44

43

40

39

38

37

36

35

32

31

30

29

28

27

24

23

22

21

R17

100

R3

100

R7

1k

R37

BLM

18B

B470S

N1D

R38

100

R39

100

R40

100

R42

100

R43

100

R18

100

R19

100

R20

100

R21

100

R22

100

R28 1

00

R30 1

00

24

OF+

OF–

D11

+

D11

–

D10

+

D10

–

D9

+

D9

–

D8

+

D8

–

D7

+

D7

–

D6

+

D6

–

D5

+

D5

–

CLK

OU

T+

CLK

OU

T–

D4

+

D4

–

D3

+

D3

–

D2

+

D2

–

D1

+

D1

–

D0

+

D0

–

LTC

2242-1

2

GND

GND

GND

GND

VDD

VDD

VDD

VDD

VDD

65

64

61

16

63

62

15

14

13

C26 0

.1F

C25 0

.1F

2.5

V

OVDD

OVDD

OVDD

OVDD

OGND

OGND

OGND

OGND

25

33

41

50

26

34

42

49

TP

6V

CM

EN

C+

EN

C–

SH

DN

OE

SEN

SE

MO

DE

LVD

S

VC

M

C20 0

.1F

C21 0

.1F

C23 0

.1F

C22 0

.1F

TP

1EX

T R

EF

TP

2G

ND

SH

DN

3

VD

D 1

GN

D 5

4 O

E

2 V

DD

6 G

ND

2.5

V 1

VC

M 3

EX

T R

EF

5

2 4 6

17

18 60 19

20

59

58

57

2.5

V

2.5

V

2.5

V

R24

1k

J4S

EN

SE

1

VD

D 3

GN

D 5

2 4 2

/3

6 1

/3

J2M

OD

E

R6 1

k

R8 1

k

LT1763C

DE-2

.5

IN IN SH

DN

VO

VO

10

11 8

SEN

2

21

3 5 6B

YP

GN

DG

P

GP

7

C38

0.0

1F

C34

0.1

F

C36

4.7

F

J6A

UX

PW

RC

ON

NEC

TO

R

C24

10

F

+2.5

V

+3.3

V3.3

V T

P5

GN

D T

P4

2.5

V T

P3

(NO

TU

RR

ET)

1 2 3

EN

12

EN

34

EN

56

EN

78

EN

I 1N

I 1P

I 2N

I 2P

I 3N

I 3P

I 4N

I 4P

I 5N

I 5P

I 6N

I 6P

I 7N

I 7P

I 8N

I 8P

VB

B

O1N

O1P

O2N

O2P

O3N

O3P

O4N

O4P

O5N

O5P

O6N

O6P

O7N

O7P

O8N

O8P

VC1

VC2

VC3

VC4

VC5

12

25

26

47

48

VE1

VE2

VE3

VE4

VE5

1

2

23

36

37

U3 F

INII

08

3.3

V

EN

12

EN

34

EN

56

EN

78

EN

I 1N

I 1P

I 2N

I 2P

I 3N

I 3P

I 4N

I 4P

I 5N

I 5P

I 6N

I 6P

I 7N

I 7P

I 8N

I 8P

VB

B

O1N

O1P

O2N

O2P

O3N

O3P

O4N

O4P

O5N

O5P

O6N

O6P

O7N

O7P

O8N

O8P

VC1

VC2

VC3

VC4

VC5

12

25

26

47

48

VE1

VE2

VE3

VE4

VE5

1

2

23

36

37

U3 F

INII

08

3.3

V3

22

27

46

13 4 5 6 7 8 9

10

11

14

15

16

17

18

19

20

21

45

44

43

42

41

40

39

38

35

34

33

32

31

30

29

28

45

44

43

42

41

40

39

38

35

34

33

32

31

30

29

28

3

22

27

46

13 4 5 6 7 8 9

10

11

14

15

16

17

18

19

20

21 2

4

2 4 6 8

10

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

42

44

46

48

50

52

54

1 3 5 7 9 11

13

15

17

19

21

23

25

27

29

31

33

35

37

39

41

43

45

47

49

51

53

56

58

60

62

64

66

68

70

72

74

76

78

80

82

84

86

88

90

92

94

96

98

100

55

57

59

61

63

65

67

69

71

73

75

77

79

81

83

85

87

89

91

93

95

97

99

LVD

S B

UFF

ER

BY

PA

SS

C28

0.1

F

C29

0.1

F

3.3

V

C30

0.1

F

C31

0.1

F

C32

0.1

F

C33

0.1

F

C5

0.1

F

C8

0.1

F

R16

100k

VC

C

24LC

02S

T

GN

D 4

22

42

12

AI0

1

8

ARRAYEEPROM

SC

L

SD

A

WP

A2

A1

A0

6 5 7 3 2 1

C27

0.1

F

R46

4990

R29

4990

2.5

V

R26

4990

R1

49.9

R2

49.9

R4

4.9

9

R5

4.9

9

J7EN

CO

DE

CLK

C3

0.1

FC

11

0.1

F

C4

1.8

pFR

41

100

C13

0.1

F

C14

0.1

F

C15

1F

C16

1F

C17

2.2

F

R23

100

C12

0.1

F

C9

1.8

pF

R11

49.9

R12

49.9

R13

4.9

9

R14

4.9

9

R9

12.4

R10

12.4

C18

2.2

F

C10

0.1

FR

15

49.9

T2

MA

BA

-007159-0

00000

R27

49.9

AIN

C6

0.1

FJ5 SM

A

C2

0.1

F

C7

0.1

F

SM

A

C1

0.1

F

T1

MA

BA

-007159-0

00000

VER

SIO

N

DEV

ICE

BIT

S

SA

MP

LE R

ATE

DC

997B

-A

LTC

2242-1

2

12

250M

sps

DC

997B

-B

LTC

2241-1

2

12

210M

sps

DC

997B

-C

LTC

2240-1

2

12

170M

sps

DC

997B

-D

LTC

2242-1

0

10

250M

sps

DC

997B

-E

LTC

2241-1

0

10

210M

sps

DC

997B

-F

LTC

2240-1

0

10

170M

sps

R25

1k

U5

SJ

LTC2242-12

25224212fc

APPLICATIONS INFORMATIONSilkscreen Top Layer 2 GND Plane

Layer 1 Component Side Layer 3 Power/Ground Plane

LTC2242-12

26224212fc

APPLICATIONS INFORMATIONLayer 4 Power/Ground Planes

Layer 5 Power/Ground Planes

LTC2242-12

27224212fc

Layer Back Solder Side

Silk Screen Back, Solder Side


LTC2242-12

28224212fc

PACKAGE DESCRIPTIONPlease refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

9 .00 ± 0.10(4 SIDES)

NOTE:1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION WNJR-52. ALL DIMENSIONS ARE IN MILLIMETERS3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT4. EXPOSED PAD SHALL BE SOLDER PLATED5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 6. DRAWING NOT TO SCALE

PIN 1 TOP MARK(SEE NOTE 5)

0.40 ± 0.10

6463

12

BOTTOM VIEW—EXPOSED PAD

7.15 ± 0.10

7.15 ± 0.10

7.50 REF(4-SIDES)

0.75 ± 0.05R = 0.10

TYP

R = 0.115TYP

0.25 ± 0.05

0.50 BSC

0.200 REF

0.00 – 0.05

(UP64) QFN 0406 REV C

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONSAPPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

0.70 ±0.05

7.50 REF(4 SIDES)

7.15 ±0.05

7.15 ±0.05

8.10 ±0.05 9.50 ±0.05

0.25 ±0.050.50 BSC

PACKAGE OUTLINE

PIN 1CHAMFER

C = 0.35

UP Package64-Lead Plastic QFN (9mm × 9mm)

(Reference LTC DWG # 05-08-1705 Rev C)

LTC2242-12

29224212fc

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

REVISION HISTORYREV DATE DESCRIPTION PAGE NUMBER

C 10/11 Corrected axis label for G14 in Typical Performance Characteristics

Changed pin names on schematic drawing

8

24

(Revision history begins at Rev C)

LTC2242-12

30224212fc

Linear Technology Corporation1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2006

LT 1011 REV C • PRINTED IN USA

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LTC2242-12 - 12-Bit, 250Msps ADC - analog.com · VID Differential Input Voltage (Note 7) 0.2 V VICM Common Mode Input Voltage Internally Set Externally Set (Note 7) ... V DD Analog